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Merge tag 'pci-v5.18-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci
Pull pci updates from Bjorn Helgaas: "Enumeration: - Move the VGA arbiter from drivers/gpu to drivers/pci because it's PCI-specific, not GPU-specific (Bjorn Helgaas) - Select the default VGA device consistently whether it's enumerated before or after VGA arbiter init, which fixes arches that enumerate PCI devices late (Huacai Chen) Resource management: - Support BAR sizes up to 8TB (Dongdong Liu) PCIe native device hotplug: - Fix "Command Completed" tracking to avoid spurious timouts when powering off empty slots (Liguang Zhang) - Quirk Qualcomm devices that don't implement Command Completed correctly, again to avoid spurious timeouts (Manivannan Sadhasivam) Peer-to-peer DMA: - Add Intel 3rd Gen Intel Xeon Scalable Processors to whitelist (Michael J. Ruhl) APM X-Gene PCIe controller driver: - Revert generic DT parsing changes that broke some machines in the field (Marc Zyngier) Freescale i.MX6 PCIe controller driver: - Allow controller probe to succeed even when no devices currently present to allow hot-add later (Fabio Estevam) - Enable power management on i.MX6QP (Richard Zhu) - Assert CLKREQ# on i.MX8MM so enumeration doesn't hang when no device is connected (Richard Zhu) Marvell Aardvark PCIe controller driver: - Fix MSI and MSI-X support (Marek Behún, Pali Rohár) - Add support for ERR and PME interrupts (Pali Rohár) Marvell MVEBU PCIe controller driver: - Add DT binding and support for "num-lanes" (Pali Rohár) - Add support for INTx interrupts (Pali Rohár) Microsoft Hyper-V host bridge driver: - Avoid unnecessary hypercalls when unmasking IRQs on ARM64 (Boqun Feng) Qualcomm PCIe controller driver: - Add SM8450 DT binding and driver support (Dmitry Baryshkov) Renesas R-Car PCIe controller driver: - Help the controller get to the L1 state since the hardware can't do it on its own (Marek Vasut) - Return PCI_ERROR_RESPONSE (~0) for reads that fail on PCIe (Marek Vasut) SiFive FU740 PCIe controller driver: - Drop redundant '-gpios' from DT GPIO lookup (Ben Dooks) - Force 2.5GT/s for initial device probe (Ben Dooks) Socionext UniPhier Pro5 controller driver: - Add NX1 DT binding and driver support (Kunihiko Hayashi) Synopsys DesignWare PCIe controller driver: - Restore MSI configuration so MSI works after resume (Jisheng Zhang)" * tag 'pci-v5.18-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (94 commits) x86/PCI: Add #includes to asm/pci_x86.h PCI: ibmphp: Remove unused assignments PCI: cpqphp: Remove unused assignments PCI: fu740: Remove unused assignments PCI: kirin: Remove unused assignments PCI: Remove unused assignments PCI: Declare pci_filp_private only when HAVE_PCI_MMAP PCI: Avoid broken MSI on SB600 USB devices PCI: fu740: Force 2.5GT/s for initial device probe PCI: xgene: Revert "PCI: xgene: Fix IB window setup" PCI: xgene: Revert "PCI: xgene: Use inbound resources for setup" PCI: imx6: Assert i.MX8MM CLKREQ# even if no device present PCI: imx6: Invoke the PHY exit function after PHY power off PCI: rcar: Use PCI_SET_ERROR_RESPONSE after read which triggered an exception PCI: rcar: Finish transition to L1 state in rcar_pcie_config_access() PCI: dwc: Restore MSI Receiver mask during resume PCI: fu740: Drop redundant '-gpios' from DT GPIO lookup PCI/VGA: Replace full MIT license text with SPDX identifier PCI/VGA: Use unsigned format string to print lock counts PCI/VGA: Log bridge control messages when adding devices ...
2 parents 636f64d + 611f841 commit 148a650

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Documentation/devicetree/bindings/pci/mvebu-pci.txt

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Original file line numberDiff line numberDiff line change
@@ -77,9 +77,15 @@ and the following optional properties:
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- marvell,pcie-lane: the physical PCIe lane number, for ports having
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multiple lanes. If this property is not found, we assume that the
7979
value is 0.
80+
- num-lanes: number of SerDes PCIe lanes for this link (1 or 4)
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- reset-gpios: optional GPIO to PERST#
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- reset-delay-us: delay in us to wait after reset de-assertion, if not
8283
specified will default to 100ms, as required by the PCIe specification.
84+
- interrupt-names: list of interrupt names, supported are:
85+
- "intx" - interrupt line triggered by one of the legacy interrupt
86+
- interrupts or interrupts-extended: List of the interrupt sources which
87+
corresponding to the "interrupt-names". If non-empty then also additional
88+
'interrupt-controller' subnode must be defined.
8389

8490
Example:
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@@ -141,6 +147,7 @@ pcie-controller {
141147
interrupt-map = <0 0 0 0 &mpic 58>;
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marvell,pcie-port = <0>;
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marvell,pcie-lane = <0>;
150+
num-lanes = <1>;
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/* low-active PERST# reset on GPIO 25 */
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reset-gpios = <&gpio0 25 1>;
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/* wait 20ms for device settle after reset deassertion */
@@ -161,6 +168,7 @@ pcie-controller {
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interrupt-map = <0 0 0 0 &mpic 59>;
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marvell,pcie-port = <0>;
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marvell,pcie-lane = <1>;
171+
num-lanes = <1>;
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clocks = <&gateclk 6>;
165173
};
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@@ -177,6 +185,7 @@ pcie-controller {
177185
interrupt-map = <0 0 0 0 &mpic 60>;
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marvell,pcie-port = <0>;
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marvell,pcie-lane = <2>;
188+
num-lanes = <1>;
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clocks = <&gateclk 7>;
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};
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@@ -193,6 +202,7 @@ pcie-controller {
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interrupt-map = <0 0 0 0 &mpic 61>;
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marvell,pcie-port = <0>;
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marvell,pcie-lane = <3>;
205+
num-lanes = <1>;
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clocks = <&gateclk 8>;
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};
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@@ -209,6 +219,7 @@ pcie-controller {
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interrupt-map = <0 0 0 0 &mpic 62>;
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marvell,pcie-port = <1>;
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marvell,pcie-lane = <0>;
222+
num-lanes = <1>;
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clocks = <&gateclk 9>;
213224
};
214225

@@ -225,6 +236,7 @@ pcie-controller {
225236
interrupt-map = <0 0 0 0 &mpic 63>;
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marvell,pcie-port = <1>;
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marvell,pcie-lane = <1>;
239+
num-lanes = <1>;
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clocks = <&gateclk 10>;
229241
};
230242

@@ -241,6 +253,7 @@ pcie-controller {
241253
interrupt-map = <0 0 0 0 &mpic 64>;
242254
marvell,pcie-port = <1>;
243255
marvell,pcie-lane = <2>;
256+
num-lanes = <1>;
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clocks = <&gateclk 11>;
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};
246259

@@ -257,6 +270,7 @@ pcie-controller {
257270
interrupt-map = <0 0 0 0 &mpic 65>;
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marvell,pcie-port = <1>;
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marvell,pcie-lane = <3>;
273+
num-lanes = <1>;
260274
clocks = <&gateclk 12>;
261275
};
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@@ -273,6 +287,7 @@ pcie-controller {
273287
interrupt-map = <0 0 0 0 &mpic 99>;
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marvell,pcie-port = <2>;
275289
marvell,pcie-lane = <0>;
290+
num-lanes = <1>;
276291
clocks = <&gateclk 26>;
277292
};
278293

@@ -289,6 +304,7 @@ pcie-controller {
289304
interrupt-map = <0 0 0 0 &mpic 103>;
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marvell,pcie-port = <3>;
291306
marvell,pcie-lane = <0>;
307+
num-lanes = <1>;
292308
clocks = <&gateclk 27>;
293309
};
294310
};

Documentation/devicetree/bindings/pci/qcom,pcie.txt

Lines changed: 21 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -15,6 +15,8 @@
1515
- "qcom,pcie-sc8180x" for sc8180x
1616
- "qcom,pcie-sdm845" for sdm845
1717
- "qcom,pcie-sm8250" for sm8250
18+
- "qcom,pcie-sm8450-pcie0" for PCIe0 on sm8450
19+
- "qcom,pcie-sm8450-pcie1" for PCIe1 on sm8450
1820
- "qcom,pcie-ipq6018" for ipq6018
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2022
- reg:
@@ -169,6 +171,24 @@
169171
- "ddrss_sf_tbu" PCIe SF TBU clock
170172
- "pipe" PIPE clock
171173

174+
- clock-names:
175+
Usage: required for sm8450-pcie0 and sm8450-pcie1
176+
Value type: <stringlist>
177+
Definition: Should contain the following entries
178+
- "aux" Auxiliary clock
179+
- "cfg" Configuration clock
180+
- "bus_master" Master AXI clock
181+
- "bus_slave" Slave AXI clock
182+
- "slave_q2a" Slave Q2A clock
183+
- "tbu" PCIe TBU clock
184+
- "ddrss_sf_tbu" PCIe SF TBU clock
185+
- "pipe" PIPE clock
186+
- "pipe_mux" PIPE MUX
187+
- "phy_pipe" PIPE output clock
188+
- "ref" REFERENCE clock
189+
- "aggre0" Aggre NoC PCIe0 AXI clock, only for sm8450-pcie0
190+
- "aggre1" Aggre NoC PCIe1 AXI clock
191+
172192
- resets:
173193
Usage: required
174194
Value type: <prop-encoded-array>
@@ -246,7 +266,7 @@
246266
- "ahb" AHB reset
247267

248268
- reset-names:
249-
Usage: required for sc8180x, sdm845 and sm8250
269+
Usage: required for sc8180x, sdm845, sm8250 and sm8450
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Value type: <stringlist>
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Definition: Should contain the following entries
252272
- "pci" PCIe core reset

Documentation/devicetree/bindings/pci/socionext,uniphier-pcie-ep.yaml

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@@ -20,7 +20,9 @@ allOf:
2020

2121
properties:
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compatible:
23-
const: socionext,uniphier-pro5-pcie-ep
23+
enum:
24+
- socionext,uniphier-pro5-pcie-ep
25+
- socionext,uniphier-nx1-pcie-ep
2426

2527
reg:
2628
minItems: 4
@@ -41,20 +43,26 @@ properties:
4143
- const: atu
4244

4345
clocks:
46+
minItems: 1
4447
maxItems: 2
4548

4649
clock-names:
47-
items:
48-
- const: gio
49-
- const: link
50+
oneOf:
51+
- items: # for Pro5
52+
- const: gio
53+
- const: link
54+
- const: link # for NX1
5055

5156
resets:
57+
minItems: 1
5258
maxItems: 2
5359

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reset-names:
55-
items:
56-
- const: gio
57-
- const: link
61+
oneOf:
62+
- items: # for Pro5
63+
- const: gio
64+
- const: link
65+
- const: link # for NX1
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5967
num-ib-windows:
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const: 16

Documentation/gpu/vgaarbiter.rst

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@@ -100,7 +100,7 @@ In-kernel interface
100100
.. kernel-doc:: include/linux/vgaarb.h
101101
:internal:
102102

103-
.. kernel-doc:: drivers/gpu/vga/vgaarb.c
103+
.. kernel-doc:: drivers/pci/vgaarb.c
104104
:export:
105105

106106
libpciaccess

MAINTAINERS

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@@ -14938,6 +14938,7 @@ F: drivers/pci/controller/mobiveil/pcie-mobiveil*
1493814938

1493914939
PCI DRIVER FOR MVEBU (Marvell Armada 370 and Armada XP SOC support)
1494014940
M: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
14941+
M: Pali Rohár <pali@kernel.org>
1494114942
L: linux-pci@vger.kernel.org
1494214943
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
1494314944
S: Maintained

arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h

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@@ -1380,8 +1380,6 @@
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13811381
#define PCIE_IDVAL3_REG 0x43c
13821382
#define IDVAL3_CLASS_CODE_MASK 0xffffff
1383-
#define IDVAL3_SUBCLASS_SHIFT 8
1384-
#define IDVAL3_CLASS_SHIFT 16
13851383

13861384
#define PCIE_DLSTATUS_REG 0x1048
13871385
#define DLSTATUS_PHYLINKUP (1 << 13)

arch/mips/pci/fixup-sb1250.c

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@@ -75,7 +75,7 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SIBYTE, PCI_DEVICE_ID_BCM1250_PCI,
7575
*/
7676
static void quirk_sb1250_ht(struct pci_dev *dev)
7777
{
78-
dev->class = PCI_CLASS_BRIDGE_PCI << 8;
78+
dev->class = PCI_CLASS_BRIDGE_PCI_NORMAL;
7979
}
8080
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SIBYTE, PCI_DEVICE_ID_BCM1250_HT,
8181
quirk_sb1250_ht);

arch/mips/pci/pci-bcm63xx.c

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Original file line numberDiff line numberDiff line change
@@ -186,7 +186,7 @@ static int __init bcm63xx_register_pcie(void)
186186
/* setup class code as bridge */
187187
val = bcm_pcie_readl(PCIE_IDVAL3_REG);
188188
val &= ~IDVAL3_CLASS_CODE_MASK;
189-
val |= (PCI_CLASS_BRIDGE_PCI << IDVAL3_SUBCLASS_SHIFT);
189+
val |= PCI_CLASS_BRIDGE_PCI_NORMAL;
190190
bcm_pcie_writel(val, PCIE_IDVAL3_REG);
191191

192192
/* disable bar1 size */

arch/powerpc/platforms/powernv/pci.c

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@@ -815,7 +815,7 @@ void pnv_pci_shutdown(void)
815815
/* Fixup wrong class code in p7ioc and p8 root complex */
816816
static void pnv_p7ioc_rc_quirk(struct pci_dev *dev)
817817
{
818-
dev->class = PCI_CLASS_BRIDGE_PCI << 8;
818+
dev->class = PCI_CLASS_BRIDGE_PCI_NORMAL;
819819
}
820820
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_IBM, 0x3b9, pnv_p7ioc_rc_quirk);
821821

arch/powerpc/sysdev/fsl_pci.c

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@@ -55,7 +55,7 @@ static void quirk_fsl_pcie_early(struct pci_dev *dev)
5555
if ((hdr_type & 0x7f) != PCI_HEADER_TYPE_BRIDGE)
5656
return;
5757

58-
dev->class = PCI_CLASS_BRIDGE_PCI << 8;
58+
dev->class = PCI_CLASS_BRIDGE_PCI_NORMAL;
5959
fsl_pcie_bus_fixup = 1;
6060
return;
6161
}

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