Quinta

The project will be built for the Nexys A7-100T FPGA.

(todo: add beq comparition)

General

• fetch_stage
• decode_stage
• execute_stage
• mem_stage
• wb_stage
• decompressor
• instruction_memory
• control
• data_memory
• imm_gen
• registers
• Branches
• Forwarding
• Hazard

Phase1 instructions

• INSTR_LUI
• INSTR_BEQ
• INSTR_BNE
• INSTR_BLT
• INSTR_BGE
• INSTR_BLTU
• INSTR_BGEU
• INSTR_LW
• INSTR_SW
• INSTR_ADDI
• INSTR_SLTI
• INSTR_SLTIU
• INSTR_XORI
• INSTR_ORI
• INSTR_ANDI
• INSTR_SLLI
• INSTR_SRLI
• INSTR_SRAI
• INSTR_ADD
• INSTR_SUB
• INSTR_SLL
• INSTR_SLT
• INSTR_SLTU
• INSTR_XOR
• INSTR_SRL
• INSTR_SRA
• INSTR_OR
• INSTR_AND

Phase2 instructions

• INSTR_JAL
• INSTR_JALR
• INSTR_LBU
• INSTR_LHU
• INSTR_SB
• INSTR_SH
• INSTR_LB
• INSTR_LH
• INSTR_AUIPC
• INSTR_MUL
• INSTR_MULH
• INSTR_DIV
• INSTR_DIVU
• INSTR_REM
• INSTR_REMU

Phase3 instructions

• INSTR_FLW
• INSTR_FSW
• INSTR_FADD_S
• INSTR_FSUB_S
• INSTR_FMUL_S
• INSTR_FDIV_S
• INSTR_FSQRT_S
• INSTR_FMV_X_W
• INSTR_FEQ_S
• INSTR_FLT_S
• INSTR_FLE_S
• INSTR_FMV_W_X

Tests

• Test1
• Test2
• Test3
• Test4
• Test5
• Test6
• Test7
• Test8
• Test9
• Test10
• Test11

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