Add ATtiny 817 support

Cargo.toml

@@ -64,6 +64,7 @@ attiny414 = ["device-selected"]
 attiny416 = ["device-selected"]
 attiny44a = ["device-selected"]
 attiny816 = ["device-selected"]
+attiny817 = ["device-selected"]
 attiny828 = ["device-selected"]
 attiny84 = ["device-selected"]
 attiny841 = ["device-selected"]

Makefile

@@ -1,7 +1,6 @@
 all: deps chips
 
-CHIPS := at90usb1286 atmega1280 atmega1284p atmega128a atmega128rfa1 atmega16 atmega164pa atmega168 atmega16u2 atmega2560 atmega8 atmega8u2 atmega324pa atmega328p atmega328pb atmega32a atmega32u2 atmega32u4 atmega3208 atmega3209 atmega4808 atmega4809 atmega48p atmega64 atmega644 atmega88p attiny13a attiny202 attiny212 attiny214 attiny2313 attiny2313a attiny26 attiny402 attiny404 attiny412 attiny414 attiny416 attiny44a attiny84 attiny85 attiny88 attiny816 attiny828 attiny841 attiny84a attiny861 attiny167 attiny1614 avr64du32 avr64du28
-
+CHIPS := at90usb1286 atmega1280 atmega1284p atmega128a atmega128rfa1 atmega16 atmega164pa atmega168 atmega16u2 atmega2560 atmega8 atmega8u2 atmega324pa atmega328p atmega328pb atmega32a atmega32u2 atmega32u4 atmega3208 atmega3209 atmega4808 atmega4809 atmega48p atmega64 atmega644 atmega88p attiny13a attiny202 attiny212 attiny214 attiny2313 attiny2313a attiny26 attiny402 attiny404 attiny412 attiny414 attiny416 attiny44a attiny84 attiny85 attiny88 attiny816 attiny817 attiny828 attiny841 attiny84a attiny861 attiny167 attiny1614 avr64du32 avr64du28
 RUSTUP_TOOLCHAIN ?= nightly
 
 PATCHES := $(foreach chip, $(CHIPS), $(wildcard patch/$(chip).yaml))
@@ -33,7 +32,7 @@ svd/%.svd.patched: svd/%.svd .deps/%.d patch/%.yaml
 src/devices/%/mod.full.rs: svd/%.svd.patched
 	@mkdir -p $(@D)
 	@echo -e "\tSVD2RUST\t$*"
-	@cd $(@D); svd2rust --generic_mod --make_mod --target none -i $(realpath $<)
+	@cd $(@D); svd2rust --generic_mod --make_mod --target avr -i $(realpath $<)
 	@mv $(@D)/mod.rs $@
 	@mv $(@D)/generic.rs $(@D)/../../generic.rs
 

README.md

@@ -29,8 +29,9 @@ Via the feature you can select which chip you want the register specifications f
 |  `atmega1284p`  |              |                   |               |  `attiny85`   |
 |  `atmega128a`   |              |                   |               |  `attiny88`   |
 | `atmega128rfa1` |              |                   |               |  `attiny816`  |
-|  `atmega2560`   |              |                   |               |  `attiny828`  |
-|  `atmega164pa`  |              |                   |               |  `attiny841`  |
+|  `atmega2560`   |              |                   |               |  `attiny817`  |
+|  `atmega164pa`  |              |                   |               |  `attiny828`  |
+|                 |              |                   |               |  `attiny841`  |
 |                 |              |                   |               |  `attiny84a`  |
 |                 |              |                   |               |  `attiny861`  |
 |                 |              |                   |               | `attiny1614`  |

patch/attiny817.yaml

@@ -0,0 +1,133 @@
+_svd: ../svd/attiny817.svd
+
+CRCSCAN:
+  CTRLB:
+    SRC:
+      _replace_enum:
+        FLASH: [0, "CRC on entire flash"]
+        BOOTAPP: [1, "CRC on boot and appl section of flash"]
+        BOOT: [2, "CRC on boot section of flash"]
+    MODE:
+      _replace_enum:
+        PRIORITY: [0, "Priority to flash"]
+
+NVMCTRL:
+  CTRLA:
+    CMD:
+      _replace_enum:
+        NONE: [0, "No command"]
+        WP: [1, "Write page"]
+        ER: [2, "Erase page"]
+        ERWP: [3, "Erase and write page"]
+        PBC: [4, "Page buffer clear"]
+        CHER: [5, "Chip erase"]
+        EEER: [6, "EEPROM erase"]
+        WFU: [7, "Write fuse (PDI only)"]
+
+SLPCTRL:
+  CTRLA:
+    SMODE:
+      _replace_enum:
+        IDLE: [0, "Idle mode"]
+        STANDBY: [1, "Standby Mode"]
+        PDOWN: [2, "Power-down Mode"]
+
+TCB0:
+  _add:
+    # FIXME: no idea how to add a write constraint with range [0x0, 0xFF] to
+    #        added registers to prevent bits() from being marked as unsafe
+    CCMPL:
+      description: Lower Compare or Capture in 8-bit PWM mode
+      addressOffset: 0x0C
+      access: read-write
+      size: 8
+    CCMPH:
+      description: Upper Compare or Capture in 8-bit PWM mode
+      addressOffset: 0x0D
+      access: read-write
+      size: 8
+
+TCD0:
+  EVCTRL?:
+    CFG:
+      _replace_enum:
+        NEITHER: [0, "Neither Filter nor Asynchronous Event is enabled"]
+        FILTERON: [1, "Input Capture Noise Cancellation Filter enabled"]
+        ASYNCON: [2, "Asynchronous Event output qualification enabled"]
+
+"PORT?":
+  DIR:
+    "P*":
+      # Make all Pins use the same enum
+      _replace_enum:
+        Input: [0, "Input"]
+        Output: [1, "Output"]
+
+  # make PINxCTRL a rust slice
+  _array:
+    "PIN?CTRL": {}
+
+"USART?":
+  STATUS:
+    _modify:
+      # The RXSIF bit is actually writable to clear the flag
+      RXSIF:
+        access: read-write
+      # The WFB bit is write-only
+      WFB:
+        access: write-only
+
+"SPI?":
+  CTRLA:
+    DORD:
+      # Make it an enum
+      _replace_enum:
+        MsbFirst: [0, "Most significant byte first"]
+        LsbFirst: [1, "Least significant byte first"]
+
+CCL:
+  _cluster:
+    "LUT%s":
+      description: "CCL LUT configuration cluster"
+      "LUT?CTRLA": {}
+      "LUT?CTRLB": {}
+      "LUT?CTRLC": {}
+      "TRUTH?": {}
+
+  # turn all SEQCTRL-registers into slices
+  _array:
+    "SEQCTRL?": {}
+
+CPUINT:
+  CTRLA:
+    IVSEL:
+      _replace_enum:
+        AFTERBOOT: [0, "Interrupt vectors are placed after the BOOT section of the Flash"]
+        INBOOT: [1, "Interrupt vectors are placed at the start of the BOOT section of the Flash"]
+    CVT:
+      _replace_enum:
+        NORMAL: [0, "Compact Vector Table function is disabled"]
+        COMPACT: [1, "Compact Vector Table function is enabled"]
+    LVL0RR:
+      _replace_enum:
+        FIXED: [0, "Priority is fixed for priority level 0 interrupt requests: The lowest interrupt vector address has the highest priority."]
+        ROUNDROBIN: [1, "The round robin priority scheme is enabled for priority level 0 interrupt requests"]
+
+EVSYS:
+  # make ASYNCCHx, SYNCCHx, ASYNCUSERx and SYNCUSERx a rust slice
+  _modify:
+    "ASYNCUSER*":
+      description: "Users of asynchronous channels"
+    "SYNCUSER*":
+      description: "Users of synchronous channels"
+  _array:
+    "ASYNCCH*": {}
+    "SYNCCH*": {}
+    "ASYNCUSER*": {}
+    "SYNCUSER*": {}
+
+"SIGROW":
+  # make a bunch of registers rust slices for easier access
+  _array:
+    "DEVICEID?": {}
+    "SERNUM?": {}

src/ccp.rs

@@ -0,0 +1,41 @@
+//! Configuration change protected (CCP) register definitions
+
+pub use crate::generic::ProtectedWritable;
+
+#[cfg(feature = "attiny817")]
+pub mod attiny817 {
+    use crate::generic::{UnlockRegister, Protected};
+
+    // Mark the CPU.CCP register with the UnlockRegister trait so that it can be used to unlock the below defined registers
+    impl UnlockRegister for crate::attiny817::cpu::ccp::CcpSpec { const PTR: *mut u8 = 0x34 as *mut u8; }
+
+    // Configuration change protected registers in NVMCTRL
+    impl Protected for crate::attiny817::nvmctrl::ctrla::CtrlaSpec { const MAGIC: u8 = 0x9D; type CcpReg = crate::attiny817::cpu::ccp::CcpSpec; }
+    impl Protected for crate::attiny817::nvmctrl::ctrlb::CtrlbSpec { const MAGIC: u8 = 0xD8; type CcpReg = crate::attiny817::cpu::ccp::CcpSpec; }
+
+    // Configuration change protected registers in CLKCTRL
+    impl Protected for crate::attiny817::clkctrl::mclkctrlb::MclkctrlbSpec { const MAGIC: u8 = 0xD8; type CcpReg = crate::attiny817::cpu::ccp::CcpSpec; }
+    impl Protected for crate::attiny817::clkctrl::mclklock::MclklockSpec { const MAGIC: u8 = 0xD8; type CcpReg = crate::attiny817::cpu::ccp::CcpSpec; }
+    impl Protected for crate::attiny817::clkctrl::xosc32kctrla::Xosc32kctrlaSpec { const MAGIC: u8 = 0xD8; type CcpReg = crate::attiny817::cpu::ccp::CcpSpec; }
+    impl Protected for crate::attiny817::clkctrl::mclkctrla::MclkctrlaSpec { const MAGIC: u8 = 0xD8; type CcpReg = crate::attiny817::cpu::ccp::CcpSpec; }
+    impl Protected for crate::attiny817::clkctrl::osc20mctrla::Osc20mctrlaSpec { const MAGIC: u8 = 0xD8; type CcpReg = crate::attiny817::cpu::ccp::CcpSpec; }
+    impl Protected for crate::attiny817::clkctrl::osc20mcaliba::Osc20mcalibaSpec { const MAGIC: u8 = 0xD8; type CcpReg = crate::attiny817::cpu::ccp::CcpSpec; }
+    impl Protected for crate::attiny817::clkctrl::osc20mcalibb::Osc20mcalibbSpec { const MAGIC: u8 = 0xD8; type CcpReg = crate::attiny817::cpu::ccp::CcpSpec; }
+    impl Protected for crate::attiny817::clkctrl::osc32kctrla::Osc32kctrlaSpec { const MAGIC: u8 = 0xD8; type CcpReg = crate::attiny817::cpu::ccp::CcpSpec; }
+
+    // Configuration change protected registers in RSTCTRL
+    impl Protected for crate::attiny817::rstctrl::swrr::SwrrSpec { const MAGIC: u8 = 0xD8; type CcpReg = crate::attiny817::cpu::ccp::CcpSpec; }
+
+    // Configuration change protected registers in CPUINT
+    impl Protected for crate::attiny817::cpuint::ctrla::CtrlaSpec { const MAGIC: u8 = 0xD8; type CcpReg = crate::attiny817::cpu::ccp::CcpSpec; }
+
+    // Configuration change protected registers in BOD
+    impl Protected for crate::attiny817::bod::ctrla::CtrlaSpec { const MAGIC: u8 = 0xD8; type CcpReg = crate::attiny817::cpu::ccp::CcpSpec; }
+
+    // Configuration change protected registers in WDT
+    impl Protected for crate::attiny817::wdt::ctrla::CtrlaSpec { const MAGIC: u8 = 0xD8; type CcpReg = crate::attiny817::cpu::ccp::CcpSpec; }
+    impl Protected for crate::attiny817::wdt::status::StatusSpec { const MAGIC: u8 = 0xD8; type CcpReg = crate::attiny817::cpu::ccp::CcpSpec; }
+
+    // Configuration change protected registers in TCD0
+    impl Protected for crate::attiny817::tcd0::faultctrl::FaultctrlSpec { const MAGIC: u8 = 0xD8; type CcpReg = crate::attiny817::cpu::ccp::CcpSpec; }
+}

src/devices/mod.rs

@@ -171,6 +171,10 @@ pub mod attiny44a;
 #[cfg(feature = "attiny816")]
 pub mod attiny816;
 
+/// [ATtiny817](https://www.microchip.com/wwwproducts/en/ATtiny817)
+#[cfg(feature = "attiny817")]
+pub mod attiny817;
+
 /// [ATtiny828](https://www.microchip.com/wwwproducts/en/ATtiny828)
 #[cfg(feature = "attiny828")]
 pub mod attiny828;

src/lib.rs

@@ -1,5 +1,4 @@
 //! This crate contains register definitions for
-
 #![cfg_attr(feature = "at90usb1286", doc = "**at90usb1286**,")]
 #![cfg_attr(feature = "atmega1280", doc = "**atmega1280**,")]
 #![cfg_attr(feature = "atmega1284p", doc = "**atmega1284p**,")]
@@ -42,6 +41,7 @@
 #![cfg_attr(feature = "attiny416", doc = "**attiny416**,")]
 #![cfg_attr(feature = "attiny44a", doc = "**attiny44a**,")]
 #![cfg_attr(feature = "attiny816", doc = "**attiny816**,")]
+#![cfg_attr(feature = "attiny817", doc = "**attiny817**,")]
 #![cfg_attr(feature = "attiny828", doc = "**attiny828**,")]
 #![cfg_attr(feature = "attiny84", doc = "**attiny84**,")]
 #![cfg_attr(feature = "attiny841", doc = "**attiny841**,")]
@@ -101,6 +101,7 @@
 //! `attiny416`,
 //! `attiny44a`,
 //! `attiny816`,
+//! `attiny817`,
 //! `attiny828`,
 //! `attiny84`,
 //! `attiny841`,
@@ -273,6 +274,7 @@ compile_error!(
     * attiny416
     * attiny44a
     * attiny816
+    * attiny817
     * attiny828
     * attiny84
     * attiny841
@@ -372,6 +374,8 @@ pub use crate::devices::attiny416;
 pub use crate::devices::attiny44a;
 #[cfg(feature = "attiny816")]
 pub use crate::devices::attiny816;
+#[cfg(feature = "attiny817")]
+pub use crate::devices::attiny817;
 #[cfg(feature = "attiny828")]
 pub use crate::devices::attiny828;
 #[cfg(feature = "attiny84")]
@@ -390,3 +394,9 @@ pub use crate::devices::attiny88;
 pub use crate::devices::avr64du28;
 #[cfg(feature = "avr64du32")]
 pub use crate::devices::avr64du32;
+
+#[allow(non_camel_case_types, unused_attributes, unreachable_patterns)]
+pub mod ccp;
+
+#[cfg(feature = "attiny817")]
+pub use crate::ccp::attiny817 as attiny817_ccp;