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[AMDGPU][WaveTransform] Enable SIOptimizeExecMaskingPreRA pass for new pipeline. #412

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Merged
merged 1 commit into from
Oct 29, 2025
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[AMDGPU][WaveTransform] Enable SIOptimizeExecMaskingPreRA pass for new pipeline. #412

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6 changes: 3 additions & 3 deletions llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1675,9 +1675,6 @@ void GCNPassConfig::addOptimizedRegAlloc() {
// instructions that cause scheduling barriers.
insertPass(&MachineSchedulerID, &SIWholeQuadModeID);

if (!LateWaveTransform && OptExecMaskPreRA)
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Don't change the default behavior. This has to be retained.

insertPass(&MachineSchedulerID, &SIOptimizeExecMaskingPreRAID);

// This is not an essential optimization and it has a noticeable impact on
// compilation time, so we only enable it from O2.
if (TM->getOptLevel() > CodeGenOptLevel::Less)
Expand Down Expand Up @@ -1861,6 +1858,9 @@ bool GCNPassConfig::addRegAssignAndRewriteOptimized() {
addPass(&RegisterCoalescerID);
}

if (OptExecMaskPreRA)
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Move it inside the LateWaveTransform check.

addPass(&SIOptimizeExecMaskingPreRAID);

addPass(createSGPRAllocPass(true));

// Commit allocated register changes. This is mostly necessary because too
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1 change: 1 addition & 0 deletions llvm/test/CodeGen/AMDGPU/WaveTransform/wave-transform-llc-pipeline.ll
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Expand Up @@ -387,6 +387,7 @@
; GCN-O3-NEXT: Live Interval Analysis
; GCN-O3-NEXT: Machine Natural Loop Construction
; GCN-O3-NEXT: Register Coalescer
; GCN-O3-NEXT: SI optimize exec mask operations pre-RA
; GCN-O3-NEXT: Machine Block Frequency Analysis
; GCN-O3-NEXT: Debug Variable Analysis
; GCN-O3-NEXT: Live Stack Slot Analysis
Expand Down
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/AMDGPU/llc-pipeline.ll
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Expand Up @@ -352,8 +352,8 @@
; GCN-O1-NEXT: Rewrite Partial Register Uses
; GCN-O1-NEXT: Machine Instruction Scheduler
; GCN-O1-NEXT: SI Whole Quad Mode
; GCN-O1-NEXT: SI optimize exec mask operations pre-RA
; GCN-O1-NEXT: AMDGPU Pre-RA Long Branch Reg
; GCN-O1-NEXT: SI optimize exec mask operations pre-RA
; GCN-O1-NEXT: Machine Natural Loop Construction
; GCN-O1-NEXT: Machine Block Frequency Analysis
; GCN-O1-NEXT: Debug Variable Analysis
Expand Down Expand Up @@ -665,8 +665,8 @@
; GCN-O1-OPTS-NEXT: Machine Instruction Scheduler
; GCN-O1-OPTS-NEXT: AMDGPU Pre-RA optimizations
; GCN-O1-OPTS-NEXT: SI Whole Quad Mode
; GCN-O1-OPTS-NEXT: SI optimize exec mask operations pre-RA
; GCN-O1-OPTS-NEXT: AMDGPU Pre-RA Long Branch Reg
; GCN-O1-OPTS-NEXT: SI optimize exec mask operations pre-RA
; GCN-O1-OPTS-NEXT: Machine Natural Loop Construction
; GCN-O1-OPTS-NEXT: Machine Block Frequency Analysis
; GCN-O1-OPTS-NEXT: Debug Variable Analysis
Expand Down Expand Up @@ -983,9 +983,9 @@
; GCN-O2-NEXT: Machine Instruction Scheduler
; GCN-O2-NEXT: AMDGPU Pre-RA optimizations
; GCN-O2-NEXT: SI Whole Quad Mode
; GCN-O2-NEXT: SI optimize exec mask operations pre-RA
; GCN-O2-NEXT: SI Form memory clauses
; GCN-O2-NEXT: AMDGPU Pre-RA Long Branch Reg
; GCN-O2-NEXT: SI optimize exec mask operations pre-RA
; GCN-O2-NEXT: Machine Natural Loop Construction
; GCN-O2-NEXT: Machine Block Frequency Analysis
; GCN-O2-NEXT: Debug Variable Analysis
Expand Down Expand Up @@ -1315,9 +1315,9 @@
; GCN-O3-NEXT: Machine Instruction Scheduler
; GCN-O3-NEXT: AMDGPU Pre-RA optimizations
; GCN-O3-NEXT: SI Whole Quad Mode
; GCN-O3-NEXT: SI optimize exec mask operations pre-RA
; GCN-O3-NEXT: SI Form memory clauses
; GCN-O3-NEXT: AMDGPU Pre-RA Long Branch Reg
; GCN-O3-NEXT: SI optimize exec mask operations pre-RA
; GCN-O3-NEXT: Machine Natural Loop Construction
; GCN-O3-NEXT: Machine Block Frequency Analysis
; GCN-O3-NEXT: Debug Variable Analysis
Expand Down