Tbps_CRC

A SystemVerilog implementation of Cyclic Redundancy Check that runs at up to Terabits per second.

Zenodo DOI of this repository: 10.5281/zenodo.7226144.

Core HDL code for CRC calculation

The core code of Tbps CRC is located in the rtl directory. There are 3 files in the folder:

• tbps_crc.sv - The main SystemVerilog CRC module with byte enable support and configurable pipelining
• tbps_crc_axis.sv - AXI-Stream wrapper module for easy integration with AXI-Stream interfaces
• tbps_crc.svh - SystemVerilog header file containing constant functions that run at elaboration (pre-synthesis) time

Key Features

• High Throughput: Designed for Terabits per second operation
• Parameterizable: Configurable data width (must be multiple of 8), CRC polynomial, and pipeline levels
• Byte Enable Support: Built-in support for partial byte processing
• AXI-Stream Ready: Includes AXI-Stream wrapper for seamless integration
• Pipeline Optimization: Configurable pipeline levels for frequency/area/latency tradeoffs
• Flexible CRC Configuration: Supports custom polynomials, initial values, and bit reflection options

Simulation

The testbench is under the sim directory and includes:

• tb.sv - SystemVerilog testbench module with AXI-Stream interface
• run_test.py - Python-based CocoTB test runner with comprehensive CRC verification

Running Tests

The simulation uses Python CocoTB framework with pytest for comprehensive testing:

Single Unit Test with Custom Parameters:

cd sim
python run_test.py --DWIDTH=512 --PIPE_LVL=0 --CRC_NAME="crc-32"

Comprehensive Test Suite: For testing a wide variety of CRC polynomials with different configurations, simply run:

cd sim
mkdir build && cd build
cmake ..
make pytest

The test framework supports:

• Multiple data widths (32, 128, 512, 768 bits)
• Different pipeline levels (0, 1, 2+)
• All standard CRC polynomials defined in the crcmod library
• Automatic verification against software CRC implementations

Both simulation and on-board tests generate random messages of a given random size and feed the messages into the CRC module. The simulation compares the results generated by the hardware with the results computed by a software function and reports the mismatch (if any) between the software and hardware results.

Module Parameters

Implementation Parameters:

• DWIDTH: Data width in bits (must be a multiple of 8, e.g., 64, 512, 768)
• PIPE_LVL: Number of pipeline stages for frequency/area/latency tradeoff
• REV_PIPE_EN_ONEHOT: Revert pipeline enable one-hot code, controls whether to register corresponding pipeline stages

CRC Polynomial Parameters:

• CRC_WIDTH: Width of the CRC output (e.g., 16 for CRC-16, 32 for CRC-32)
• CRC_POLY: CRC polynomial in hexadecimal format (e.g., 32'h04C11DB7 for CRC-32)

Ports

Clock and Reset:

• clk: Clock signal
• rst: Synchronous reset (active high)

CRC Configuration:

• crc_init_val: Initial CRC value [CRC_WIDTH-1:0]
• xor_out: Value to XOR with CRC result before output [CRC_WIDTH-1:0]
• ref_in: Reflect input bytes (bit reversal per byte)
• ref_out: Reflect output CRC (bit reversal)

Data Inputs:

tbps_crc.sv:

• din: Input data bus [DWIDTH-1:0]
• byteEn: Byte enable mask [DWIDTH/8-1:0]
• dlast: Indicates the last data beat in a packet/transaction
• flitEn: Data valid strobe (asserted when din/byteEn are valid)

tbps_crc_axis.sv:

• i_data_axis_tdata: Input data bus [DWIDTH-1:0]
• i_data_axis_tkeep: Byte enable mask [DWIDTH/8-1:0]
• i_data_axis_tlast: Last signal (asserted on last data beat)
• i_data_axis_tvalid: Valid signal

Outputs:

tbps_crc.sv:

• crc_out: CRC output value [CRC_WIDTH-1:0]
• crc_out_vld: CRC output valid (asserted when crc_out is valid)

tbps_crc_axis.sv:

• o_crc_axis_tdata: CRC output value [CRC_WIDTH-1:0]
• o_crc_axis_tvalid: CRC output valid signal

Usage Example

  tbps_crc_axis #(
    .DWIDTH(256),
    .CRC_WIDTH(16),
    .PIPE_LVL(2),
    .CRC_POLY(16'h1021)
  ) u_tbps_crc_axis (
    .clk(clk),
    .rst(rst),
    .crc_init_val(16'hFFFF),
    .xor_out(16'h0000),
    .ref_in(1'b1),
    .ref_out(1'b1),
    .i_data_axis_tdata(i_data_axis_tdata),
    .i_data_axis_tkeep(i_data_axis_tkeep),
    .i_data_axis_tlast(i_data_axis_tlast),
    .i_data_axis_tvalid(i_data_axis_tvalid),
    .o_crc_axis_tdata(o_crc_axis_tdata),
    .o_crc_axis_tvalid(o_crc_axis_tvalid)
  );

tbps_crc #(
    .DWIDTH(256),
    .CRC_WIDTH(32),
    .PIPE_LVL(2),
    .CRC_POLY(32'h04C11DB7)
) u_tbps_crc (
    .clk(clk),
    .rst(rst),
    .crc_init_val(32'hFFFFFFFF),
    .xor_out(32'hFFFFFFFF),
    .ref_in(1'b1),
    .ref_out(1'b1),
    .din(din),
    .byteEn(byteEn),
    .dlast(dlast),
    .flitEn(flitEn),
    .crc_out(crc_out),
    .crc_out_vld(crc_out_vld)
);

License

This project is licensed under the MIT License - see the LICENSE.md file for details.