top: Add a difftop for the fpgadiff platform

src/main/scala/nutcore/NutCore.scala

@@ -66,6 +66,7 @@ abstract class NutCoreBundle extends Bundle with HasNutCoreParameter with HasNut
 
 case class NutCoreConfig (
   FPGAPlatform: Boolean = true,
+  FPGADifftest: Boolean = false,
   EnableDebug: Boolean = Settings.get("EnableDebug"),
   EnhancedLog: Boolean = true
 )

src/main/scala/nutcore/backend/fu/CSR.scala

@@ -885,14 +885,14 @@ class CSR(implicit val p: NutCoreConfig) extends NutCoreModule with HasCSRConst{
   }}
 
   val nutcoretrap = WireInit(false.B)
-  if (!p.FPGAPlatform) {
+  if (!p.FPGAPlatform || p.FPGADifftest) {
     BoringUtils.addSink(nutcoretrap, "nutcoretrap")
   } else {
     nutcoretrap := 0.U
   }
   def readWithScala(addr: Int): UInt = mapping(addr)._1
 
-  if (!p.FPGAPlatform) {
+  if (!p.FPGAPlatform || p.FPGADifftest) {
     // to monitor
     BoringUtils.addSource(readWithScala(perfCntList("Mcycle")._1), "simCycleCnt")
     BoringUtils.addSource(readWithScala(perfCntList("Minstret")._1), "simInstrCnt")

src/main/scala/nutcore/backend/ooo/Backend.scala

@@ -639,13 +639,13 @@ class Backend_ooo(implicit val p: NutCoreConfig) extends NutCoreModule with HasR
   BoringUtils.addSource(io.in(1).valid && !instCango(1), "perfCntCondMdp2StCnt")
   BoringUtils.addSource(!io.in(0).valid, "perfCntCondMdpNoInst")
 
-  if (!p.FPGAPlatform) {
+  if (!p.FPGAPlatform || p.FPGADifftest) {
     val difftest = DifftestModule(new DiffArchIntRegState)
     difftest.coreid := 0.U // TODO
     difftest.value  := VecInit((0 to NRReg-1).map(i => rf.read(i.U)))
   }
 
-  if (!p.FPGAPlatform) {
+  if (!p.FPGAPlatform || p.FPGADifftest) {
     val cycleCnt = WireInit(0.U(XLEN.W))
     val instrCnt = WireInit(0.U(XLEN.W))
     val nutcoretrap = WireInit(csrrs.io.out.bits.decode.ctrl.isNutCoreTrap && csrrs.io.out.valid)

src/main/scala/nutcore/backend/ooo/ROB.scala

@@ -495,7 +495,7 @@ class ROB(implicit val p: NutCoreConfig) extends NutCoreModule with HasInstrType
   BoringUtils.addSource(retireATerm, "perfCntCondMinstret")
   BoringUtils.addSource(retireMultiTerms, "perfCntCondMultiCommit")
 
-  if (!p.FPGAPlatform) {
+  if (!p.FPGAPlatform || p.FPGADifftest) {
     for (i <- 0 until RetireWidth) {
       val difftest_commit = DifftestModule(new DiffInstrCommit(robSize * robWidth), delay = 1)
       difftest_commit.coreid   := 0.U

src/main/scala/nutcore/backend/seq/EXU.scala

@@ -129,7 +129,7 @@ class EXU(implicit val p: NutCoreConfig) extends NutCoreModule {
   BoringUtils.addSource(WireInit(mdu.io.out.fire), "perfCntCondMmduInstr")
   BoringUtils.addSource(WireInit(csr.io.out.fire), "perfCntCondMcsrInstr")
 
-  if (!p.FPGAPlatform) {
+  if (!p.FPGAPlatform || p.FPGADifftest) {
     val cycleCnt = WireInit(0.U(64.W))
     val instrCnt = WireInit(0.U(64.W))
     val nutcoretrap = WireInit(io.in.bits.ctrl.isNutCoreTrap && io.in.valid)

src/main/scala/nutcore/backend/seq/ISU.scala

@@ -98,7 +98,7 @@ class ISU(implicit val p: NutCoreConfig) extends NutCoreModule with HasRegFilePa
   BoringUtils.addSource(WireInit(io.out.valid && !io.out.fire), "perfCntCondMexuBusy")
   BoringUtils.addSource(WireInit(io.out.fire), "perfCntCondISUIssue")
 
-  if (!p.FPGAPlatform) {
+  if (!p.FPGAPlatform || p.FPGADifftest) {
     val difftest = DifftestModule(new DiffArchIntRegState)
     difftest.coreid := 0.U // TODO
     difftest.value  := VecInit((0 to NRReg-1).map(i => rf.read(i.U)))

src/main/scala/nutcore/backend/seq/WBU.scala

@@ -44,7 +44,7 @@ class WBU(implicit val p: NutCoreConfig) extends NutCoreModule{
   BoringUtils.addSource(io.in.valid, "perfCntCondMinstret")
   BoringUtils.addSource(falseWire, "perfCntCondMultiCommit")
 
-  if (!p.FPGAPlatform) {
+  if (!p.FPGAPlatform || p.FPGADifftest) {
     val difftest_commit = DifftestModule(new DiffInstrCommit, delay = 1, dontCare = true)
     difftest_commit.coreid := 0.U
     difftest_commit.index  := 0.U

src/main/scala/system/NutShell.scala

@@ -125,7 +125,7 @@ class NutShell(implicit val p: NutCoreConfig) extends Module with HasSoCParamete
 
 
   // ILA
-  if (p.FPGAPlatform) {
+  if (p.FPGAPlatform && !p.FPGADifftest) {
     def BoringUtilsConnect(sink: UInt, id: String) = {
       val temp = WireInit(0.U(64.W))
       BoringUtils.addSink(temp, id)

src/main/scala/top/Settings.scala

@@ -64,6 +64,17 @@ object Axu3cgSettings {
   )
 }
 
+object FpgaDiffSettings {
+  def apply() = Map(
+    "FPGAPlatform" -> true,
+    "FPGADifftest" -> true,
+    "EnableILA" -> false,
+    "hasPerfCnt" -> false,
+    "NrExtIntr" -> 2,
+    "EnableDebug" -> false
+  )
+}
+
 object PXIeSettings {
   def apply() = Map(
     "FPGAPlatform" -> true,

src/test/scala/TopMain.scala

@@ -36,6 +36,17 @@ class Top extends Module {
   dontTouch(vga.io)
 }
 
+class FpgaDiffTop extends Module {
+  override lazy val desiredName: String = "SimTop"
+  lazy val config = NutCoreConfig(FPGADifftest = true)
+  val soc = Module(new NutShell()(config))
+  val io = IO(soc.io.cloneType)
+  soc.io <> io
+
+  val difftest = DifftestModule.finish("nutshell")
+  dontTouch(soc.io)
+}
+
 object TopMain extends App {
   def parseArgs(info: String, args: Array[String]): String = {
     var target = ""
@@ -51,6 +62,7 @@ object TopMain extends App {
     case "sim"    => Nil
     case "pynq"   => PynqSettings()
     case "axu3cg" => Axu3cgSettings()
+    case "fpgadiff" => FpgaDiffSettings()
     case "PXIe"   => PXIeSettings()
   } ) ++ ( core match {
     case "inorder"  => InOrderSettings()
@@ -68,6 +80,8 @@ object TopMain extends App {
 
   val generator = if (board == "sim") {
     ChiselGeneratorAnnotation(() => new SimTop)
+  } else if (board == "fpgadiff") {
+    ChiselGeneratorAnnotation(() => new FpgaDiffTop)
   }
   else {
     ChiselGeneratorAnnotation(() => new Top)