LLM4Ver

Fuzzing FPGA Logic Synthesis Compilers via LLM-Generated Syntax-Valid HDL Designs

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Env dependencies:

1. python 3.8
2. openai 1.17.1
3. pyverilog 1.3.0
4. Provide an API for large language models in src/openai_client.py

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Fuzz Testing Targets:(logic synthesis tools and simulated tools)

1. Vivado 2023.2
2. Yosys 0.39+165
3. Icarus Verilog V12_0
4. Quartus Prime 23.1

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Our Work

In modern electronic system design, the logic synthesis and functional simulation steps of Field-Programmable Gate Arrays (FPGAs) play a crucial role. These steps are performed by Electronic Design Automation (EDA) tools, which:

• Convert Hardware Description Language (HDL) code into logic gates and circuit layouts, and
• Simulate their behavior to ensure the correctness and stability of the design.

However, logic synthesis tools and simulation tools may contain defects that can cause the design to exhibit unexpected behavior when implemented in hardware, leading to serious consequences.

Our Solution: LLM4Ver

We propose a novel fuzzing method named LLM4Ver, the first fuzz testing tool that leverages prompting large language models for generating valid Verilog programs to test logic synthesis tools.

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directory structure

VerFuzzer-main/
├── README.md
├── check.py
├── config/
│   └── config.toml
├── src/
│   ├── AST.py
│   ├── code_generate.py
│   ├── code_inspect.py
│   ├── config_extract.py
│   ├── equiv_check.py
│   ├── equivcheck_code.py
│   ├── error_feedback.py
│   ├── generate.py
│   ├── openai_client.py
│   ├── prompt_generate.py
│   ├── run.sh
│   ├── run_main.sh
│   ├── run_symbiyosys.sh
│   ├── synthesis.py
│   ├── testbench.py
│   └── Tool/
│       ├── Icarus.py
│       ├── Vivado.py
│       └── Yosys.py
│   └── temp_save/
│       ├── tem_ast.txt
│       └── temp.v

The directory structure of the document is as follows. After adding the API, you can run the command below to execute: bash run.sh <outputdir> <number>