" I tried to ImProVe, but NeVer really did — so I MOVe-d on ¯\_(ツ)_/¯ "

ImProVe – IMage PROcessing using VErilog: A collection of image processing algorithms implemented in Verilog, including geometric transformations, color space conversions, and other foundational operations.

NeVer – NEural NEtwork on VERilog: A hardware-implemented multi-layer perceptron (MLP) neural network in Verilog for character recognition using EMNIST and MNIST datasets.

MOVe – Math Ops in VErilog

• CORDIC Algorithm – Implements Coordinate Rotation Digital Computer (CORDIC) algorithms in Verilog for efficient hardware-based calculation of sine, cosine, tangent, square root, magnitude, and more.

• Systolic Array Matrix Multiplication – Verilog implementation of matrix multiplication using systolic arrays to enable parallel computation and hardware-level performance optimization. Each processing element leverages a Multiply-Accumulate (MAC) unit for core operations.

• Multiply-Accumulate Unit – The MAC unit uses Booth’s algorithm for efficient signed multiplication and a Kogge-Stone adder for fast, parallel addition. Booth reduces operation count by encoding the multiplier, while Kogge-Stone ensures low-latency summation through parallel carry computation. Together, they enable compute-heavy multiply-accumulate operations in a compact and optimized form.

• Posit Arithmetic (Python) – Currently using fixed-point arithmetic; considering Posit as an alternative to IEEE 754 for better precision and dynamic range. Still working through the trade-off.

Storage and Buffer Modules

• RAM1KB – A 1KB (1024 x 8-bit) memory module in Verilog with write-once locking for even addresses. Includes a randomized testbench.

• FIFO Buffer – Not started. Planned as a synchronous FIFO with fixed depth, single clock domain, and standard full/empty flag logic.

Duration: Individual, Ongoing
Tools: Verilog (Icarus Verilog, Xilinx Vivado) | Python (OpenCV, NumPy, Tkinter) | Scripting (TCL, Perl)

• Designed image processing algorithms (e.g., edge detection, geometric & color transforms, noise reduction) in Verilog, utilizing hardware optimized math techniques to maximize computational efficiency. These algorithms were fine-tuned for low-latency preprocessing in embedded vision SoCs.

• Implemented a 64-bit 3-layer perceptron (MLP 784-256-128-62, ~242k params) for Extended-MNIST Character Recognition (62 classes, ∼124k samples) using an FSM-controlled neural network in Verilog. This implementation achieved >90% training accuracy (>75% simulation accuracy) with ~1.5s inference latency (in simulation). A full end-to-end preprocessing and inference workflow was developed.

• Automated model inference and performance metric evaluation via Tcl/Perl scripts (executing Python and Icarus Verilog commands). Additionally, a real-time Tkinter GUI was created for test user input.

• Now working on a lightweight CNN accelerator for image classification on CIFAR-10, with a focus on making it hardware-friendly

Duration: Team-based (ISRO RIG), Ongoing Tools: Jetson Nano | Pixhawk | RealSense D435i | ESP32 (ESP‑Now) | VINS‑Fusion | ROS2

• Built a <2kg autonomous quadrotor> for GNSS-denied environments, capable of real-time mapping, navigation, and safe-zone detection with zero manual intervention; Jetson Nano was used for onboard compute and Pixhawk handled flight control.

• Calibrated ESCs and implemented embedded power distribution via BEC module to ensure stable regulation for compute/sensing; integrated barometer and external optical flow sensor with Pixhawk for redundancy in low-texture or drifting conditions.

• Fused stereo-IMU data from Intel RealSense D435i using VINS-Fusion on ROS2, achieving <5cm drift over ~5m; transmitted real-time telemetry using ESP32 modules (ESP‑Now); autonomously landed on obstacle-free 1.5×1.5m zones with <15° slopes.

Duration: Individual, Ongoing
Tools: Verilog (Icarus Verilog) | TL-Verilog (Makerchip)

• Implemented a fully synthesizable RV32I RISC-V core in TL-Verilog with a single-stage pipeline, supporting all base integer instructions and immediate formats (I, S, B, U, J).

• Developed a test program summing integers 1 to 9, verified correct ALU operations, branching, and control flow within 50 simulation cycles, with pass/fail status stored in registers x30 and x31.

• Designed a 32-register file with dual-read and single-write ports, enforcing write-disable on register x0, and integrated instruction decode logic handling opcode, funct3, and funct7 fields.

• Implemented comprehensive ALU supporting arithmetic, logic, shifts, and comparisons, with immediate extraction and flexible program counter update logic including branch and jump target calculation.

• Enabled simulation and debugging via Makerchip integration using m4+cpu_viz(), with waveform visualization and automated test validation through register monitoring.

Designed I2C with a single-master, multi-slave configuration supporting clock stretching and configurable delays; SPI supports modes 0–3 via CPOL/CPHA, performs single 8-bit full-duplex transfers, and allows clock frequency scaling through a divider

Designed and simulated semiconductor structures (N-resistor, PN diode, NMOS) using Sentaurus TCAD; explored effects of doping, geometry, and physical models through process setup, simulation scripting, and visual analysis of internal device behavior

A vision-guided, algorithm-driven robot that solves the Rubik’s Cube with precision using Kociemba’s two-phase algorithm for optimal move sequences, developed in Unity3D with C# scripting