This project is a testbench generator for the RISC-V instruction set, written in C. It uses the principles of object-oriented programming to automatically generate assembly test programs for corresponding instructions. These programs can be used to test the implementation of the instruction set in a RISC-V processor.
To use this generator, simply provide the instructions you want to generate test programs for, and the generator will output the corresponding assembly test programs.
This tool is ideal for both hardware developers working on RISC-V processors and educators teaching the RISC-V instruction set. By automatically generating test programs, users can focus on the more critical aspects of their work or studies.