In this project, we should design a 5 floor elevator.
- Verilog
- Modelsim
This elevator works based on time priority. But if we reach a floor that its request signal is on , we wait for a certain time without checking its priority. This is an example that illustrates the explanation:
go to the Document for more details.
for running the program, you should just control the buttons of the elevator in TestBench module. More information is in the report.
The result are shown in two way Transcript and Waveform of Modelsim. Waveform is more detailed and has all signals.
Transcript:
Wave:
descriptions are in the report file in document.