Skip to content

This Computer Architecture Final Project involves the development of an L1-L2-DRAM with L1 as Direct Mapped cache and L2 as Set Associative cache. The program involves python NumPy and pandas packages to determine and differentiate the working of direct-mapped and set-associative caches.

Notifications You must be signed in to change notification settings

Lohitanvita/Computer-Architecture

Folders and files

NameName
Last commit message
Last commit date

Latest commit

 

History

22 Commits
 
 
 
 
 
 

Repository files navigation

Computer-Architecture

The project contains simulation results and python code for computer Architecture concepts such as memory hierarchy, branch prediction, cache organization and associativity. The resources used for simulation project are VMware 16, Ubuntu 1604, and SimpleScalar. In this project I ran the linux commands in simplescalar tool to learn the difference between ISAs (PISA and ALPHA Intruction Set Architectures), how memory hierarchy and branch prediction helped improve the CPU speed etc,. The part 2 of the project involves python code with Numpy and Pandas packages to define a dynamic memory table and run the direct mapped and set associative caches. This explains how set-associative cache is more flexible in performance than direct-mapped cache. There is a pdf containing the whole report the project.

About

This Computer Architecture Final Project involves the development of an L1-L2-DRAM with L1 as Direct Mapped cache and L2 as Set Associative cache. The program involves python NumPy and pandas packages to determine and differentiate the working of direct-mapped and set-associative caches.

Resources

Stars

Watchers

Forks

Releases

No releases published

Packages

No packages published

Languages