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1. cv32e40p cv32e40p Public

   Forked from openhwgroup/cv32e40p

   CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

   SystemVerilog

2. croc croc Public

   Forked from sislab-vnu/croc

   A PULP SoC for education, easy to understand and extend with a full flow for a physical design.

   SystemVerilog

3. Clock-Domain-Crossing-Synchronizers Clock-Domain-Crossing-Synchronizers Public

   Forked from MahmouodMagdi/Clock-Domain-Crossing-Synchronizers

   Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference for understanding and implementing robust clock domain crossi…

   Verilog

4. Arty-A7-FPGA-Projects Arty-A7-FPGA-Projects Public

   Forked from BitOpenFPGA/Arty-A7-FPGA-Projects

   Various FPGA projects targeting a Digilent Arty FPGA board

   VHDL

5. picorv32 picorv32 Public

   Forked from YosysHQ/picorv32

   PicoRV32 - A Size-Optimized RISC-V CPU

   Verilog

6. vivado-risc-v vivado-risc-v Public

   Forked from eugene-tarassov/vivado-risc-v

   Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro

   Tcl