Skip to content

Add Intel Cascade Lake and Ice Lake #469

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 3 commits into from
May 28, 2025
Merged

Add Intel Cascade Lake and Ice Lake #469

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
3 commits
Select commit Hold shift + click to select a range
7f81734
add cascadelake and icelake
bedroge May 23, 2025
dabd466
remove cascadelake and icelake from excluded targets
bedroge May 23, 2025
01d631d
add two columns for icelake and cascadelake
bedroge May 23, 2025
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
6 changes: 4 additions & 2 deletions docs/available_software/overview.md
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -8,14 +8,14 @@ This table gives an overview of all the available software in EESSI per specific
<tr>
<th rowspan="3">Name</th>
<th colspan="4">aarch64</th>
<th colspan="7">x86_64</th>
<th colspan="9">x86_64</th>
</tr>
<tr>
<th colspan="3"></th>
<th colspan="1">nvidia</th>
<th colspan="1"></th>
<th colspan="3">amd</th>
<th colspan="3">intel</th>
<th colspan="5">intel</th>
</tr>
<tr>
<th colspan="1"></th>
Expand All @@ -29,6 +29,8 @@ This table gives an overview of all the available software in EESSI per specific
<th colspan="1"></th>
<th colspan="1"></th>
<th colspan="1"></th>
<th colspan="1"></th>
<th colspan="1"></th>
</tr>
</thead>
</table>
4 changes: 3 additions & 1 deletion docs/software_layer/cpu_targets.md
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -11,7 +11,9 @@ In the 2023.06 version of the EESSI repository, the following CPU microarchitect
* `x86_64/amd/zen3`: AMD Milan, Milan-X
* `x86_64/amd/zen4`: AMD Genoa, Genoa-X, Bergamo, Siena
* `x86_64/intel/haswell`: Intel Haswell, Broadwell
* `x86_64/intel/skylake_avx512`: Intel Skylake, Cascade Lake, Ice Lake, Cooper Lake
* `x86_64/intel/skylake_avx512`: Intel Skylake
* `x86_64/intel/cascadelake`: Intel Cascade Lake, Cooper Lake
* `x86_64/intel/icelake`: Intel Ice Lake
* `x86_64/intel/sapphirerapids`: Intel Sapphire Rapids, Emerald Rapids

The names of these CPU targets correspond to the names used by [archspec](https://github.com/archspec/archspec).
2 changes: 1 addition & 1 deletion scripts/available_software/available_software.py
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -29,7 +29,7 @@
EESSI_TOPDIR = "/cvmfs/software.eessi.io/versions/2023.06"

# some CPU targets are excluded for now, because software layer is too incomplete currently
EXCLUDE_CPU_TARGETS = ['aarch64/a64fx', 'x86_64/intel/cascadelake', 'x86_64/intel/icelake']
EXCLUDE_CPU_TARGETS = ['aarch64/a64fx']


# --------------------------------------------------------------------------------------------------------
Expand Down
Loading