MiniLA CPU

中文

This is my experimental project for the Computer Design and Practice course in 2025, implementing a simple LoongArch CPU architecture that supports basic instruction sets and pipeline structures, including features such as branch prediction and data forwarding.

• Designed using Chisel/Scala language. It's worth noting that this project uses Chisel 7.0.0-RC2. If you want to migrate to lower versions, please pay attention to the syntax of chiselsim and MuxLookup.
• Adopts a five-stage pipeline: Instruction Fetch and Decode (IFD), Instruction Decode (ID), Execute (EX), Memory Access (MEM), and Write Back (WB).
• The pipeline uses typical 2-bit branch prediction and data forwarding mechanisms.
• Implements 38 instructions, supporting basic integer operations, load/store, branch/jump operations.
  • 3R: add.w, sub.w, and, or, xor, sll.w, srl.w, sra.w, slt, sltu
  • 2RI5: slli.w, srli.w, srai.w
  • 2RI12: addi.w, andi, ori, xori, slti, sltui, ld.b, ld.bu, ld.h, ld.hu, ld.w, st.b, st.h, st.w
  • 1RI20: lu12i.w, pcaddu12i
  • 2RI16: beq, bne, blt, bltu, bge, bgeu, jirl
  • I26: b, bl

Project Overview

The repository contains multiple branches, each branch contains a clean single-cycle/pipeline CPU implementation, and you can pull only a single branch. Each branch follows the structure below:

├── project/                    # SBT project configuration files
├── src/
│   ├── main/
│   │   └── scala/
│   │       ├── core/           # CPU core modules
│   │       │   ├── Bundles.scala    # Datapath interface definitions
│   │       │   ├── Cpucore.scala    # CPU core top-level module
│   │       │   ├── Modules.scala    # Basic functional modules
│   │       │   └── Stages.scala     # Five-stage pipeline definitions
│   │       ├── debug/          # Debug and test modules
│   │       │   ├── Debug.scala      # For trace debugging
│   │       │   └── Test.scala       # Built-in test programs
│   │       ├── dev/            # Peripheral and I/O modules
│   │       │   ├── Bridge.scala     # Peripheral bridging
│   │       │   ├── Bundles.scala    # Peripheral interface definitions
│   │       │   └── Devices.scala    # Peripheral implementations
│   │       ├── Blackboxes.scala     # Blackbox modules (memory, etc.)
│   │       ├── Generate.scala       # SystemVerilog generation
│   │       └── miniLA.scala         # System top-level module
│   └── test/
│       └── scala/
│           └── Cputest.scala   # Unit tests and simulation tests
├── test/                       # Test programs and data
├── build.sbt                   # SBT build configuration
├── Makefile
└── miniLA_{$branch_name?}.svg     # Architecture diagram

In the project root directory, you can use make to compile/test/clean. You can check the Makefile yourself. Note that both branches have architecture diagrams for reference, drawn using draw.io. The source files can be found in the docs/chart/ directory of the main branch.

Runtime Environment

You need to install sbt and verilator yourself. The Java version needs to be handled appropriately. The official documentation states that chisel 7.0.0-RC1 cannot use Java 23+ language features, however, this project does not use Java syntax.

After some minor modifications to the test project, it runs and tests well on both my macOS and an Arch Linux machine. It works normally under both Verilator 5.038 2025-07-08 rev and Verilator 5.036 2025-04-27 rev.

Compilation and Testing

Instructions are as follows:

$ make          # Compile
$ make test     # Test
$ make clean    # Clean

Compilation results are in the build/sv directory. Files are scattered and need to be packaged for Vivado. Compilation is required before testing.

Test output is in the test.log file, including personal tests and school tests. Personal tests simulate the execution process, with output including 8 bytes from 7-segment displays and 16 bits from LEDs. The final output should be sorted 7-segment display content and LED data with the last bit as 1.

Make includes .sv file generation and verilator compilation. Testing also includes both tests. If you want to save time, please run directly:

$ sbt run       # build
$ sbt test      # test

FPGA Implementation

I used the EGO1 development board with chip model XC7A35TCSG324-1.

You need to create IP modules yourself in the Vivado project. For related instructions, refer to the documentation excerpt.

Assembly

You can write in C language for convenience. For virtual machine reference, see asm/LA/CLFS_LoongArch32.

Acknowledgments

Thanks to the following projects for their contributions:

• Test framework cdp-test
• Chisel template chisel-template
• Experiment documentation CPUDesign

Disclaimer

This project is licensed under the MIT License. You are free to use and learn from this project, but any consequences arising from plagiarism are the sole responsibility of the infringer, and the author assumes no responsibility.