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| 1 | +From 4f764e21e589c2c5704342237259cb2a8c0a304a Mon Sep 17 00:00:00 2001 |
| 2 | +From: Nick Desaulniers <ndesaulniers@google.com> |
| 3 | +Date: Mon, 29 Jul 2019 10:12:14 -0700 |
| 4 | +Subject: [PATCH] powerpc: workaround clang codegen bug in dcbz |
| 5 | + |
| 6 | +Commit 6c5875843b87 ("powerpc: slightly improve cache helpers") exposed |
| 7 | +what looks like a codegen bug in Clang's handling of `%y` output |
| 8 | +template with `Z` constraint. This is resulting in panics during boot |
| 9 | +for 32b powerpc builds w/ Clang, as reported by our CI. |
| 10 | + |
| 11 | +Add back the original code that worked behind a preprocessor check for |
| 12 | +__clang__ until we can fix LLVM. |
| 13 | + |
| 14 | +Further, it seems that clang allnoconfig builds are unhappy with `Z`, as |
| 15 | +reported by 0day bot. This is likely because Clang warns about inline |
| 16 | +asm constraints when the constraint requires inlining to be semantically |
| 17 | +valid. |
| 18 | + |
| 19 | +Link: https://bugs.llvm.org/show_bug.cgi?id=42762 |
| 20 | +Link: https://github.com/ClangBuiltLinux/linux/issues/593 |
| 21 | +Link: https://lore.kernel.org/lkml/20190721075846.GA97701@archlinux-threadripper/ |
| 22 | +Reported-by: Nathan Chancellor <natechancellor@gmail.com> |
| 23 | +Reported-by: kbuild test robot <lkp@intel.com> |
| 24 | +Signed-off-by: Nick Desaulniers <ndesaulniers@google.com> |
| 25 | +--- |
| 26 | + arch/powerpc/include/asm/cache.h | 25 +++++++++++++++++++++++++ |
| 27 | + 1 file changed, 25 insertions(+) |
| 28 | + |
| 29 | +diff --git a/arch/powerpc/include/asm/cache.h b/arch/powerpc/include/asm/cache.h |
| 30 | +index b3388d95f451..72983da94dce 100644 |
| 31 | +--- a/arch/powerpc/include/asm/cache.h |
| 32 | ++++ b/arch/powerpc/include/asm/cache.h |
| 33 | +@@ -105,6 +105,30 @@ extern void _set_L3CR(unsigned long); |
| 34 | + #define _set_L3CR(val) do { } while(0) |
| 35 | + #endif |
| 36 | + |
| 37 | ++/* |
| 38 | ++ * Workaround for https://bugs.llvm.org/show_bug.cgi?id=42762. |
| 39 | ++ */ |
| 40 | ++#ifdef __clang__ |
| 41 | ++static inline void dcbz(void *addr) |
| 42 | ++{ |
| 43 | ++ __asm__ __volatile__ ("dcbz 0, %0" : : "r"(addr) : "memory"); |
| 44 | ++} |
| 45 | ++ |
| 46 | ++static inline void dcbi(void *addr) |
| 47 | ++{ |
| 48 | ++ __asm__ __volatile__ ("dcbi 0, %0" : : "r"(addr) : "memory"); |
| 49 | ++} |
| 50 | ++ |
| 51 | ++static inline void dcbf(void *addr) |
| 52 | ++{ |
| 53 | ++ __asm__ __volatile__ ("dcbf 0, %0" : : "r"(addr) : "memory"); |
| 54 | ++} |
| 55 | ++ |
| 56 | ++static inline void dcbst(void *addr) |
| 57 | ++{ |
| 58 | ++ __asm__ __volatile__ ("dcbst 0, %0" : : "r"(addr) : "memory"); |
| 59 | ++} |
| 60 | ++#else |
| 61 | + static inline void dcbz(void *addr) |
| 62 | + { |
| 63 | + __asm__ __volatile__ ("dcbz %y0" : : "Z"(*(u8 *)addr) : "memory"); |
| 64 | +@@ -124,6 +148,7 @@ static inline void dcbst(void *addr) |
| 65 | + { |
| 66 | + __asm__ __volatile__ ("dcbst %y0" : : "Z"(*(u8 *)addr) : "memory"); |
| 67 | + } |
| 68 | ++#endif /* __clang__ */ |
| 69 | + #endif /* !__ASSEMBLY__ */ |
| 70 | + #endif /* __KERNEL__ */ |
| 71 | + #endif /* _ASM_POWERPC_CACHE_H */ |
| 72 | +-- |
| 73 | +2.22.0 |
| 74 | + |
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