patches: Unbreak ppc32

It does not seem like this is going to be dealt with in a timely manner;
revert the problematic commit for clang so that everything works again.

Presubmit: https://travis-ci.com/nathanchance/continuous-integration/builds/121137965

[skip ci]

Signed-off-by: Nathan Chancellor <natechancellor@gmail.com>

Author: nathanchance

patches/llvm-all/linux-next

@@ -0,0 +1 @@
+linux

patches/llvm-all/linux/ppc32/0001-powerpc-workaround-clang-codegen-bug-in-dcbz.patch

@@ -0,0 +1,74 @@
+From 4f764e21e589c2c5704342237259cb2a8c0a304a Mon Sep 17 00:00:00 2001
+From: Nick Desaulniers <ndesaulniers@google.com>
+Date: Mon, 29 Jul 2019 10:12:14 -0700
+Subject: [PATCH] powerpc: workaround clang codegen bug in dcbz
+
+Commit 6c5875843b87 ("powerpc: slightly improve cache helpers") exposed
+what looks like a codegen bug in Clang's handling of `%y` output
+template with `Z` constraint. This is resulting in panics during boot
+for 32b powerpc builds w/ Clang, as reported by our CI.
+
+Add back the original code that worked behind a preprocessor check for
+__clang__ until we can fix LLVM.
+
+Further, it seems that clang allnoconfig builds are unhappy with `Z`, as
+reported by 0day bot. This is likely because Clang warns about inline
+asm constraints when the constraint requires inlining to be semantically
+valid.
+
+Link: https://bugs.llvm.org/show_bug.cgi?id=42762
+Link: https://github.com/ClangBuiltLinux/linux/issues/593
+Link: https://lore.kernel.org/lkml/20190721075846.GA97701@archlinux-threadripper/
+Reported-by: Nathan Chancellor <natechancellor@gmail.com>
+Reported-by: kbuild test robot <lkp@intel.com>
+Signed-off-by: Nick Desaulniers <ndesaulniers@google.com>
+---
+ arch/powerpc/include/asm/cache.h | 25 +++++++++++++++++++++++++
+ 1 file changed, 25 insertions(+)
+
+diff --git a/arch/powerpc/include/asm/cache.h b/arch/powerpc/include/asm/cache.h
+index b3388d95f451..72983da94dce 100644
+--- a/arch/powerpc/include/asm/cache.h
++++ b/arch/powerpc/include/asm/cache.h
+@@ -105,6 +105,30 @@ extern void _set_L3CR(unsigned long);
+ #define _set_L3CR(val)	do { } while(0)
+ #endif
+ 
++/*
++ * Workaround for https://bugs.llvm.org/show_bug.cgi?id=42762.
++ */
++#ifdef __clang__
++static inline void dcbz(void *addr)
++{
++	__asm__ __volatile__ ("dcbz 0, %0" : : "r"(addr) : "memory");
++}
++
++static inline void dcbi(void *addr)
++{
++	__asm__ __volatile__ ("dcbi 0, %0" : : "r"(addr) : "memory");
++}
++
++static inline void dcbf(void *addr)
++{
++	__asm__ __volatile__ ("dcbf 0, %0" : : "r"(addr) : "memory");
++}
++
++static inline void dcbst(void *addr)
++{
++	__asm__ __volatile__ ("dcbst 0, %0" : : "r"(addr) : "memory");
++}
++#else
+ static inline void dcbz(void *addr)
+ {
+ 	__asm__ __volatile__ ("dcbz %y0" : : "Z"(*(u8 *)addr) : "memory");
+@@ -124,6 +148,7 @@ static inline void dcbst(void *addr)
+ {
+ 	__asm__ __volatile__ ("dcbst %y0" : : "Z"(*(u8 *)addr) : "memory");
+ }
++#endif /* __clang__ */
+ #endif /* !__ASSEMBLY__ */
+ #endif /* __KERNEL__ */
+ #endif /* _ASM_POWERPC_CACHE_H */
+-- 
+2.22.0
+