Clocked SR Flip-Flop: Truth Table, Circuit Diagram, Working

This repository contains supporting media (GIFs and images) for the article on Clocked SR Flip-Flop, a key digital electronics component used for data storage and control in synchronized circuits.

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🔧 Overview

The Clocked SR (Set-Reset) Flip-Flop is an improved version of the SR latch. It includes a clock input, making it a synchronous circuit. The output only changes on the clock edge, helping avoid unwanted state changes.

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⚙️ Inputs and Outputs

• Inputs:

  • S (Set)
  • R (Reset)
  • CLK (Clock)

• Outputs:

  • Q (Normal)
  • Q̅ (Inverted)

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📊 Truth Table

CLK	S	R	Q (Next State)	Description
0	X	X	No Change	Clock is LOW
1	0	0	No Change	Hold
1	1	0	1	Set
1	0	1	0	Reset
1	1	1	Invalid	Forbidden State

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🧪 Circuit Implementations

NAND Gate Version

• Uses a basic SR latch made from NAND gates
• Clocked using two additional NAND gates

NOR Gate Version

• Uses a basic SR latch made from NOR gates
• Clocked using two AND gates

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🧠 Working Summary

• When CLK = 0: Inputs are ignored, output remains unchanged.
• When CLK = 1:
  • S = 1, R = 0 → Set
  • S = 0, R = 1 → Reset
  • S = 0, R = 0 → Hold
  • S = 1, R = 1 → Invalid

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📁 Contents

This repository includes:

• GIF videos showing simulations of Clocked SR Flip-Flop using NAND and NOR gates
• Circuit diagrams and symbol illustrations

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📌 Applications

• Digital memory registers
• Data synchronization
• Sequential state machines
• Timing-critical control logic

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⚠️ Avoid using both Set and Reset HIGH when the Clock is active — it leads to an invalid state.