This repository contains the final report of a university project for UNIBO Master's degree in Electronics. It is focused on the design, simulation, and characterization of a digital adder based on a modified Kogge-Stone architecture with BLC optimization.
The project was developed using Cadence Virtuoso and aimed to optimize latency in digital addition circuits, comparing trade-offs with area and power consumption. The adder operates on 8-bit inputs and supports both addition and subtraction operations.
- XOR blocks for sum/subtract logic
- “Single-bit” blocks for generate/propagate signal generation
- O-operator blocks with buffering logic for timing balance
- Registers for synchronous operation
- Static Power Consumption: ~20.9 nW
- Energy per Clock Cycle: ranges from ~98 fJ to ~349 fJ depending on activity level
- Area Growth: proportional to N × log₂N
- Performance: significantly lower latency compared to other carry-lookahead adders (e.g. Carry Bypass, Carry Select)
The full project report is available here: kogge-stone-BLC-8bit.pdf