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The FPGA High Bandwith Memory Interfacing and Monitoring Project

DRGBL Logo

Hi! We are BYU Capstone Team 17 (DRGBL)!

We are working on the FPGA High-Bandwidth Memory Interfacing and Monitoring Project!

Video about project

HBM GUI Tutorial

Documentation / Background Info

Our Project Documentation and Background information can be found on our Wiki

We also made a YouTube video detailing our contributions to the LiteX project and our work on High-Bandwidth Memory. You can watch it here: YouTube Link

Contact us

If you have any questions, please reach out at capstone2022.team17@gmail.com.

Overview of Project Implementation

DRGBL Project

Project Requirements

The system requirements can be summarized as follows:

  • A memory bandwidth generator module that can be applied to each of the 32 available AXI interfaces to the HBM
  • Each memory bandwidth generator module has these functionalities
    • Continuous reads to HBM of a specified number of bytes a specified number of times.
    • Continuous writes to HBM of a specified number of bytes a specified number of times
  • A hardware counter records the number of transactions and the number of clock cycles to determine the transaction speed
  • A program that communicates with the board over UART to activate the BISTs

As part of this, we have forked 3 different repositories for this project.

Forked Repositories

Forked LiteX

  • This is where most of the SOC/AXI implementation is located and also where we have implemented new BIOS code.

LiteHBM

  • This contains all of our project files as a way to put everything together as a seprate module. We ended up giving up on getting that to work becuse it would make it more difficult for the user to use our code.

Forked litex-boards

  • This is where most of our code is. Here is the exact file that is being updated for this project. It's called the xilinx_alveo_u280.py. We have updated this file to have the cpu dependent on the DRAM and now we have full access to the 32 HBM ports.

What we are working on

We now have working Bandwidth generators and are working on BIOS implementations of their controll. We are also working on data colection and data analysis.

To see a more detailed and individualized tasks check out our project Here.

What is in this Repository

  • rgb_pwm has a basic Migen script that gradually changes the RGB leds to different colors.
  • rgb_pwm_withSoC is a basic SoC used to control the rgb leds.

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