Simulate a 5 stage - Instrcuton Fetch | Decode | Execute | Memory | Write back Simple processor with Instruction Level Parallelism (ILP) including buffers, handling data and control hazards by stalling. Analyzes the pipeline behaviour and perfomance by tracking clockcycles, instruction count, and calculating CPI.
ICache and DCache are provided and are perfect (no cache misses), run the instrution set in the simulator reflecting the changes in DCache in the output directory. Output.txt contains the analytics - Instruction Count, Clock cycles, CPI etc.
Go through the Problem Statement for a detailed description of the problem.