Hardware Infrastructure - RISC-V Pipeline Project

This repository contains the base files for the Hardware Infrastructure (IF674) project at CIn-UFPE. The project's goal is to implement instructions in a RISC-V processor using SystemVerilog.

Group formed by Artur Vinicius Fernandes (arturvpf), Caio Vilas Boas (ccnvb), Fabio Pereira de Miranda (fpm3), Felipe Mateus Barreto (fmfb) and João Victor Nascimento (jvsn2).

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Instructions

The table below shows the status of instructions implemented so far:

#	Instruction	Implemented	Tested	Working
1	BEQ	✅	✅	✅
2	LW	✅	✅	✅
3	SW	✅	✅	✅
4	ADD	✅	✅	✅
5	AND	✅	✅	✅

#	Instruction	Implemented	Tested	Working
1	JAL	✅	✅	✅
2	JALR	✅	✅	✅
3	BNE	✅	✅	✅
4	BLT	✅	✅	✅
5	BGE	✅	✅	✅
6	LB	✅	✅	✅
7	LH	✅	✅	✅
8	LBU	✅	✅	✅
9	SB	✅	✅	✅
10	SH	✅	✅	✅
11	SLTI	✅	✅	✅
12	ADDI	✅	✅	✅
13	SLLI	✅	✅	✅
14	SRLI	✅	✅	✅
15	SRAI	✅	✅	✅
16	SUB	✅	✅	✅
17	SLT	✅	✅	✅
18	XOR	✅	✅	✅
19	OR	✅	✅	✅
20	HALT	✅	✅	✅

Notes

• Instructions 1 to 19 are official part of the RV32I instruction set. The HALT pseudo-instruction is used in assembly languages to indicate the end of a program or pause its execution. When the processor encounters the HALT instruction, a specific action is usually triggered, such as inserting zeros (or other predetermined value) into the processor pipeline and stopping the program counter (PC), preventing the execution of new instructions. This functionality allows the programmer to have control over the program flow, explicitly indicating when the program should terminate.

Repository structure

The repository is organized as follows:

• design: Contains the RISC-V processor project source code.
• doc: Contains more explanations about the implementation.
• sim: Contains simulation files and results, for use in testing.
• verif: Contains testbench files and instructions on how to test the project.

Resources

• To start studying the RISC-V instruction set, consult:

  • RISC-V Instruction Set Manual Volume I: User-Level ISA - Document Version 2.2
  • risc-v isa pages, by msyksphinz

• To simulate and test the RISC-V processor project, use:

  • ModelSim-Intel® FPGAs Standard Edition Software Version 20.1.1

• To verify results:

  • Compare your results with examples provided in sim
  • Use the CompSim simulator
  • Use the RISC-V Interpreter, by Cornell University

2. Pull Request: If you are familiar with the pull request process, feel free to send your changes directly through a pull request. Make sure to clearly describe the changes made and the reason behind them.