MESI_Directory_Cache-Coherence

A directory-based MESI protocol cache coherence multicore system.

Configuration

CPU

• 2 cores
• RISC-V instruction

Cache

• Size: 128B
• 4 Sets
• 4-way associativity

Memory

• Size: 2kB
• Block size: 64 bits

Interconnect

• crossbar

FPGA

• ZYNQ-Z2 (xc7z020clg400-1)

System architecture

Cache architecture

Transaction

Transaction	Goal of requestor
GetShared(Get_S)	Obtain block in Shared (read-only) state
GetModified (Get_M)	Obtain block in Modified (read-only) state
PutShared (Put_S)	Evict block in Shared state
PutExclusive (Put_E)	Evict block in Exclusive state
PutModified (Put_M)	Evict block in Modified state

FSM

• The state diagram of a CPU issuing requests to its cache

• The state diagram of receiving requests from the caches of other CPUs

Cache Coherency & I/O ordering

Transition Table

Cache controller

Directory

A Primer on Memory Consistency and Cache Coherence

Testbench

In tb.v, I designed 23 read and write instructions that cover scenarios such as local CPU read/write hits and misses, forwarded reads/writes from other CPUs, invalidation, LRU replacement policy, and other possible situations represented in the above FSM and transition table.

If all tests pass, you will be rewarded with a cute Pikachu.

Synthesis & Implementation

Utilization

Resource	Utilization
LUT	2045
FF	1396
IO	6
BUFG	1

device

Schematic