A couple of updates to prepare the support of GNAT FSF 15

arch/ARM/cortex_m/src/semihosting-filesystem.adb

@@ -394,6 +394,10 @@ package body Semihosting.Filesystem is
    function Flush
      (This : in out SHFS_File_Handle)
       return Status_Code
-   is (OK);
+   is
+      pragma Unreferenced (This);
+   begin
+      return OK;
+   end Flush;
 
 end Semihosting.Filesystem;

arch/RISC-V/SiFive/drivers/fe310-time.adb

@@ -32,7 +32,6 @@
 --                                                                          --
 ------------------------------------------------------------------------------
 
-with FE310; use FE310;
 with FE310.CLINT; use FE310.CLINT;
 
 package body FE310.Time is

arch/RISC-V/src/riscv-csr_generic.adb

@@ -33,14 +33,17 @@ with System.Machine_Code; use System.Machine_Code;
 
 package body RISCV.CSR_Generic is
 
+   NL : constant String := ASCII.CR & ASCII.LF;
+
    --------------
    -- Read_CSR --
    --------------
 
    function Read_CSR return Reg_Type is
       Ret : Reg_Type;
    begin
-      Asm ("csrr %0, " & Reg_Name,
+      Asm (".option arch, +zicsr" & NL &
+           "csrr %0, " & Reg_Name,
            Outputs  => Reg_Type'Asm_Output ("=r", Ret),
            Volatile => True);
       return Ret;
@@ -52,7 +55,8 @@ package body RISCV.CSR_Generic is
 
    procedure Write_CSR (Val : Reg_Type) is
    begin
-      Asm ("csrw " & Reg_Name & ", %0",
+      Asm (".option arch, +zicsr" & NL &
+           "csrw " & Reg_Name & ", %0",
            Inputs   => Reg_Type'Asm_Input ("r", Val),
            Volatile => True);
    end Write_CSR;
@@ -64,7 +68,8 @@ package body RISCV.CSR_Generic is
    function Swap_CSR (Val : Reg_Type) return Reg_Type is
       Ret : Reg_Type;
    begin
-      Asm ("csrrw %1, " & Reg_Name & ", %0",
+      Asm (".option arch, +zicsr" & NL &
+           "csrrw %1, " & Reg_Name & ", %0",
            Inputs   => Reg_Type'Asm_Input ("r", Val),
            Outputs  => Reg_Type'Asm_Output ("=r", Ret),
            Volatile => True);
@@ -77,7 +82,8 @@ package body RISCV.CSR_Generic is
 
    procedure Set_Bits_CSR (Val : Reg_Type) is
    begin
-      Asm ("csrs " & Reg_Name & ", %0",
+      Asm (".option arch, +zicsr" & NL &
+           "csrs " & Reg_Name & ", %0",
            Inputs   => Reg_Type'Asm_Input ("r", Val),
            Volatile => True);
    end Set_Bits_CSR;
@@ -89,7 +95,8 @@ package body RISCV.CSR_Generic is
    function Read_And_Set_Bits_CSR (Val : Reg_Type) return Reg_Type is
       Ret : Reg_Type;
    begin
-      Asm ("csrrs %1, " & Reg_Name & ", %0",
+      Asm (".option arch, +zicsr" & NL &
+           "csrrs %1, " & Reg_Name & ", %0",
            Inputs   => Reg_Type'Asm_Input ("r", Val),
            Outputs  => Reg_Type'Asm_Output ("=r", Ret),
            Volatile => True);
@@ -102,7 +109,8 @@ package body RISCV.CSR_Generic is
 
    procedure Clear_Bits_CSR (Val : Reg_Type) is
    begin
-      Asm ("csrc " & Reg_Name & ", %0",
+      Asm (".option arch, +zicsr" & NL &
+           "csrc " & Reg_Name & ", %0",
            Inputs   => Reg_Type'Asm_Input ("r", Val),
            Volatile => True);
    end Clear_Bits_CSR;
@@ -114,7 +122,8 @@ package body RISCV.CSR_Generic is
    function Read_And_Clear_Bits_CSR (Val : Reg_Type) return Reg_Type is
       Ret : Reg_Type;
    begin
-      Asm ("csrrc %1, " & Reg_Name & ", %0",
+      Asm (".option arch, +zicsr" & NL &
+           "csrrc %1, " & Reg_Name & ", %0",
            Inputs   => Reg_Type'Asm_Input ("r", Val),
            Outputs  => Reg_Type'Asm_Output ("=r", Ret),
            Volatile => True);

boards/HiFive1/hifive1_zfp.gpr

@@ -8,7 +8,7 @@ library project HiFive1_ZFP is
    Build_Checks : Build_Checks_Type := external ("ADL_BUILD_CHECKS", "Disabled");
 
    --  Target architecture
-   for Target use "riscv32-elf";
+   for Target use "riscv64-elf";
    Target := Project'Target;
 
    --  Callgraph info is not available on all architectures

boards/HiFive1_rev_B/hifive1_rev_b_zfp.gpr

@@ -8,13 +8,13 @@ library project HiFive1_rev_B_ZFP is
    Build_Checks : Build_Checks_Type := external ("ADL_BUILD_CHECKS", "Disabled");
 
    --  Target architecture
-   for Target use "riscv32-elf";
+   for Target use "riscv64-elf";
    Target := Project'Target;
 
    --  Callgraph info is not available on all architectures
    Callgraph_Switch := ();
    case Target is
-      when "riscv32-unknown-elf" => null;
+      when "riscv64-elf" => null;
       when others => Callgraph_Switch := ("-fcallgraph-info=su");
    end case;
 

boards/Unleashed/unleashed_full.gpr

@@ -8,13 +8,13 @@ library project Unleashed_Full is
    Build_Checks : Build_Checks_Type := external ("ADL_BUILD_CHECKS", "Disabled");
 
    --  Target architecture
-   for Target use "riscv32-elf";
+   for Target use "riscv64-elf";
    Target := Project'Target;
 
    --  Callgraph info is not available on all architectures
    Callgraph_Switch := ();
    case Target is
-      when "riscv32-unknown-elf" => null;
+      when "riscv64-elf" => null;
       when others => Callgraph_Switch := ("-fcallgraph-info=su");
    end case;
 

boards/Unleashed/unleashed_sfp.gpr

@@ -8,13 +8,13 @@ library project Unleashed_SFP is
    Build_Checks : Build_Checks_Type := external ("ADL_BUILD_CHECKS", "Disabled");
 
    --  Target architecture
-   for Target use "riscv32-elf";
+   for Target use "riscv64-elf";
    Target := Project'Target;
 
    --  Callgraph info is not available on all architectures
    Callgraph_Switch := ();
    case Target is
-      when "riscv32-unknown-elf" => null;
+      when "riscv64-elf" => null;
       when others => Callgraph_Switch := ("-fcallgraph-info=su");
    end case;
 

boards/Unleashed/unleashed_zfp.gpr

@@ -8,13 +8,13 @@ library project Unleashed_ZFP is
    Build_Checks : Build_Checks_Type := external ("ADL_BUILD_CHECKS", "Disabled");
 
    --  Target architecture
-   for Target use "riscv32-elf";
+   for Target use "riscv64-elf";
    Target := Project'Target;
 
    --  Callgraph info is not available on all architectures
    Callgraph_Switch := ();
    case Target is
-      when "riscv32-unknown-elf" => null;
+      when "riscv64-elf" => null;
       when others => Callgraph_Switch := ("-fcallgraph-info=su");
    end case;
 

examples/HiFive1/hifive1_example.gpr

@@ -3,7 +3,7 @@ with "../../boards/HiFive1/hifive1_zfp.gpr";
 project HiFive1_Example is
 
   for Runtime ("ada") use HiFive1_ZFP'Runtime ("Ada");
-  for Target use "riscv32-elf";
+  for Target use "riscv64-elf";
   for Main use ("main.adb");
   for Languages use ("Ada");
   for Source_Dirs use ("src");

examples/HiFive1_rev_B/README.md

@@ -22,7 +22,7 @@ This will create a folder named `obj` in the same directory with the elf-formate
 binary plus some auxiliary files. Inside this folder run the following command
 to create the `hex` file:
 
-`$ riscv32-elf-objcopy -O ihex main main.hex`
+`$ riscv64-elf-objcopy -O ihex main main.hex`
 
 This new revision of the HiFive board allows the `hex` file to be uploaded
 through the USB connection that should appear in your file manager. Just copy

examples/HiFive1_rev_B/hifive1_rev_B_example.gpr

@@ -3,7 +3,7 @@ with "../../boards/HiFive1_rev_B/hifive1_rev_b_zfp.gpr";
 project HiFive1_rev_B_Example is
 
   for Runtime ("ada") use HiFive1_rev_B_ZFP'Runtime ("Ada");
-  for Target use "riscv32-elf";
+  for Target use "riscv64-elf";
   for Main use ("main.adb");
   for Languages use ("Ada");
   for Source_Dirs use ("src");

scripts/build_all_examples.py

@@ -173,7 +173,7 @@ def gprbuild(project_file, debug=False):
             ]
 
 # Check if RISC-V32 compiler is available
-if distutils.spawn.find_executable("riscv32-elf-gnatls"):
+if distutils.spawn.find_executable("riscv64-elf-gnatls"):
 
     # Add RISC-V32 projects
     projects += ["/examples/HiFive1/hifive1_example.gpr"]

scripts/config/__init__.py

@@ -67,7 +67,7 @@ def target(self):
             if arch == "ARM":
                 target = "arm-eabi"
             elif arch == "RISC-V":
-                target = "riscv32-elf"
+                target = "riscv64-elf"
 
         return target