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RISC‐I Emulator
Lucas Perônico Barbotin edited this page Nov 1, 2024
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This is a wiki about the RISC-I Emulator project developed by me (710lucas)!
The emulator is divided into 4 main sections:
- CPU
- Memory
- I/O
- BUS
Both I/O and Memory are Bus modules (see busModule.hpp for more details).
The communication between the CPU and the bus modules occur trough the BUS (see systemBus.hpp for more details and instructions).