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alexrpalexrp
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Merge pull request #24302 from alexrp/riscv
Native RISC-V bootstrap and test fixes
2 parents ee6d194 + 8e511e0 commit edf785d

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17 files changed

+142
-20
lines changed

17 files changed

+142
-20
lines changed

‎doc/langref/runtime_shrExact_overflow.zig

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,10 +1,13 @@
1+
const builtin = @import("builtin");
12
const std = @import("std");
23

34
pub fn main() void {
45
var x: u8 = 0b10101010; // runtime-known
56
_ = &x;
67
const y = @shrExact(x, 2);
78
std.debug.print("value: {}\n", .{y});
9+
10+
if (builtin.cpu.arch.isRISCV() and builtin.zig_backend == .stage2_llvm) @panic("https://github.com/ziglang/zig/issues/24304");
811
}
912

1013
// exe=fail

‎lib/libunwind/src/UnwindCursor.hpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -150,7 +150,7 @@ bool DwarfFDECache<A>::_registeredForDyldUnloads = false;
150150
#endif
151151

152152
template <typename A>
153-
typename A::pint_t DwarfFDECache<A>::findFDE(pint_t mh, pint_t pc) {
153+
typename DwarfFDECache<A>::pint_t DwarfFDECache<A>::findFDE(pint_t mh, pint_t pc) {
154154
pint_t result = 0;
155155
_LIBUNWIND_LOG_IF_FALSE(_lock.lock_shared());
156156
for (entry *p = _buffer; p < _bufferUsed; ++p) {

‎lib/std/Build/Step/CheckObject.zig

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2270,7 +2270,7 @@ const ElfDumper = struct {
22702270
try writer.print(" {s}", .{sym_bind});
22712271
}
22722272

2273-
const sym_vis = @as(elf.STV, @enumFromInt(sym.st_other));
2273+
const sym_vis = @as(elf.STV, @enumFromInt(@as(u2, @truncate(sym.st_other))));
22742274
try writer.print(" {s}", .{@tagName(sym_vis)});
22752275

22762276
const sym_name = switch (sym.st_type()) {

‎lib/std/bit_set.zig

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1699,6 +1699,7 @@ fn testStaticBitSet(comptime Set: type) !void {
16991699

17001700
test IntegerBitSet {
17011701
if (builtin.zig_backend == .stage2_c) return error.SkipZigTest;
1702+
if (comptime builtin.cpu.has(.riscv, .v) and builtin.zig_backend == .stage2_llvm) return error.SkipZigTest; // https://github.com/ziglang/zig/issues/24300
17021703

17031704
try testStaticBitSet(IntegerBitSet(0));
17041705
try testStaticBitSet(IntegerBitSet(1));

‎lib/std/crypto/salsa20.zig

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -557,6 +557,8 @@ pub const SealedBox = struct {
557557
const htest = @import("test.zig");
558558

559559
test "(x)salsa20" {
560+
if (builtin.cpu.has(.riscv, .v) and builtin.zig_backend == .stage2_llvm) return error.SkipZigTest; // https://github.com/ziglang/zig/issues/24299
561+
560562
const key = [_]u8{0x69} ** 32;
561563
const nonce = [_]u8{0x42} ** 8;
562564
const msg = [_]u8{0} ** 20;
@@ -600,6 +602,8 @@ test "xsalsa20poly1305 secretbox" {
600602
}
601603

602604
test "xsalsa20poly1305 box" {
605+
if (builtin.cpu.has(.riscv, .v) and builtin.zig_backend == .stage2_llvm) return error.SkipZigTest; // https://github.com/ziglang/zig/issues/24299
606+
603607
var msg: [100]u8 = undefined;
604608
var msg2: [msg.len]u8 = undefined;
605609
var nonce: [Box.nonce_length]u8 = undefined;
@@ -614,6 +618,8 @@ test "xsalsa20poly1305 box" {
614618
}
615619

616620
test "xsalsa20poly1305 sealedbox" {
621+
if (builtin.cpu.has(.riscv, .v) and builtin.zig_backend == .stage2_llvm) return error.SkipZigTest; // https://github.com/ziglang/zig/issues/24299
622+
617623
var msg: [100]u8 = undefined;
618624
var msg2: [msg.len]u8 = undefined;
619625
var boxed: [msg.len + SealedBox.seal_length]u8 = undefined;

‎lib/std/os/linux/riscv32.zig

Lines changed: 36 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -7,6 +7,8 @@ const SYS = linux.SYS;
77
const uid_t = std.os.linux.uid_t;
88
const gid_t = std.os.linux.gid_t;
99
const pid_t = std.os.linux.pid_t;
10+
const stack_t = linux.stack_t;
11+
const sigset_t = linux.sigset_t;
1012
const sockaddr = linux.sockaddr;
1113
const socklen_t = linux.socklen_t;
1214
const timespec = std.os.linux.timespec;
@@ -261,8 +263,40 @@ pub const VDSO = struct {
261263
pub const CGT_VER = "LINUX_4.15";
262264
};
263265

264-
/// TODO
265-
pub const ucontext_t = void;
266+
pub const f_ext_state = extern struct {
267+
f: [32]f32,
268+
fcsr: u32,
269+
};
270+
271+
pub const d_ext_state = extern struct {
272+
f: [32]f64,
273+
fcsr: u32,
274+
};
275+
276+
pub const q_ext_state = extern struct {
277+
f: [32]f128,
278+
fcsr: u32,
279+
_reserved: [3]u32,
280+
};
281+
282+
pub const fpstate = extern union {
283+
f: f_ext_state,
284+
d: d_ext_state,
285+
q: q_ext_state,
286+
};
287+
288+
pub const mcontext_t = extern struct {
289+
gregs: [32]u32,
290+
fpregs: fpstate,
291+
};
292+
293+
pub const ucontext_t = extern struct {
294+
flags: c_ulong,
295+
link: ?*ucontext_t,
296+
stack: stack_t,
297+
sigmask: [1024 / @bitSizeOf(c_ulong)]c_ulong, // Currently a libc-compatible (1024-bit) sigmask
298+
mcontext: mcontext_t,
299+
};
266300

267301
/// TODO
268302
pub const getcontext = {};

‎lib/std/os/linux/riscv64.zig

Lines changed: 36 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -7,6 +7,8 @@ const SYS = linux.SYS;
77
const uid_t = std.os.linux.uid_t;
88
const gid_t = std.os.linux.gid_t;
99
const pid_t = std.os.linux.pid_t;
10+
const stack_t = linux.stack_t;
11+
const sigset_t = linux.sigset_t;
1012
const sockaddr = linux.sockaddr;
1113
const socklen_t = linux.socklen_t;
1214
const timespec = std.os.linux.timespec;
@@ -261,8 +263,40 @@ pub const VDSO = struct {
261263
pub const CGT_VER = "LINUX_4.15";
262264
};
263265

264-
/// TODO
265-
pub const ucontext_t = void;
266+
pub const f_ext_state = extern struct {
267+
f: [32]f32,
268+
fcsr: u32,
269+
};
270+
271+
pub const d_ext_state = extern struct {
272+
f: [32]f64,
273+
fcsr: u32,
274+
};
275+
276+
pub const q_ext_state = extern struct {
277+
f: [32]f128,
278+
fcsr: u32,
279+
_reserved: [3]u32,
280+
};
281+
282+
pub const fpstate = extern union {
283+
f: f_ext_state,
284+
d: d_ext_state,
285+
q: q_ext_state,
286+
};
287+
288+
pub const mcontext_t = extern struct {
289+
gregs: [32]u64,
290+
fpregs: fpstate,
291+
};
292+
293+
pub const ucontext_t = extern struct {
294+
flags: c_ulong,
295+
link: ?*ucontext_t,
296+
stack: stack_t,
297+
sigmask: [1024 / @bitSizeOf(c_ulong)]c_ulong, // Currently a libc-compatible (1024-bit) sigmask
298+
mcontext: mcontext_t,
299+
};
266300

267301
/// TODO
268302
pub const getcontext = {};

‎lib/std/simd.zig

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -9,6 +9,8 @@ const std = @import("std");
99
const builtin = @import("builtin");
1010

1111
pub fn suggestVectorLengthForCpu(comptime T: type, comptime cpu: std.Target.Cpu) ?comptime_int {
12+
@setEvalBranchQuota(2_000);
13+
1214
// This is guesswork, if you have better suggestions can add it or edit the current here
1315
const element_bit_size = @max(8, std.math.ceilPowerOfTwo(u16, @bitSizeOf(T)) catch unreachable);
1416
const vector_bit_size: u16 = blk: {

‎lib/std/zig/system/linux.zig

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -76,9 +76,11 @@ const RiscvCpuinfoImpl = struct {
7676

7777
const cpu_names = .{
7878
.{ "sifive,u54", &Target.riscv.cpu.sifive_u54 },
79+
.{ "sifive,u54-mc", &Target.riscv.cpu.sifive_u54 },
7980
.{ "sifive,u7", &Target.riscv.cpu.sifive_7_series },
8081
.{ "sifive,u74", &Target.riscv.cpu.sifive_u74 },
8182
.{ "sifive,u74-mc", &Target.riscv.cpu.sifive_u74 },
83+
.{ "spacemit,x60", &Target.riscv.cpu.spacemit_x60 },
8284
};
8385

8486
fn line_hook(self: *RiscvCpuinfoImpl, key: []const u8, value: []const u8) !bool {

‎src/codegen/llvm.zig

Lines changed: 7 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1068,6 +1068,9 @@ pub const Object = struct {
10681068
.full => .FullPreLink,
10691069
},
10701070
.allow_fast_isel = true,
1071+
// LLVM's RISC-V backend for some reason enables the machine outliner by default even
1072+
// though it's clearly not ready and produces multiple miscompilations in our std tests.
1073+
.allow_machine_outliner = !comp.root_mod.resolved_target.result.cpu.arch.isRISCV(),
10711074
.asm_filename = null,
10721075
.bin_filename = options.bin_path,
10731076
.llvm_ir_filename = options.post_ir_path,
@@ -6831,8 +6834,8 @@ pub const FuncGen = struct {
68316834

68326835
self.maybeMarkAllowZeroAccess(slice_ty.ptrInfo(zcu));
68336836

6834-
const elem_alignment = elem_ty.abiAlignment(zcu).toLlvm();
6835-
return self.loadByRef(ptr, elem_ty, elem_alignment, if (slice_ty.isVolatilePtr(zcu)) .@"volatile" else .normal);
6837+
const slice_align = (slice_ty.ptrAlignment(zcu).min(elem_ty.abiAlignment(zcu))).toLlvm();
6838+
return self.loadByRef(ptr, elem_ty, slice_align, if (slice_ty.isVolatilePtr(zcu)) .@"volatile" else .normal);
68366839
}
68376840

68386841
self.maybeMarkAllowZeroAccess(slice_ty.ptrInfo(zcu));
@@ -6909,8 +6912,8 @@ pub const FuncGen = struct {
69096912

69106913
self.maybeMarkAllowZeroAccess(ptr_ty.ptrInfo(zcu));
69116914

6912-
const elem_alignment = elem_ty.abiAlignment(zcu).toLlvm();
6913-
return self.loadByRef(ptr, elem_ty, elem_alignment, if (ptr_ty.isVolatilePtr(zcu)) .@"volatile" else .normal);
6915+
const ptr_align = (ptr_ty.ptrAlignment(zcu).min(elem_ty.abiAlignment(zcu))).toLlvm();
6916+
return self.loadByRef(ptr, elem_ty, ptr_align, if (ptr_ty.isVolatilePtr(zcu)) .@"volatile" else .normal);
69146917
}
69156918

69166919
self.maybeMarkAllowZeroAccess(ptr_ty.ptrInfo(zcu));

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