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stage2: add compile errors for comptime @shrExact and @divExact failures
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4 files changed

+31
-5
lines changed

4 files changed

+31
-5
lines changed

src/Sema.zig

Lines changed: 9 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -10441,7 +10441,7 @@ fn zirShr(
1044110441
// Detect if any ones would be shifted out.
1044210442
const truncated = try lhs_val.intTruncBitsAsValue(lhs_ty, sema.arena, .unsigned, rhs_val, target);
1044310443
if (!(try truncated.compareWithZeroAdvanced(.eq, sema.kit(block, src)))) {
10444-
return sema.addConstUndef(lhs_ty);
10444+
return sema.fail(block, src, "exact shift shifted out 1 bits", .{});
1044510445
}
1044610446
}
1044710447
const val = try lhs_val.shr(rhs_val, lhs_ty, sema.arena, target);
@@ -11346,13 +11346,19 @@ fn zirDivExact(sema: *Sema, block: *Block, inst: Zir.Inst.Index) CompileError!Ai
1134611346
if (maybe_lhs_val) |lhs_val| {
1134711347
if (maybe_rhs_val) |rhs_val| {
1134811348
if (is_int) {
11349-
// TODO: emit compile error if there is a remainder
11349+
const modulus_val = try lhs_val.intMod(rhs_val, resolved_type, sema.arena, target);
11350+
if (modulus_val.compareWithZero(.neq)) {
11351+
return sema.fail(block, src, "exact division produced remainder", .{});
11352+
}
1135011353
return sema.addConstant(
1135111354
resolved_type,
1135211355
try lhs_val.intDiv(rhs_val, resolved_type, sema.arena, target),
1135311356
);
1135411357
} else {
11355-
// TODO: emit compile error if there is a remainder
11358+
const modulus_val = try lhs_val.floatMod(rhs_val, resolved_type, sema.arena, target);
11359+
if (modulus_val.compareWithZero(.neq)) {
11360+
return sema.fail(block, src, "exact division produced remainder", .{});
11361+
}
1135611362
return sema.addConstant(
1135711363
resolved_type,
1135811364
try lhs_val.floatDiv(rhs_val, resolved_type, sema.arena, target),
Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,10 @@
1+
comptime {
2+
const x = @divExact(10, 3);
3+
_ = x;
4+
}
5+
6+
// error
7+
// backend=llvm
8+
// target=native
9+
//
10+
// :2:15: error: exact division produced remainder
Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,10 @@
1+
comptime {
2+
const x = @divExact(10.0, 3.0);
3+
_ = x;
4+
}
5+
6+
// error
7+
// backend=llvm
8+
// target=native
9+
//
10+
// :2:15: error: exact division produced remainder

test/cases/compile_errors/stage1/obj/shrExact_shifts_out_1_bits.zig renamed to test/cases/compile_errors/shrExact_shifts_out_1_bits.zig

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@ comptime {
44
}
55

66
// error
7-
// backend=stage1
7+
// backend=llvm
88
// target=native
99
//
10-
// tmp.zig:2:15: error: exact shift shifted out 1 bits
10+
// :2:15: error: exact shift shifted out 1 bits

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