diff --git a/boards/adi/eval_adin1110ebz/adi_eval_adin1110ebz.dts b/boards/adi/eval_adin1110ebz/adi_eval_adin1110ebz.dts
index c61de385148ab..c49fa7eb82d96 100644
--- a/boards/adi/eval_adin1110ebz/adi_eval_adin1110ebz.dts
+++ b/boards/adi/eval_adin1110ebz/adi_eval_adin1110ebz.dts
@@ -308,7 +308,7 @@ zephyr_udc0: &usbotg_fs {
 
 	sram {
 		bank@0 {
-			reg = <0x0>;
+			reg = <STM32_FMC_NORSRAM_BANK1>;
 			st,control = <STM32_FMC_DATA_ADDRESS_MUX_DISABLE
 				      STM32_FMC_MEMORY_TYPE_SRAM
 				      STM32_FMC_NORSRAM_MEM_BUS_WIDTH_16
diff --git a/boards/st/stm32h573i_dk/stm32h573i_dk.dts b/boards/st/stm32h573i_dk/stm32h573i_dk.dts
index c431357be226a..3bd1c61c8ce5f 100644
--- a/boards/st/stm32h573i_dk/stm32h573i_dk.dts
+++ b/boards/st/stm32h573i_dk/stm32h573i_dk.dts
@@ -110,21 +110,21 @@
 		#size-cells = <0>;
 
 		bank@0 {
-			reg = <0x0>;
+			reg = <STM32_FMC_NORSRAM_BANK1>;
 			st,control = <STM32_FMC_DATA_ADDRESS_MUX_DISABLE
-				STM32_FMC_MEMORY_TYPE_SRAM
-				STM32_FMC_NORSRAM_MEM_BUS_WIDTH_16
-				STM32_FMC_BURST_ACCESS_MODE_DISABLE
-				STM32_FMC_WAIT_SIGNAL_POLARITY_LOW
-				STM32_FMC_WAIT_TIMING_BEFORE_WS
-				STM32_FMC_WRITE_OPERATION_ENABLE
-				STM32_FMC_WAIT_SIGNAL_DISABLE
-				STM32_FMC_EXTENDED_MODE_DISABLE
-				STM32_FMC_ASYNCHRONOUS_WAIT_DISABLE
-				STM32_FMC_WRITE_BURST_DISABLE
-				STM32_FMC_CONTINUOUS_CLOCK_SYNC_ONLY
-				STM32_FMC_WRITE_FIFO_DISABLE
-				STM32_FMC_PAGE_SIZE_NONE>;
+				      STM32_FMC_MEMORY_TYPE_SRAM
+				      STM32_FMC_NORSRAM_MEM_BUS_WIDTH_16
+				      STM32_FMC_BURST_ACCESS_MODE_DISABLE
+				      STM32_FMC_WAIT_SIGNAL_POLARITY_LOW
+				      STM32_FMC_WAIT_TIMING_BEFORE_WS
+				      STM32_FMC_WRITE_OPERATION_ENABLE
+				      STM32_FMC_WAIT_SIGNAL_DISABLE
+				      STM32_FMC_EXTENDED_MODE_DISABLE
+				      STM32_FMC_ASYNCHRONOUS_WAIT_DISABLE
+				      STM32_FMC_WRITE_BURST_DISABLE
+				      STM32_FMC_CONTINUOUS_CLOCK_SYNC_ONLY
+				      STM32_FMC_WRITE_FIFO_DISABLE
+				      STM32_FMC_PAGE_SIZE_NONE>;
 			st,timing = <1 1 32 0 2 2 STM32_FMC_ACCESS_MODE_A>;
 
 			fmc-mipi-dbi {
diff --git a/boards/st/stm32l562e_dk/stm32l562e_dk_common.dtsi b/boards/st/stm32l562e_dk/stm32l562e_dk_common.dtsi
index 0dcafde404f49..3a30b8071b8a8 100644
--- a/boards/st/stm32l562e_dk/stm32l562e_dk_common.dtsi
+++ b/boards/st/stm32l562e_dk/stm32l562e_dk_common.dtsi
@@ -69,21 +69,21 @@
 		#size-cells = <0>;
 
 		bank@0 {
-			reg = <0x0>;
+			reg = <STM32_FMC_NORSRAM_BANK1>;
 			st,control = <STM32_FMC_DATA_ADDRESS_MUX_DISABLE
-				STM32_FMC_MEMORY_TYPE_SRAM
-				STM32_FMC_NORSRAM_MEM_BUS_WIDTH_16
-				STM32_FMC_BURST_ACCESS_MODE_DISABLE
-				STM32_FMC_WAIT_SIGNAL_POLARITY_LOW
-				STM32_FMC_WAIT_TIMING_BEFORE_WS
-				STM32_FMC_WRITE_OPERATION_ENABLE
-				STM32_FMC_WAIT_SIGNAL_DISABLE
-				STM32_FMC_EXTENDED_MODE_DISABLE
-				STM32_FMC_ASYNCHRONOUS_WAIT_DISABLE
-				STM32_FMC_WRITE_BURST_DISABLE
-				STM32_FMC_CONTINUOUS_CLOCK_SYNC_ONLY
-				STM32_FMC_WRITE_FIFO_DISABLE
-				STM32_FMC_PAGE_SIZE_NONE>;
+				      STM32_FMC_MEMORY_TYPE_SRAM
+				      STM32_FMC_NORSRAM_MEM_BUS_WIDTH_16
+				      STM32_FMC_BURST_ACCESS_MODE_DISABLE
+				      STM32_FMC_WAIT_SIGNAL_POLARITY_LOW
+				      STM32_FMC_WAIT_TIMING_BEFORE_WS
+				      STM32_FMC_WRITE_OPERATION_ENABLE
+				      STM32_FMC_WAIT_SIGNAL_DISABLE
+				      STM32_FMC_EXTENDED_MODE_DISABLE
+				      STM32_FMC_ASYNCHRONOUS_WAIT_DISABLE
+				      STM32_FMC_WRITE_BURST_DISABLE
+				      STM32_FMC_CONTINUOUS_CLOCK_SYNC_ONLY
+				      STM32_FMC_WRITE_FIFO_DISABLE
+				      STM32_FMC_PAGE_SIZE_NONE>;
 			st,timing = <1 1 32 0 2 2 STM32_FMC_ACCESS_MODE_A>;
 
 			fmc-mipi-dbi {