diff --git a/boards/arduino/portenta_c33/arduino_portenta_c33.dts b/boards/arduino/portenta_c33/arduino_portenta_c33.dts index ac8c348fddf1f..b4f535267e656 100644 --- a/boards/arduino/portenta_c33/arduino_portenta_c33.dts +++ b/boards/arduino/portenta_c33/arduino_portenta_c33.dts @@ -95,15 +95,39 @@ }; }; -&option_setting_s { +&option_setting_ofs0 { status = "disabled"; }; -&option_setting_sas { +&option_setting_dualsel { status = "disabled"; }; -&option_setting_ofs { +&option_setting_ofs1_sec { + status = "disabled"; +}; + +&option_setting_banksel_sec { + status = "disabled"; +}; + +&option_setting_bps_sec { + status = "disabled"; +}; + +&option_setting_pbps_sec { + status = "disabled"; +}; + +&option_setting_ofs1_sel { + status = "disabled"; +}; + +&option_setting_banksel_sel { + status = "disabled"; +}; + +&option_setting_bps_sel { status = "disabled"; }; diff --git a/drivers/can/can_renesas_ra.c b/drivers/can/can_renesas_ra.c index 3195e201c292e..c85a744e36198 100644 --- a/drivers/can/can_renesas_ra.c +++ b/drivers/can/can_renesas_ra.c @@ -1149,7 +1149,7 @@ DT_FOREACH_STATUS_OKAY(renesas_ra_canfd_global, CAN_RENESAS_RA_GLOBAL_DEFINE) .tx_irq = DT_INST_IRQ_BY_NAME(index, tx, irq), \ .p_extend = &can_renesas_ra_data##index.fsp_canfd_extend, \ .p_bit_timing = &can_renesas_ra_data##index.bit_timing, \ - .p_context = DEVICE_DT_INST_GET(index), \ + .p_context = (void *)DEVICE_DT_INST_GET(index), \ .p_callback = can_renesas_ra_fsp_cb, \ }, \ .fsp_canfd_extend = \ diff --git a/drivers/comparator/comparator_renesas_ra.c b/drivers/comparator/comparator_renesas_ra.c index 6b0cb98249b6b..c040b645fb546 100644 --- a/drivers/comparator/comparator_renesas_ra.c +++ b/drivers/comparator/comparator_renesas_ra.c @@ -164,7 +164,7 @@ static int acmphs_renesas_ra_init(const struct device *dev) return ret; } - data->fsp_config.p_context = dev; + data->fsp_config.p_context = (void *)dev; fsp_err = R_ACMPHS_Open(&data->acmphs, &data->fsp_config); if (FSP_SUCCESS != fsp_err) { diff --git a/drivers/display/display_renesas_ra.c b/drivers/display/display_renesas_ra.c index 9d53aa55e8351..f7a0a61936f18 100644 --- a/drivers/display/display_renesas_ra.c +++ b/drivers/display/display_renesas_ra.c @@ -491,7 +491,7 @@ static int display_init(const struct device *dev) .contrast = {.enable = false}, \ .dithering_on = false}, \ .p_callback = renesas_ra_callback_adapter, \ - .p_context = DEVICE_DT_INST_GET(id), \ + .p_context = (void *)DEVICE_DT_INST_GET(id), \ .p_extend = (void *)(&display_extend_cfg##id), \ .line_detect_irq = DT_INST_IRQ_BY_NAME(id, line, irq), \ .line_detect_ipl = DT_INST_IRQ_BY_NAME(id, line, priority), \ diff --git a/drivers/ethernet/eth_renesas_ra.c b/drivers/ethernet/eth_renesas_ra.c index 84dcad293e9fb..161deb5f1529e 100644 --- a/drivers/ethernet/eth_renesas_ra.c +++ b/drivers/ethernet/eth_renesas_ra.c @@ -27,13 +27,15 @@ LOG_MODULE_REGISTER(LOG_MODULE_NAME); #include "r_ether_phy.h" /* Additional configurations to use with hal_renesas */ -#define ETHER_DEFAULT NULL -#define ETHER_CHANNEL0 0 -#define ETHER_BUF_SIZE 1536 -#define ETHER_PADDING_OFFSET 1 -#define ETHER_BROADCAST_FILTER 0 -#define ETHER_TOTAL_BUF_NUM (CONFIG_ETH_RENESAS_TX_BUF_NUM + CONFIG_ETH_RENESAS_RX_BUF_NUM) -#define ETHER_EE_RECEIVE_EVENT_MASK (0x01070000) +#define ETHER_DEFAULT NULL +#define ETHER_CHANNEL0 0 +#define ETHER_BUF_SIZE 1536 +#define ETHER_PADDING_OFFSET 1 +#define ETHER_BROADCAST_FILTER 0 +#define ETHER_TOTAL_BUF_NUM (CONFIG_ETH_RENESAS_TX_BUF_NUM + CONFIG_ETH_RENESAS_RX_BUF_NUM) +#define ETHER_EE_RECEIVE_EVENT_MASK \ + (ETHER_EESR_EVENT_MASK_RFOF | ETHER_EESR_EVENT_MASK_RDE | ETHER_EESR_EVENT_MASK_FR | \ + ETHER_EESR_EVENT_MASK_RFCOF) BUILD_ASSERT(DT_INST_ENUM_IDX(0, phy_connection_type) <= 1, "Invalid PHY connection setting"); @@ -79,8 +81,7 @@ LISTIFY(CONFIG_ETH_RENESAS_TX_BUF_NUM, DECLARE_ETHER_TX_BUFFER, (;)); uint8_t *pp_g_ether0_ether_buffers[ETHER_TOTAL_BUF_NUM] = { LISTIFY(CONFIG_ETH_RENESAS_RX_BUF_NUM, DECLARE_ETHER_RX_BUFFER_PTR, (,)), - LISTIFY(CONFIG_ETH_RENESAS_TX_BUF_NUM, DECLARE_ETHER_TX_BUFFER_PTR, (,)) -}; + LISTIFY(CONFIG_ETH_RENESAS_TX_BUF_NUM, DECLARE_ETHER_TX_BUFFER_PTR, (,)) }; static __aligned(16) ether_instance_descriptor_t g_ether0_tx_descriptors[CONFIG_ETH_RENESAS_TX_BUF_NUM]; @@ -90,6 +91,7 @@ static __aligned(16) ether_instance_descriptor_t const ether_extended_cfg_t g_ether0_extended_cfg_t = { .p_rx_descriptors = g_ether0_rx_descriptors, .p_tx_descriptors = g_ether0_tx_descriptors, + .eesr_event_filter = ETHER_EE_RECEIVE_EVENT_MASK, }; /* Dummy configuration for ether phy as hal layer require */ @@ -142,7 +144,7 @@ void renesas_ra_eth_callback(ether_callback_args_t *p_args) struct device *dev = (struct device *)p_args->p_context; struct renesas_ra_eth_context *ctx = dev->data; - if (p_args->status_eesr & ETHER_EE_RECEIVE_EVENT_MASK) { + if (p_args->event == ETHER_EVENT_RX_COMPLETE) { k_sem_give(&ctx->rx_sem); } } @@ -251,7 +253,7 @@ static void renesas_ra_eth_initialize(struct net_if *iface) LOG_ERR("Failed to init ether - R_ETHER_Open fail"); } - err = R_ETHER_CallbackSet(&ctx->ctrl, renesas_ra_eth_callback, dev, NULL); + err = R_ETHER_CallbackSet(&ctx->ctrl, renesas_ra_eth_callback, (void *const)dev, NULL); if (err != FSP_SUCCESS) { LOG_ERR("Failed to init ether - R_ETHER_CallbackSet fail"); diff --git a/drivers/flash/flash_renesas_ra_ospi_b.c b/drivers/flash/flash_renesas_ra_ospi_b.c index 89ad48c28fc4e..7dbb77696d5e8 100644 --- a/drivers/flash/flash_renesas_ra_ospi_b.c +++ b/drivers/flash/flash_renesas_ra_ospi_b.c @@ -162,7 +162,7 @@ static int flash_renesas_ra_ospi_b_spi_mode_init(ospi_b_instance_ctrl_t *p_ctrl, } /* DDR sampling window extend */ - R_XSPI->LIOCFGCS_b[p_ctrl->channel].DDRSMPEX = 1; + R_XSPI0->LIOCFGCS_b[p_ctrl->channel].DDRSMPEX = 1; /* Switch OSPI module to 1S-1S-1S mode to configure flash device */ err = R_OSPI_B_SpiProtocolSet(p_ctrl, SPI_FLASH_PROTOCOL_EXTENDED_SPI); @@ -172,9 +172,9 @@ static int flash_renesas_ra_ospi_b_spi_mode_init(ospi_b_instance_ctrl_t *p_ctrl, } /* Reset flash device by driving OM_RESET pin */ - R_XSPI->LIOCTL_b.RSTCS0 = 0; + R_XSPI0->LIOCTL_b.RSTCS0 = 0; k_sleep(K_USEC(500)); - R_XSPI->LIOCTL_b.RSTCS0 = 1; + R_XSPI0->LIOCTL_b.RSTCS0 = 1; k_sleep(K_NSEC(50)); /* Transfer write enable command */ diff --git a/drivers/i2c/i2c_renesas_ra_iic.c b/drivers/i2c/i2c_renesas_ra_iic.c index a58fd3323b438..3b006a2644a6a 100644 --- a/drivers/i2c/i2c_renesas_ra_iic.c +++ b/drivers/i2c/i2c_renesas_ra_iic.c @@ -540,7 +540,7 @@ static DEVICE_API(i2c, i2c_ra_iic_driver_api) = { .tei_irq = DT_INST_IRQ_BY_NAME(index, tei, irq), \ .eri_irq = DT_INST_IRQ_BY_NAME(index, eri, irq), \ .p_callback = i2c_ra_iic_callback, \ - .p_context = DEVICE_DT_GET(DT_DRV_INST(index)), \ + .p_context = (void *)DEVICE_DT_GET(DT_DRV_INST(index)), \ }, \ }; \ \ diff --git a/drivers/i2c/i2c_renesas_ra_sci_b.c b/drivers/i2c/i2c_renesas_ra_sci_b.c index 7318f27359006..472f64e329245 100644 --- a/drivers/i2c/i2c_renesas_ra_sci_b.c +++ b/drivers/i2c/i2c_renesas_ra_sci_b.c @@ -710,7 +710,7 @@ static const struct i2c_driver_api renesas_ra_sci_b_i2c_driver_api = { .txi_irq = DT_IRQ_BY_NAME(DT_INST_PARENT(index), txi, irq), \ .tei_irq = DT_IRQ_BY_NAME(DT_INST_PARENT(index), tei, irq), \ .p_callback = renesas_ra_sci_b_i2c_callback, \ - .p_context = DEVICE_DT_GET(DT_DRV_INST(index)), \ + .p_context = (void *)DEVICE_DT_GET(DT_DRV_INST(index)), \ }, \ .ext_cfg = \ { \ diff --git a/drivers/i2s/i2s_renesas_ra_ssie.c b/drivers/i2s/i2s_renesas_ra_ssie.c index d06edda8c9fc9..47f6134f889c5 100644 --- a/drivers/i2s/i2s_renesas_ra_ssie.c +++ b/drivers/i2s/i2s_renesas_ra_ssie.c @@ -1155,7 +1155,7 @@ static DEVICE_API(i2s, i2s_renesas_ra_drv_api) = { .word_length = I2S_WORD_LENGTH_16_BITS, \ .ws_continue = I2S_WS_CONTINUE_OFF, \ .p_callback = renesas_ra_ssie_callback, \ - .p_context = DEVICE_DT_INST_GET(index), \ + .p_context = (void *)DEVICE_DT_INST_GET(index), \ .p_extend = &ssi_extended_cfg_t_##index, \ .txi_irq = RA_SSIE_TX_IRQ_BY_NAME(index, irq), \ .rxi_irq = RA_SSIE_RX_IRQ_BY_NAME(index, irq), \ diff --git a/drivers/i3c/i3c_renesas_ra.c b/drivers/i3c/i3c_renesas_ra.c index 8a74c76065bb4..fb497143a786d 100644 --- a/drivers/i3c/i3c_renesas_ra.c +++ b/drivers/i3c/i3c_renesas_ra.c @@ -1187,7 +1187,7 @@ static DEVICE_API(i3c, i3c_renesas_ra_api) = { static i3c_cfg_t i3c##index##_cfg = { \ .channel = DT_INST_PROP(index, channel), \ .p_callback = &i3c_renesas_ra_hal_callback, \ - .p_context = DEVICE_DT_INST_GET(index), \ + .p_context = (void *)DEVICE_DT_INST_GET(index), \ .p_extend = &i3c##index##_cfg_extend, \ }; \ static i3c_device_cfg_t i3c##index##_master_cfg = {0}; \ diff --git a/drivers/mdio/mdio_renesas_ra.c b/drivers/mdio/mdio_renesas_ra.c index e32443a29ea88..063d90f65c076 100644 --- a/drivers/mdio/mdio_renesas_ra.c +++ b/drivers/mdio/mdio_renesas_ra.c @@ -35,10 +35,12 @@ static int renesas_ra_mdio_read(const struct device *dev, uint8_t prtad, uint8_t uint16_t *data) { struct renesas_ra_mdio_data *dev_data = dev->data; + ether_phy_extended_cfg_t *ext_cfg = + (ether_phy_extended_cfg_t *)dev_data->ether_phy_cfg.p_extend; uint32_t read; fsp_err_t err; - dev_data->ether_phy_ctrl.phy_lsi_address = prtad; + ext_cfg->p_phy_lsi_cfg_list[0]->address = prtad; k_mutex_lock(&dev_data->rw_mutex, K_FOREVER); @@ -59,9 +61,11 @@ static int renesas_ra_mdio_write(const struct device *dev, uint8_t prtad, uint8_ uint16_t data) { struct renesas_ra_mdio_data *dev_data = dev->data; + ether_phy_extended_cfg_t *ext_cfg = + (ether_phy_extended_cfg_t *)dev_data->ether_phy_cfg.p_extend; fsp_err_t err; - dev_data->ether_phy_ctrl.phy_lsi_address = prtad; + ext_cfg->p_phy_lsi_cfg_list[0]->address = prtad; k_mutex_lock(&dev_data->rw_mutex, K_FOREVER); @@ -106,13 +110,22 @@ static DEVICE_API(mdio, renesas_ra_mdio_api) = { #define RENSAS_RA_MDIO_INSTANCE_DEFINE(node) \ PINCTRL_DT_INST_DEFINE(node); \ + static ether_phy_lsi_cfg_t renesas_ra_mdio##node##_lsi_cfg_list = { \ + .type = ETHER_PHY_LSI_TYPE_CUSTOM, \ + }; \ + static ether_phy_extended_cfg_t renesas_ra_mdio##node##_extend = { \ + .p_phy_lsi_cfg_list = \ + { \ + &renesas_ra_mdio##node##_lsi_cfg_list, \ + }, \ + }; \ static struct renesas_ra_mdio_data renesas_ra_mdio##node##_data = { \ .ether_phy_cfg = { \ .channel = 0, \ .phy_reset_wait_time = 0x00020000, \ .mii_bit_access_wait_time = 8, \ - .phy_lsi_type = ETHER_PHY_LSI_TYPE_CUSTOM, \ .flow_control = ETHER_PHY_FLOW_CONTROL_DISABLE, \ + .p_extend = &renesas_ra_mdio##node##_extend, \ }}; \ static const struct renesas_ra_mdio_config renesas_ra_mdio##node##_cfg = { \ .pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(node)}; \ diff --git a/drivers/mipi_dsi/dsi_renesas_ra.c b/drivers/mipi_dsi/dsi_renesas_ra.c index 8087284b8f233..dbf0744a1ecc4 100644 --- a/drivers/mipi_dsi/dsi_renesas_ra.c +++ b/drivers/mipi_dsi/dsi_renesas_ra.c @@ -227,8 +227,18 @@ static int mipi_dsi_renesas_ra_init(const struct device *dev) #define RENESAS_RA_MIPI_PHYS_SETTING_DEFINE(n) \ static const mipi_phy_timing_t mipi_phy_##n##_timing = { \ .t_init = CLAMP(DT_PROP(DT_INST_CHILD(n, phys_timing), t_init), 0, 0x7FFF), \ - .t_clk_prep = CLAMP(DT_PROP(DT_INST_CHILD(n, phys_timing), t_clk_prep), 0, 0xFF), \ - .t_hs_prep = CLAMP(DT_PROP(DT_INST_CHILD(n, phys_timing), t_hs_prep), 0, 0xFF), \ + .dphytim2_b = \ + { \ + .t_clk_prep = \ + CLAMP(DT_PROP(DT_INST_CHILD(n, phys_timing), t_clk_prep), \ + 0, 0xFF), \ + }, \ + .dphytim3_b = \ + { \ + .t_hs_prep = \ + CLAMP(DT_PROP(DT_INST_CHILD(n, phys_timing), t_hs_prep), \ + 0, 0xFF), \ + }, \ .t_lp_exit = CLAMP(DT_PROP(DT_INST_CHILD(n, phys_timing), t_lp_exit), 0, 0xFF), \ .dphytim4_b = \ { \ @@ -261,6 +271,7 @@ static int mipi_dsi_renesas_ra_init(const struct device *dev) }, \ .lp_divisor = CLAMP(DT_INST_PROP(n, lp_divisor), 1, 32) - 1, \ .p_timing = &mipi_phy_##n##_timing, \ + .dsi_mode = true, /* enable DSI mode, disable CSI mode */ \ }; \ \ mipi_phy_ctrl_t mipi_phy_##n##_ctrl; \ @@ -309,31 +320,31 @@ static int mipi_dsi_renesas_ra_init(const struct device *dev) .dsi_ferr.irq = DT_INST_IRQ_BY_NAME(id, ferr, irq), \ .dsi_ppi.ipl = DT_INST_IRQ_BY_NAME(id, ppi, priority), \ .dsi_ppi.irq = DT_INST_IRQ_BY_NAME(id, ppi, irq), \ - .dsi_rxie = R_DSILINK_RXIER_BTAREND_Msk | R_DSILINK_RXIER_LRXHTO_Msk | \ - R_DSILINK_RXIER_TATO_Msk | R_DSILINK_RXIER_RXRESP_Msk | \ - R_DSILINK_RXIER_RXEOTP_Msk | R_DSILINK_RXIER_RXTE_Msk | \ - R_DSILINK_RXIER_RXACK_Msk | R_DSILINK_RXIER_EXTEDET_Msk | \ - R_DSILINK_RXIER_MLFERR_Msk | R_DSILINK_RXIER_ECCERRM_Msk | \ - R_DSILINK_RXIER_UNEXERR_Msk | R_DSILINK_RXIER_WCERR_Msk | \ - R_DSILINK_RXIER_CRCERR_Msk | R_DSILINK_RXIER_IBERR_Msk | \ - R_DSILINK_RXIER_RXOVFERR_Msk | R_DSILINK_RXIER_PRTOERR_Msk | \ - R_DSILINK_RXIER_NORESERR_Msk | R_DSILINK_RXIER_RSIZEERR_Msk | \ - R_DSILINK_RXIER_ECCERRS_Msk | R_DSILINK_RXIER_RXAKE_Msk, \ - .dsi_ferrie = R_DSILINK_FERRIER_HTXTO_Msk | R_DSILINK_FERRIER_LRXHTO_Msk | \ - R_DSILINK_FERRIER_TATO_Msk | R_DSILINK_FERRIER_ESCENT_Msk | \ - R_DSILINK_FERRIER_SYNCESC_Msk | R_DSILINK_FERRIER_CTRL_Msk | \ - R_DSILINK_FERRIER_CLP0_Msk | R_DSILINK_FERRIER_CLP1_Msk, \ - .dsi_plie = R_DSILINK_PLIER_DLULPENT_Msk | R_DSILINK_PLIER_DLULPEXT_Msk, \ - .dsi_vmie = R_DSILINK_VMIER_VBUFUDF_Msk | R_DSILINK_VMIER_VBUFOVF_Msk, \ - .dsi_sqch0ie = R_DSILINK_SQCH0IER_AACTFIN_Msk | R_DSILINK_SQCH0IER_ADESFIN_Msk | \ - R_DSILINK_SQCH0IER_TXIBERR_Msk | R_DSILINK_SQCH0IER_RXFERR_Msk | \ - R_DSILINK_SQCH0IER_RXFAIL_Msk | R_DSILINK_SQCH0IER_RXPFAIL_Msk | \ - R_DSILINK_SQCH0IER_RXCORERR_Msk | R_DSILINK_SQCH0IER_RXAKE_Msk, \ - .dsi_sqch1ie = R_DSILINK_SQCH1IER_AACTFIN_Msk | R_DSILINK_SQCH1IER_ADESFIN_Msk | \ - R_DSILINK_SQCH1IER_SIZEERR_Msk | R_DSILINK_SQCH1IER_TXIBERR_Msk | \ - R_DSILINK_SQCH1IER_RXFERR_Msk | R_DSILINK_SQCH1IER_RXFAIL_Msk | \ - R_DSILINK_SQCH1IER_RXPFAIL_Msk | R_DSILINK_SQCH1IER_RXCORERR_Msk | \ - R_DSILINK_SQCH1IER_RXAKE_Msk, \ + .dsi_rxie = R_MIPI_DSI_RXIER_BTAREND_Msk | R_MIPI_DSI_RXIER_LRXHTO_Msk | \ + R_MIPI_DSI_RXIER_TATO_Msk | R_MIPI_DSI_RXIER_RXRESP_Msk | \ + R_MIPI_DSI_RXIER_RXEOTP_Msk | R_MIPI_DSI_RXIER_RXTE_Msk | \ + R_MIPI_DSI_RXIER_RXACK_Msk | R_MIPI_DSI_RXIER_EXTEDET_Msk | \ + R_MIPI_DSI_RXIER_MLFERR_Msk | R_MIPI_DSI_RXIER_ECCERRM_Msk | \ + R_MIPI_DSI_RXIER_UNEXERR_Msk | R_MIPI_DSI_RXIER_WCERR_Msk | \ + R_MIPI_DSI_RXIER_CRCERR_Msk | R_MIPI_DSI_RXIER_IBERR_Msk | \ + R_MIPI_DSI_RXIER_RXOVFERR_Msk | R_MIPI_DSI_RXIER_PRTOERR_Msk | \ + R_MIPI_DSI_RXIER_NORESERR_Msk | R_MIPI_DSI_RXIER_RSIZEERR_Msk | \ + R_MIPI_DSI_RXIER_ECCERRS_Msk | R_MIPI_DSI_RXIER_RXAKE_Msk, \ + .dsi_ferrie = R_MIPI_DSI_FERRIER_HTXTO_Msk | R_MIPI_DSI_FERRIER_LRXHTO_Msk | \ + R_MIPI_DSI_FERRIER_TATO_Msk | R_MIPI_DSI_FERRIER_ESCENT_Msk | \ + R_MIPI_DSI_FERRIER_SYNCESC_Msk | R_MIPI_DSI_FERRIER_CTRL_Msk | \ + R_MIPI_DSI_FERRIER_CLP0_Msk | R_MIPI_DSI_FERRIER_CLP1_Msk, \ + .dsi_plie = R_MIPI_DSI_PLIER_DLULPENT_Msk | R_MIPI_DSI_PLIER_DLULPEXT_Msk, \ + .dsi_vmie = R_MIPI_DSI_VMIER_VBUFUDF_Msk | R_MIPI_DSI_VMIER_VBUFOVF_Msk, \ + .dsi_sqch0ie = R_MIPI_DSI_SQCH0IER_AACTFIN_Msk | R_MIPI_DSI_SQCH0IER_ADESFIN_Msk | \ + R_MIPI_DSI_SQCH0IER_TXIBERR_Msk | R_MIPI_DSI_SQCH0IER_RXFERR_Msk | \ + R_MIPI_DSI_SQCH0IER_RXFAIL_Msk | R_MIPI_DSI_SQCH0IER_RXPFAIL_Msk | \ + R_MIPI_DSI_SQCH0IER_RXCORERR_Msk | R_MIPI_DSI_SQCH0IER_RXAKE_Msk, \ + .dsi_sqch1ie = R_MIPI_DSI_SQCH1IER_AACTFIN_Msk | R_MIPI_DSI_SQCH1IER_ADESFIN_Msk | \ + R_MIPI_DSI_SQCH1IER_SIZEERR_Msk | R_MIPI_DSI_SQCH1IER_TXIBERR_Msk | \ + R_MIPI_DSI_SQCH1IER_RXFERR_Msk | R_MIPI_DSI_SQCH1IER_RXFAIL_Msk | \ + R_MIPI_DSI_SQCH1IER_RXPFAIL_Msk | \ + R_MIPI_DSI_SQCH1IER_RXCORERR_Msk | R_MIPI_DSI_SQCH1IER_RXAKE_Msk, \ }; \ \ static const struct mipi_dsi_renesas_ra_config ra_config_##id = { \ @@ -355,9 +366,9 @@ static int mipi_dsi_renesas_ra_init(const struct device *dev) .vertical_sync_polarity = 1, \ .horizontal_sync_polarity = 1, \ .video_mode_delay = DT_INST_PROP(id, video_mode_delay), \ - .hsa_no_lp = R_DSILINK_VMSET0R_HSANOLP_Msk, \ - .hbp_no_lp = R_DSILINK_VMSET0R_HBPNOLP_Msk, \ - .hfp_no_lp = R_DSILINK_VMSET0R_HFPNOLP_Msk, \ + .hsa_no_lp = R_MIPI_DSI_VMSET0R_HSANOLP_Msk, \ + .hbp_no_lp = R_MIPI_DSI_VMSET0R_HBPNOLP_Msk, \ + .hfp_no_lp = R_MIPI_DSI_VMSET0R_HFPNOLP_Msk, \ .ulps_wakeup_period = DT_INST_PROP(id, ulps_wakeup_period), \ .continuous_clock = (1), \ .hs_tx_timeout = 0, \ @@ -374,7 +385,7 @@ static int mipi_dsi_renesas_ra_init(const struct device *dev) .eotp_enable = (1), \ .p_extend = &mipi_dsi_##id##_extended_cfg, \ .p_callback = mipi_dsi_callback, \ - .p_context = DEVICE_DT_INST_GET(id), \ + .p_context = (void *)DEVICE_DT_INST_GET(id), \ }, \ }; \ \ diff --git a/drivers/pwm/pwm_renesas_ra.c b/drivers/pwm/pwm_renesas_ra.c index 54eb817cef05a..e7f447e6a6a75 100644 --- a/drivers/pwm/pwm_renesas_ra.c +++ b/drivers/pwm/pwm_renesas_ra.c @@ -493,7 +493,7 @@ static int pwm_renesas_ra_init(const struct device *dev) #if defined(CONFIG_PWM_CAPTURE) data->fsp_cfg.p_callback = fsp_callback; - data->fsp_cfg.p_context = dev; + data->fsp_cfg.p_context = (void *)dev; #endif /* defined(CONFIG_PWM_CAPTURE) */ #ifdef CONFIG_RENESAS_RA_ELC diff --git a/drivers/serial/uart_renesas_ra8_sci_b.c b/drivers/serial/uart_renesas_ra8_sci_b.c index 36d99b029dc83..9f6e5cdcfedee 100644 --- a/drivers/serial/uart_renesas_ra8_sci_b.c +++ b/drivers/serial/uart_renesas_ra8_sci_b.c @@ -1042,7 +1042,7 @@ static int uart_ra_sci_b_init(const struct device *dev) #if defined(CONFIG_UART_ASYNC_API) data->fsp_config.p_callback = uart_ra_sci_b_callback_adapter; - data->fsp_config.p_context = dev; + data->fsp_config.p_context = (void *)dev; k_work_init_delayable(&data->tx_timeout_work, uart_ra_sci_b_async_tx_timeout); k_work_init_delayable(&data->rx_timeout_work, uart_ra_sci_b_async_rx_timeout); diff --git a/drivers/serial/uart_renesas_ra_sci.c b/drivers/serial/uart_renesas_ra_sci.c index c0011129386dd..030e40e33576d 100644 --- a/drivers/serial/uart_renesas_ra_sci.c +++ b/drivers/serial/uart_renesas_ra_sci.c @@ -960,7 +960,7 @@ static int uart_ra_sci_init(const struct device *dev) data->fsp_config_extend.p_baud_setting = &data->fsp_baud_setting; #if defined(CONFIG_UART_ASYNC_API) data->fsp_config.p_callback = uart_ra_sci_callback_adapter; - data->fsp_config.p_context = dev; + data->fsp_config.p_context = (void *)dev; k_work_init_delayable(&data->tx_timeout, uart_ra_sci_tx_timeout_handler); k_work_init_delayable(&data->rx_timeout_work, uart_ra_sci_rx_timeout_handler); #endif /* defined(CONFIG_UART_ASYNC_API) */ diff --git a/drivers/spi/spi_b_renesas_ra8.c b/drivers/spi/spi_b_renesas_ra8.c index 7e0c91e4742a5..9f0fe9a842af6 100644 --- a/drivers/spi/spi_b_renesas_ra8.c +++ b/drivers/spi/spi_b_renesas_ra8.c @@ -148,7 +148,7 @@ static int ra_spi_b_configure(const struct device *dev, const struct spi_config data->fsp_config.p_extend = &data->fsp_config_extend; data->fsp_config.p_callback = spi_cb; - data->fsp_config.p_context = dev; + data->fsp_config.p_context = (void *)dev; fsp_err = R_SPI_B_Open(&data->spi, &data->fsp_config); if (fsp_err != FSP_SUCCESS) { LOG_ERR("R_SPI_B_Open error: %d", fsp_err); diff --git a/drivers/spi/spi_renesas_ra.c b/drivers/spi/spi_renesas_ra.c index 56d95b6e2a703..182bebd1ee0c1 100644 --- a/drivers/spi/spi_renesas_ra.c +++ b/drivers/spi/spi_renesas_ra.c @@ -159,7 +159,7 @@ static int ra_spi_configure(const struct device *dev, const struct spi_config *c data->fsp_config.p_extend = &data->fsp_config_extend; data->fsp_config.p_callback = spi_cb; - data->fsp_config.p_context = dev; + data->fsp_config.p_context = (void *)dev; fsp_err = R_SPI_Open(&data->spi, &data->fsp_config); if (fsp_err != FSP_SUCCESS) { LOG_ERR("R_SPI_Open error: %d", fsp_err); diff --git a/drivers/usb/udc/udc_renesas_ra.c b/drivers/usb/udc/udc_renesas_ra.c index 4a3123ec2b9c8..11d3f02226e51 100644 --- a/drivers/usb/udc/udc_renesas_ra.c +++ b/drivers/usb/udc/udc_renesas_ra.c @@ -813,7 +813,7 @@ static const struct udc_api udc_renesas_ra_api = { .ipl = USB_RENESAS_RA_IRQ_GET(DT_INST_PARENT(n), usbfs_i, priority), \ .ipl_r = USB_RENESAS_RA_IRQ_GET(DT_INST_PARENT(n), usbfs_r, priority), \ .hsipl = USB_RENESAS_RA_IRQ_GET(DT_INST_PARENT(n), usbhs_ir, priority), \ - .p_context = DEVICE_DT_INST_GET(n), \ + .p_context = (void *)DEVICE_DT_INST_GET(n), \ .p_callback = udc_renesas_ra_event_handler, \ }, \ }; \ diff --git a/drivers/watchdog/wdt_renesas_ra.c b/drivers/watchdog/wdt_renesas_ra.c index 78790b9ccc0d7..9cfff0dbf91e4 100644 --- a/drivers/watchdog/wdt_renesas_ra.c +++ b/drivers/watchdog/wdt_renesas_ra.c @@ -323,7 +323,7 @@ static DEVICE_API(wdt, wdt_renesas_ra_api) = { .wdt_cfg = {.stop_control = WDT_STOP_CONTROL_DISABLE, \ .reset_control = WDT_RESET_CONTROL_RESET, \ .p_callback = wdt_renesas_ra_callback_adapter, \ - .p_context = DEVICE_DT_GET(id)}, \ + .p_context = (void *)DEVICE_DT_GET(id)}, \ }; \ \ DEVICE_DT_DEFINE(id, NULL, NULL, &wdt_renesas_ra_data##id, &wdt_renesas_ra_cfg##id, \ diff --git a/dts/arm/renesas/ra/ra2/ra2l1.dtsi b/dts/arm/renesas/ra/ra2/ra2l1.dtsi index 23bb39e78524b..657822f9b4e46 100644 --- a/dts/arm/renesas/ra/ra2/ra2l1.dtsi +++ b/dts/arm/renesas/ra/ra2/ra2l1.dtsi @@ -240,13 +240,6 @@ }; }; - id_code: id_code@1010018 { - compatible = "zephyr,memory-region"; - reg = <0x01010018 0x20>; - zephyr,memory-region = "ID_CODE"; - status = "okay"; - }; - wdt: wdt@40044200 { compatible = "renesas,ra-wdt"; reg = <0x40044200 0x200>; @@ -515,6 +508,45 @@ #port-irq-cells = <0>; status = "disabled"; }; + + option_setting_ofs_in_rom: option-setting-ofs-in-rom@400 { + reg = <0x00000400 0x3c>; + #address-cells = <1>; + #size-cells = <0>; + + option_setting_ofs0: option-setting-ofs0@400 { + compatible = "renesas,ofs-memory"; + reg = <0x00000400 0x4>; + status = "okay"; + }; + + option_setting_ofs1: option-setting-ofs1@404 { + compatible = "renesas,ofs-memory"; + reg = <0x00000404 0x4>; + status = "okay"; + }; + + option_setting_secmpu: option-setting-secmpu@408 { + compatible = "renesas,ofs-memory"; + reg = <0x00000408 0x34>; + status = "okay"; + }; + }; + + option_setting_ofs_conf: option-setting-ofs-conf@1010010 { + compatible = "zephyr,memory-region"; + reg = <0x01010010 0x24>; + zephyr,memory-region = "OFS_CONF_MEMORY"; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + option_setting_osis: option-setting-osis@1010018 { + compatible = "renesas,ofs-memory"; + reg = <0x01010018 0x1c>; + status = "okay"; + }; + }; }; clocks: clocks { diff --git a/dts/arm/renesas/ra/ra2/ra2xx.dtsi b/dts/arm/renesas/ra/ra2/ra2xx.dtsi index 2924b028e198f..c23452e69d6c6 100644 --- a/dts/arm/renesas/ra/ra2/ra2xx.dtsi +++ b/dts/arm/renesas/ra/ra2/ra2xx.dtsi @@ -285,13 +285,6 @@ }; }; - id_code: id_code@1010018 { - compatible = "zephyr,memory-region"; - reg = <0x01010018 0x20>; - zephyr,memory-region = "ID_CODE"; - status = "okay"; - }; - port_irq0: external-interrupt@40006000 { compatible = "renesas,ra-external-interrupt"; reg = <0x40006000 0x1>; @@ -387,6 +380,45 @@ status = "disabled"; }; }; + + option_setting_ofs_in_rom: option-setting-ofs-in-rom@400 { + reg = <0x00000400 0x3c>; + #address-cells = <1>; + #size-cells = <0>; + + option_setting_ofs0: option-setting-ofs0@400 { + compatible = "renesas,ofs-memory"; + reg = <0x00000400 0x4>; + status = "okay"; + }; + + option_setting_ofs1: option-setting-ofs1@404 { + compatible = "renesas,ofs-memory"; + reg = <0x00000404 0x4>; + status = "okay"; + }; + + option_setting_secmpu: option-setting-secmpu@408 { + compatible = "renesas,ofs-memory"; + reg = <0x00000408 0x34>; + status = "okay"; + }; + }; + + option_setting_ofs_conf: option-setting-ofs-conf@1010008 { + compatible = "zephyr,memory-region"; + reg = <0x01010008 0x2c>; + zephyr,memory-region = "OFS_CONF_MEMORY"; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + option_setting_osis: option-setting-osis@1010018 { + compatible = "renesas,ofs-memory"; + reg = <0x01010018 0x1c>; + status = "okay"; + }; + }; }; }; diff --git a/dts/arm/renesas/ra/ra4/r7fa4e10x.dtsi b/dts/arm/renesas/ra/ra4/r7fa4e10x.dtsi index 69052ce6078cd..f3049d859093c 100644 --- a/dts/arm/renesas/ra/ra4/r7fa4e10x.dtsi +++ b/dts/arm/renesas/ra/ra4/r7fa4e10x.dtsi @@ -68,6 +68,51 @@ compatible = "renesas,ra-sce9-rng"; status = "disabled"; }; + + option_setting_ofs_conf: option-setting-ofs-conf@100a100 { + compatible = "zephyr,memory-region"; + reg = <0x0100a100 0x200>; + zephyr,memory-region = "OFS_CONF_MEMORY"; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + option_setting_ofs0: option-setting-ofs0@100a100 { + compatible = "renesas,ofs-memory"; + reg = <0x0100a100 0x4>; + status = "okay"; + }; + + option_setting_ofs1_sec: option-setting-ofs1-sec@100a200 { + compatible = "renesas,ofs-memory"; + reg = <0x0100a200 0x4>; + status = "okay"; + }; + + option_setting_bps_sec: option-setting-bps-sec@100a240 { + compatible = "renesas,ofs-memory"; + reg = <0x0100a240 0x4>; + status = "okay"; + }; + + option_setting_pbps_sec: option-setting-pbps-sec@100a260 { + compatible = "renesas,ofs-memory"; + reg = <0x0100a260 0x4>; + status = "okay"; + }; + + option_setting_ofs1_sel: option-setting-ofs1-sel@100a280 { + compatible = "renesas,ofs-memory"; + reg = <0x0100a280 0x4>; + status = "okay"; + }; + + option_setting_bps_sel: option-setting-bps-sel@100a2c0 { + compatible = "renesas,ofs-memory"; + reg = <0x0100a2c0 0x4>; + status = "okay"; + }; + }; }; clocks: clocks { diff --git a/dts/arm/renesas/ra/ra4/r7fa4e2b93cfm.dtsi b/dts/arm/renesas/ra/ra4/r7fa4e2b93cfm.dtsi index 3bd77819bd3a0..3b4d0e4f335b8 100644 --- a/dts/arm/renesas/ra/ra4/r7fa4e2b93cfm.dtsi +++ b/dts/arm/renesas/ra/ra4/r7fa4e2b93cfm.dtsi @@ -66,13 +66,6 @@ channel-available-mask = <0x139f7>; }; - id_code: id_code@100a120 { - compatible = "zephyr,memory-region"; - reg = <0x0100a120 0x10>; - zephyr,memory-region = "ID_CODE"; - status = "okay"; - }; - canfd_global: canfd_global@400b0000 { compatible = "renesas,ra-canfd-global"; interrupts = <40 1>, <41 1>; @@ -128,6 +121,45 @@ status = "disabled"; }; }; + + option_setting_ofs_conf: option-setting-ofs-conf@100a100 { + compatible = "zephyr,memory-region"; + reg = <0x0100a100 0x200>; + zephyr,memory-region = "OFS_CONF_MEMORY"; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + option_setting_ofs0: option-setting-ofs0@100a100 { + compatible = "renesas,ofs-memory"; + reg = <0x0100a100 0x4>; + status = "okay"; + }; + + option_setting_osis: option-setting-osis@100a120 { + compatible = "renesas,ofs-memory"; + reg = <0x0100a120 0x10>; + status = "okay"; + }; + + option_setting_ofs1_sec: option-setting-ofs1-sec@100a200 { + compatible = "renesas,ofs-memory"; + reg = <0x0100a200 0x4>; + status = "okay"; + }; + + option_setting_bps_sec: option-setting-bps-sec@100a240 { + compatible = "renesas,ofs-memory"; + reg = <0x0100a240 0x4>; + status = "okay"; + }; + + option_setting_pbps_sec: option-setting-pbps-sec@100a260 { + compatible = "renesas,ofs-memory"; + reg = <0x0100a260 0x4>; + status = "okay"; + }; + }; }; clocks: clocks { diff --git a/dts/arm/renesas/ra/ra4/r7fa4l1bx.dtsi b/dts/arm/renesas/ra/ra4/r7fa4l1bx.dtsi index 7a94131005e36..8eaeda35f91c8 100644 --- a/dts/arm/renesas/ra/ra4/r7fa4l1bx.dtsi +++ b/dts/arm/renesas/ra/ra4/r7fa4l1bx.dtsi @@ -366,27 +366,6 @@ }; }; - option_setting_ofs: option_setting_ofs@100a100 { - compatible = "zephyr,memory-region"; - reg = <0x0100a100 0x18>; - zephyr,memory-region = "OPTION_SETTING_OFS"; - status = "okay"; - }; - - option_setting_sas: option_setting_sas@100a134 { - compatible = "zephyr,memory-region"; - reg = <0x0100a134 0xcc>; - zephyr,memory-region = "OPTION_SETTING_SAS"; - status = "okay"; - }; - - option_setting_s: option_setting_s@100a200 { - compatible = "zephyr,memory-region"; - reg = <0x0100a200 0x100>; - zephyr,memory-region = "OPTION_SETTING_S"; - status = "okay"; - }; - port_irq0: external-interrupt@40006000 { compatible = "renesas,ra-external-interrupt"; reg = <0x40006000 0x1>; @@ -579,6 +558,69 @@ full-duplex; status = "disabled"; }; + + option_setting_ofs_conf: option-setting-ofs-conf@100a100 { + compatible = "zephyr,memory-region"; + reg = <0x0100a100 0x200>; + zephyr,memory-region = "OFS_CONF_MEMORY"; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + option_setting_ofs0: option-setting-ofs0@100a100 { + compatible = "renesas,ofs-memory"; + reg = <0x0100a100 0x4>; + status = "okay"; + }; + + option_setting_dualsel: option-setting-dualsel@100a110 { + compatible = "renesas,ofs-memory"; + reg = <0x0100a110 0x4>; + status = "okay"; + }; + + option_setting_ofs1_sec: option-setting-ofs1-sec@100a200 { + compatible = "renesas,ofs-memory"; + reg = <0x0100a200 0x4>; + status = "okay"; + }; + + option_setting_banksel_sec: option-setting-banksel-sec@100a210 { + compatible = "renesas,ofs-memory"; + reg = <0x0100a210 0x4>; + status = "okay"; + }; + + option_setting_bps_sec: option-setting-bps-sec@100a240 { + compatible = "renesas,ofs-memory"; + reg = <0x0100a240 0xc>; + status = "okay"; + }; + + option_setting_pbps_sec: option-setting-pbps-sec@100a260 { + compatible = "renesas,ofs-memory"; + reg = <0x0100a260 0xc>; + status = "okay"; + }; + + option_setting_ofs1_sel: option-setting-ofs1-sel@100a280 { + compatible = "renesas,ofs-memory"; + reg = <0x0100a280 0x4>; + status = "okay"; + }; + + option_setting_banksel_sel: option-setting-banksel-sel@100a290 { + compatible = "renesas,ofs-memory"; + reg = <0x0100a290 0x4>; + status = "okay"; + }; + + option_setting_bps_sel: option-setting-bps-sel@100a2c0 { + compatible = "renesas,ofs-memory"; + reg = <0x0100a2c0 0xc>; + status = "okay"; + }; + }; }; clocks: clocks { diff --git a/dts/arm/renesas/ra/ra4/r7fa4m2ax.dtsi b/dts/arm/renesas/ra/ra4/r7fa4m2ax.dtsi index 8a155a1f6e8fc..f1564db9ff445 100644 --- a/dts/arm/renesas/ra/ra4/r7fa4m2ax.dtsi +++ b/dts/arm/renesas/ra/ra4/r7fa4m2ax.dtsi @@ -144,6 +144,51 @@ compatible = "renesas,ra-sce9-rng"; status = "disabled"; }; + + option_setting_ofs_conf: option-setting-ofs-conf@100a100 { + compatible = "zephyr,memory-region"; + reg = <0x0100a100 0x200>; + zephyr,memory-region = "OFS_CONF_MEMORY"; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + option_setting_ofs0: option-setting-ofs0@100a100 { + compatible = "renesas,ofs-memory"; + reg = <0x0100a100 0x4>; + status = "okay"; + }; + + option_setting_ofs1_sec: option-setting-ofs1-sec@100a200 { + compatible = "renesas,ofs-memory"; + reg = <0x0100a200 0x4>; + status = "okay"; + }; + + option_setting_bps_sec: option-setting-bps-sec@100a240 { + compatible = "renesas,ofs-memory"; + reg = <0x0100a240 0x4>; + status = "okay"; + }; + + option_setting_pbps_sec: option-setting-pbps-sec@100a260 { + compatible = "renesas,ofs-memory"; + reg = <0x0100a260 0x4>; + status = "okay"; + }; + + option_setting_ofs1_sel: option-setting-ofs1-sel@100a280 { + compatible = "renesas,ofs-memory"; + reg = <0x0100a280 0x4>; + status = "okay"; + }; + + option_setting_bps_sel: option-setting-bps-sel@100a2c0 { + compatible = "renesas,ofs-memory"; + reg = <0x0100a2c0 0x4>; + status = "okay"; + }; + }; }; clocks: clocks { diff --git a/dts/arm/renesas/ra/ra4/r7fa4m3ax.dtsi b/dts/arm/renesas/ra/ra4/r7fa4m3ax.dtsi index a34f041f1a41e..20e06b12c63dd 100644 --- a/dts/arm/renesas/ra/ra4/r7fa4m3ax.dtsi +++ b/dts/arm/renesas/ra/ra4/r7fa4m3ax.dtsi @@ -157,6 +157,63 @@ compatible = "renesas,ra-sce9-rng"; status = "disabled"; }; + + option_setting_ofs_conf: option-setting-ofs-conf@100a100 { + compatible = "zephyr,memory-region"; + reg = <0x0100a100 0x200>; + zephyr,memory-region = "OFS_CONF_MEMORY"; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + option_setting_ofs0: option-setting-ofs0@100a100 { + compatible = "renesas,ofs-memory"; + reg = <0x0100a100 0x4>; + status = "okay"; + }; + + option_setting_ofs1_sec: option-setting-ofs1-sec@100a200 { + compatible = "renesas,ofs-memory"; + reg = <0x0100a200 0x4>; + status = "okay"; + }; + + option_setting_banksel_sec: option-setting-banksel-sec@100a210 { + compatible = "renesas,ofs-memory"; + reg = <0x0100a210 0x4>; + status = "okay"; + }; + + option_setting_bps_sec: option-setting-bps-sec@100a240 { + compatible = "renesas,ofs-memory"; + reg = <0x0100a240 0x8>; + status = "okay"; + }; + + option_setting_pbps_sec: option-setting-pbps-sec@100a260 { + compatible = "renesas,ofs-memory"; + reg = <0x0100a260 0x8>; + status = "okay"; + }; + + option_setting_ofs1_sel: option-setting-ofs1-sel@100a280 { + compatible = "renesas,ofs-memory"; + reg = <0x0100a280 0x4>; + status = "okay"; + }; + + option_setting_banksel_sel: option-setting-banksel-sel@100a290 { + compatible = "renesas,ofs-memory"; + reg = <0x0100a290 0x4>; + status = "okay"; + }; + + option_setting_bps_sel: option-setting-bps-sel@100a2c0 { + compatible = "renesas,ofs-memory"; + reg = <0x0100a2c0 0x8>; + status = "okay"; + }; + }; }; clocks: clocks { diff --git a/dts/arm/renesas/ra/ra4/ra4-cm33-common.dtsi b/dts/arm/renesas/ra/ra4/ra4-cm33-common.dtsi index 9e78fae149ca7..4558a384ea063 100644 --- a/dts/arm/renesas/ra/ra4/ra4-cm33-common.dtsi +++ b/dts/arm/renesas/ra/ra4/ra4-cm33-common.dtsi @@ -341,27 +341,6 @@ }; }; - option_setting_ofs: option_setting_ofs@100a100 { - compatible = "zephyr,memory-region"; - reg = <0x0100a100 0x18>; - zephyr,memory-region = "OPTION_SETTING_OFS"; - status = "okay"; - }; - - option_setting_sas: option_setting_sas@100a134 { - compatible = "zephyr,memory-region"; - reg = <0x0100a134 0xcc>; - zephyr,memory-region = "OPTION_SETTING_SAS"; - status = "okay"; - }; - - option_setting_s: option_setting_s@100a200 { - compatible = "zephyr,memory-region"; - reg = <0x0100a200 0x100>; - zephyr,memory-region = "OPTION_SETTING_S"; - status = "okay"; - }; - port_irq0: external-interrupt@40006000 { compatible = "renesas,ra-external-interrupt"; reg = <0x40006000 0x1>; diff --git a/dts/arm/renesas/ra/ra4/ra4-cm4-common.dtsi b/dts/arm/renesas/ra/ra4/ra4-cm4-common.dtsi index 7319a75f79f6f..59c4165fcb150 100644 --- a/dts/arm/renesas/ra/ra4/ra4-cm4-common.dtsi +++ b/dts/arm/renesas/ra/ra4/ra4-cm4-common.dtsi @@ -271,13 +271,6 @@ }; }; - id_code: id_code@1010018 { - compatible = "zephyr,memory-region"; - reg = <0x01010018 0x20>; - zephyr,memory-region = "ID_CODE"; - status = "okay"; - }; - port_irq0: external-interrupt@40006000 { compatible = "renesas,ra-external-interrupt"; reg = <0x40006000 0x1>; @@ -441,6 +434,45 @@ clocks = <&pclkb 0 0>; status = "disabled"; }; + + option_setting_ofs_in_rom: option-setting-ofs-in-rom@400 { + reg = <0x00000400 0x3c>; + #address-cells = <1>; + #size-cells = <0>; + + option_setting_ofs0: option-setting-ofs0@400 { + compatible = "renesas,ofs-memory"; + reg = <0x00000400 0x4>; + status = "okay"; + }; + + option_setting_ofs1: option-setting-ofs1@404 { + compatible = "renesas,ofs-memory"; + reg = <0x00000404 0x4>; + status = "okay"; + }; + + option_setting_secmpu: option-setting-secmpu@408 { + compatible = "renesas,ofs-memory"; + reg = <0x00000408 0x34>; + status = "okay"; + }; + }; + + option_setting_ofs_conf: option-setting-ofs-conf@1010008 { + compatible = "zephyr,memory-region"; + reg = <0x01010008 0x2c>; + zephyr,memory-region = "OFS_CONF_MEMORY"; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + option_setting_osis: option-setting-osis@1010018 { + compatible = "renesas,ofs-memory"; + reg = <0x01010018 0x1c>; + status = "okay"; + }; + }; }; usbfs_phy: usbfs-phy { diff --git a/dts/arm/renesas/ra/ra6/r7fa6e10x.dtsi b/dts/arm/renesas/ra/ra6/r7fa6e10x.dtsi index 8ebba8a22ba97..a48023db84257 100644 --- a/dts/arm/renesas/ra/ra6/r7fa6e10x.dtsi +++ b/dts/arm/renesas/ra/ra6/r7fa6e10x.dtsi @@ -123,6 +123,69 @@ compatible = "renesas,ra-sce9-rng"; status = "disabled"; }; + + option_setting_ofs_conf: option-setting-ofs-conf@100a100 { + compatible = "zephyr,memory-region"; + reg = <0x0100a100 0x200>; + zephyr,memory-region = "OFS_CONF_MEMORY"; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + option_setting_ofs0: option-setting-ofs0@100a100 { + compatible = "renesas,ofs-memory"; + reg = <0x0100a100 0x4>; + status = "okay"; + }; + + option_setting_dualsel: option-setting-dualsel@100a110 { + compatible = "renesas,ofs-memory"; + reg = <0x0100a110 0x4>; + status = "okay"; + }; + + option_setting_ofs1_sec: option-setting-ofs1-sec@100a200 { + compatible = "renesas,ofs-memory"; + reg = <0x0100a200 0x4>; + status = "okay"; + }; + + option_setting_banksel_sec: option-setting-banksel-sec@100a210 { + compatible = "renesas,ofs-memory"; + reg = <0x0100a210 0x4>; + status = "okay"; + }; + + option_setting_bps_sec: option-setting-bps-sec@100a240 { + compatible = "renesas,ofs-memory"; + reg = <0x0100a240 0xc>; + status = "okay"; + }; + + option_setting_pbps_sec: option-setting-pbps-sec@100a260 { + compatible = "renesas,ofs-memory"; + reg = <0x0100a260 0xc>; + status = "okay"; + }; + + option_setting_ofs1_sel: option-setting-ofs1-sel@100a280 { + compatible = "renesas,ofs-memory"; + reg = <0x0100a280 0x4>; + status = "okay"; + }; + + option_setting_banksel_sel: option-setting-banksel-sel@100a290 { + compatible = "renesas,ofs-memory"; + reg = <0x0100a290 0x4>; + status = "okay"; + }; + + option_setting_bps_sel: option-setting-bps-sel@100a2c0 { + compatible = "renesas,ofs-memory"; + reg = <0x0100a2c0 0xc>; + status = "okay"; + }; + }; }; clocks: clocks { diff --git a/dts/arm/renesas/ra/ra6/r7fa6e2bx.dtsi b/dts/arm/renesas/ra/ra6/r7fa6e2bx.dtsi index 68336cafa893e..97c0eea22d55d 100644 --- a/dts/arm/renesas/ra/ra6/r7fa6e2bx.dtsi +++ b/dts/arm/renesas/ra/ra6/r7fa6e2bx.dtsi @@ -42,13 +42,6 @@ channel-available-mask = <0x139f7>; }; - id_code: id_code@100a120 { - compatible = "zephyr,memory-region"; - reg = <0x0100a120 0x10>; - zephyr,memory-region = "ID_CODE"; - status = "okay"; - }; - canfd_global: canfd_global@400b0000 { compatible = "renesas,ra-canfd-global"; interrupts = <40 1>, <41 1>; @@ -124,6 +117,45 @@ status = "disabled"; }; }; + + option_setting_ofs_conf: option-setting-ofs-conf@100a100 { + compatible = "zephyr,memory-region"; + reg = <0x0100a100 0x200>; + zephyr,memory-region = "OFS_CONF_MEMORY"; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + option_setting_ofs0: option-setting-ofs0@100a100 { + compatible = "renesas,ofs-memory"; + reg = <0x0100a100 0x4>; + status = "okay"; + }; + + option_setting_osis: option-setting-osis@100a120 { + compatible = "renesas,ofs-memory"; + reg = <0x0100a120 0x10>; + status = "okay"; + }; + + option_setting_ofs1_sec: option-setting-ofs1-sec@100a200 { + compatible = "renesas,ofs-memory"; + reg = <0x0100a200 0x4>; + status = "okay"; + }; + + option_setting_bps_sec: option-setting-bps-sec@100a240 { + compatible = "renesas,ofs-memory"; + reg = <0x0100a240 0x4>; + status = "okay"; + }; + + option_setting_pbps_sec: option-setting-pbps-sec@100a260 { + compatible = "renesas,ofs-memory"; + reg = <0x0100a260 0x4>; + status = "okay"; + }; + }; }; clocks: clocks { diff --git a/dts/arm/renesas/ra/ra6/r7fa6m1ad3cfp.dtsi b/dts/arm/renesas/ra/ra6/r7fa6m1ad3cfp.dtsi index 6fd2261436698..dbb0455c641db 100644 --- a/dts/arm/renesas/ra/ra6/r7fa6m1ad3cfp.dtsi +++ b/dts/arm/renesas/ra/ra6/r7fa6m1ad3cfp.dtsi @@ -53,6 +53,45 @@ adc@4005c200 { channel-available-mask = <0x300e7>; }; + + option_setting_ofs_in_rom: option-setting-ofs-in-rom@400 { + reg = <0x00000400 0x3c>; + #address-cells = <1>; + #size-cells = <0>; + + option_setting_ofs0: option-setting-ofs0@400 { + compatible = "renesas,ofs-memory"; + reg = <0x00000400 0x4>; + status = "okay"; + }; + + option_setting_ofs1: option-setting-ofs1@404 { + compatible = "renesas,ofs-memory"; + reg = <0x00000404 0x4>; + status = "okay"; + }; + + option_setting_secmpu: option-setting-secmpu@408 { + compatible = "renesas,ofs-memory"; + reg = <0x00000408 0x34>; + status = "okay"; + }; + }; + + option_setting_ofs_conf: option-setting-ofs-conf@100a150 { + compatible = "zephyr,memory-region"; + reg = <0x0100a150 0x18>; + zephyr,memory-region = "OFS_CONF_MEMORY"; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + option_setting_osis: option-setting-osis@100a150 { + compatible = "renesas,ofs-memory"; + reg = <0x0100a150 0x10>; + status = "okay"; + }; + }; }; clocks: clocks { diff --git a/dts/arm/renesas/ra/ra6/r7fa6m2ax.dtsi b/dts/arm/renesas/ra/ra6/r7fa6m2ax.dtsi index 0908d4e6545bc..5382c36e9fa79 100644 --- a/dts/arm/renesas/ra/ra6/r7fa6m2ax.dtsi +++ b/dts/arm/renesas/ra/ra6/r7fa6m2ax.dtsi @@ -81,6 +81,45 @@ #pwm-cells = <3>; status = "disabled"; }; + + option_setting_ofs_in_rom: option-setting-ofs-in-rom@400 { + reg = <0x00000400 0x3c>; + #address-cells = <1>; + #size-cells = <0>; + + option_setting_ofs0: option-setting-ofs0@400 { + compatible = "renesas,ofs-memory"; + reg = <0x00000400 0x4>; + status = "okay"; + }; + + option_setting_ofs1: option-setting-ofs1@404 { + compatible = "renesas,ofs-memory"; + reg = <0x00000404 0x4>; + status = "okay"; + }; + + option_setting_secmpu: option-setting-secmpu@408 { + compatible = "renesas,ofs-memory"; + reg = <0x00000408 0x34>; + status = "okay"; + }; + }; + + option_setting_ofs_conf: option-setting-ofs-conf@100a150 { + compatible = "zephyr,memory-region"; + reg = <0x0100a150 0x18>; + zephyr,memory-region = "OFS_CONF_MEMORY"; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + option_setting_osis: option-setting-osis@100a150 { + compatible = "renesas,ofs-memory"; + reg = <0x0100a150 0x10>; + status = "okay"; + }; + }; }; clocks: clocks { diff --git a/dts/arm/renesas/ra/ra6/r7fa6m3ax.dtsi b/dts/arm/renesas/ra/ra6/r7fa6m3ax.dtsi index d0d96a1ec1da2..4ece673930e43 100644 --- a/dts/arm/renesas/ra/ra6/r7fa6m3ax.dtsi +++ b/dts/arm/renesas/ra/ra6/r7fa6m3ax.dtsi @@ -137,6 +137,45 @@ #pwm-cells = <3>; status = "disabled"; }; + + option_setting_ofs_in_rom: option-setting-ofs-in-rom@400 { + reg = <0x00000400 0x3c>; + #address-cells = <1>; + #size-cells = <0>; + + option_setting_ofs0: option-setting-ofs0@400 { + compatible = "renesas,ofs-memory"; + reg = <0x00000400 0x4>; + status = "okay"; + }; + + option_setting_ofs1: option-setting-ofs1@404 { + compatible = "renesas,ofs-memory"; + reg = <0x00000404 0x4>; + status = "okay"; + }; + + option_setting_secmpu: option-setting-secmpu@408 { + compatible = "renesas,ofs-memory"; + reg = <0x00000408 0x34>; + status = "okay"; + }; + }; + + option_setting_ofs_conf: option-setting-ofs-conf@100a150 { + compatible = "zephyr,memory-region"; + reg = <0x0100a150 0x18>; + zephyr,memory-region = "OFS_CONF_MEMORY"; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + option_setting_osis: option-setting-osis@100a150 { + compatible = "renesas,ofs-memory"; + reg = <0x0100a150 0x10>; + status = "okay"; + }; + }; }; clocks: clocks { diff --git a/dts/arm/renesas/ra/ra6/r7fa6m4ax.dtsi b/dts/arm/renesas/ra/ra6/r7fa6m4ax.dtsi index 83a19e70135fb..7598c6adcf3d5 100644 --- a/dts/arm/renesas/ra/ra6/r7fa6m4ax.dtsi +++ b/dts/arm/renesas/ra/ra6/r7fa6m4ax.dtsi @@ -230,6 +230,69 @@ compatible = "renesas,ra-sce9-rng"; status = "disabled"; }; + + option_setting_ofs_conf: option-setting-ofs-conf@100a100 { + compatible = "zephyr,memory-region"; + reg = <0x0100a100 0x200>; + zephyr,memory-region = "OFS_CONF_MEMORY"; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + option_setting_ofs0: option-setting-ofs0@100a100 { + compatible = "renesas,ofs-memory"; + reg = <0x0100a100 0x4>; + status = "okay"; + }; + + option_setting_dualsel: option-setting-dualsel@100a110 { + compatible = "renesas,ofs-memory"; + reg = <0x0100a110 0x4>; + status = "okay"; + }; + + option_setting_ofs1_sec: option-setting-ofs1-sec@100a200 { + compatible = "renesas,ofs-memory"; + reg = <0x0100a200 0x4>; + status = "okay"; + }; + + option_setting_banksel_sec: option-setting-banksel-sec@100a210 { + compatible = "renesas,ofs-memory"; + reg = <0x0100a210 0x4>; + status = "okay"; + }; + + option_setting_bps_sec: option-setting-bps-sec@100a240 { + compatible = "renesas,ofs-memory"; + reg = <0x0100a240 0x10>; + status = "okay"; + }; + + option_setting_pbps_sec: option-setting-pbps-sec@100a260 { + compatible = "renesas,ofs-memory"; + reg = <0x0100a260 0x10>; + status = "okay"; + }; + + option_setting_ofs1_sel: option-setting-ofs1-sel@100a280 { + compatible = "renesas,ofs-memory"; + reg = <0x0100a280 0x4>; + status = "okay"; + }; + + option_setting_banksel_sel: option-setting-banksel-sel@100a290 { + compatible = "renesas,ofs-memory"; + reg = <0x0100a290 0x4>; + status = "okay"; + }; + + option_setting_bps_sel: option-setting-bps-sel@100a2c0 { + compatible = "renesas,ofs-memory"; + reg = <0x0100a2c0 0x10>; + status = "okay"; + }; + }; }; clocks: clocks { diff --git a/dts/arm/renesas/ra/ra6/r7fa6m5xh.dtsi b/dts/arm/renesas/ra/ra6/r7fa6m5xh.dtsi index e130b0755132e..d6dc47095321a 100644 --- a/dts/arm/renesas/ra/ra6/r7fa6m5xh.dtsi +++ b/dts/arm/renesas/ra/ra6/r7fa6m5xh.dtsi @@ -282,6 +282,69 @@ compatible = "renesas,ra-sce9-rng"; status = "disabled"; }; + + option_setting_ofs_conf: option-setting-ofs-conf@100a100 { + compatible = "zephyr,memory-region"; + reg = <0x0100a100 0x200>; + zephyr,memory-region = "OFS_CONF_MEMORY"; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + option_setting_ofs0: option-setting-ofs0@100a100 { + compatible = "renesas,ofs-memory"; + reg = <0x0100a100 0x4>; + status = "okay"; + }; + + option_setting_dualsel: option-setting-dualsel@100a110 { + compatible = "renesas,ofs-memory"; + reg = <0x0100a110 0x4>; + status = "okay"; + }; + + option_setting_ofs1_sec: option-setting-ofs1-sec@100a200 { + compatible = "renesas,ofs-memory"; + reg = <0x0100a200 0x4>; + status = "okay"; + }; + + option_setting_banksel_sec: option-setting-banksel-sec@100a210 { + compatible = "renesas,ofs-memory"; + reg = <0x0100a210 0x4>; + status = "okay"; + }; + + option_setting_bps_sec: option-setting-bps-sec@100a240 { + compatible = "renesas,ofs-memory"; + reg = <0x0100a240 0x10>; + status = "okay"; + }; + + option_setting_pbps_sec: option-setting-pbps-sec@100a260 { + compatible = "renesas,ofs-memory"; + reg = <0x0100a260 0x10>; + status = "okay"; + }; + + option_setting_ofs1_sel: option-setting-ofs1-sel@100a280 { + compatible = "renesas,ofs-memory"; + reg = <0x0100a280 0x4>; + status = "okay"; + }; + + option_setting_banksel_sel: option-setting-banksel-sel@100a290 { + compatible = "renesas,ofs-memory"; + reg = <0x0100a290 0x4>; + status = "okay"; + }; + + option_setting_bps_sel: option-setting-bps-sel@100a2c0 { + compatible = "renesas,ofs-memory"; + reg = <0x0100a2c0 0x10>; + status = "okay"; + }; + }; }; clocks: clocks { diff --git a/dts/arm/renesas/ra/ra6/ra6-cm33-common.dtsi b/dts/arm/renesas/ra/ra6/ra6-cm33-common.dtsi index 9625343ec278a..6193b70ccaa91 100644 --- a/dts/arm/renesas/ra/ra6/ra6-cm33-common.dtsi +++ b/dts/arm/renesas/ra/ra6/ra6-cm33-common.dtsi @@ -324,13 +324,6 @@ }; }; - option_setting_ofs: option_setting_ofs@100a100 { - compatible = "zephyr,memory-region"; - reg = <0x0100a100 0x18>; - zephyr,memory-region = "OPTION_SETTING_OFS"; - status = "okay"; - }; - flash: flash-controller@407e0000 { compatible = "renesas,ra-flash-hp-controller"; reg = <0x407e0000 0x10000>; @@ -340,20 +333,6 @@ interrupt-names = "frdyi", "fiferr"; }; - option_setting_sas: option_setting_sas@100a134 { - compatible = "zephyr,memory-region"; - reg = <0x0100a134 0xcc>; - zephyr,memory-region = "OPTION_SETTING_SAS"; - status = "okay"; - }; - - option_setting_s: option_setting_s@100a200 { - compatible = "zephyr,memory-region"; - reg = <0x0100a200 0x100>; - zephyr,memory-region = "OPTION_SETTING_S"; - status = "okay"; - }; - port_irq0: external-interrupt@40006000 { compatible = "renesas,ra-external-interrupt"; reg = <0x40006000 0x1>; diff --git a/dts/arm/renesas/ra/ra6/ra6-cm4-common.dtsi b/dts/arm/renesas/ra/ra6/ra6-cm4-common.dtsi index dd2c9cacddff7..a50f6fe1479a9 100644 --- a/dts/arm/renesas/ra/ra6/ra6-cm4-common.dtsi +++ b/dts/arm/renesas/ra/ra6/ra6-cm4-common.dtsi @@ -343,13 +343,6 @@ }; }; - id_code: id_code@100a150 { - compatible = "zephyr,memory-region"; - reg = <0x0100a150 0x10>; - zephyr,memory-region = "ID_CODE"; - status = "okay"; - }; - port_irq0: external-interrupt@40006000 { compatible = "renesas,ra-external-interrupt"; reg = <0x40006000 0x1>; diff --git a/dts/arm/renesas/ra/ra8/ra8x1.dtsi b/dts/arm/renesas/ra/ra8/ra8x1.dtsi index a6436cbffb83f..20d102e11fb02 100644 --- a/dts/arm/renesas/ra/ra8/ra8x1.dtsi +++ b/dts/arm/renesas/ra/ra8/ra8x1.dtsi @@ -610,27 +610,6 @@ status = "disabled"; }; - option_setting_ofs: option_setting_ofs@300a100 { - compatible = "zephyr,memory-region"; - reg = <0x0300a100 0x18>; - zephyr,memory-region = "OPTION_SETTING_OFS"; - status = "okay"; - }; - - option_setting_sas: option_setting_sas@300a134 { - compatible = "zephyr,memory-region"; - reg = <0x0300a134 0xcc>; - zephyr,memory-region = "OPTION_SETTING_SAS"; - status = "okay"; - }; - - option_setting_s: option_setting_s@300a200 { - compatible = "zephyr,memory-region"; - reg = <0x0300a200 0x100>; - zephyr,memory-region = "OPTION_SETTING_S"; - status = "okay"; - }; - agt0: agt@40221000 { compatible = "renesas,ra-agt"; channel = <0>; @@ -949,6 +928,75 @@ status = "disabled"; }; + option_setting_ofs_cf_sec: option-setting-ofs-cf-sec@300a100 { + compatible = "zephyr,memory-region"; + reg = <0x0300a100 0x200>; + zephyr,memory-region = "OFS_CF_SEC_MEMORY"; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + option_setting_ofs0: option-setting-ofs0@300a100 { + compatible = "renesas,ofs-memory"; + reg = <0x0300a100 0x4>; + status = "okay"; + }; + + option_setting_ofs2: option-setting-ofs2@300a104 { + compatible = "renesas,ofs-memory"; + reg = <0x0300a104 0x4>; + status = "okay"; + }; + + option_setting_dualsel: option-setting-dualsel@300a110 { + compatible = "renesas,ofs-memory"; + reg = <0x0300a110 0x4>; + status = "okay"; + }; + + option_setting_ofs1_sec: option-setting-ofs1-sec@300a200 { + compatible = "renesas,ofs-memory"; + reg = <0x0300a200 0x4>; + status = "okay"; + }; + + option_setting_banksel_sec: option-setting-banksel-sec@300a210 { + compatible = "renesas,ofs-memory"; + reg = <0x0300a210 0x4>; + status = "okay"; + }; + + option_setting_bps_sec: option-setting-bps-sec@300a240 { + compatible = "renesas,ofs-memory"; + reg = <0x0300a240 0x10>; + status = "okay"; + }; + + option_setting_pbps_sec: option-setting-pbps-sec@300a260 { + compatible = "renesas,ofs-memory"; + reg = <0x0300a260 0x10>; + status = "okay"; + }; + + option_setting_ofs1_sel: option-setting-ofs1-sel@300a280 { + compatible = "renesas,ofs-memory"; + reg = <0x0300a280 0x4>; + status = "okay"; + }; + + option_setting_banksel_sel: option-setting-banksel-sel@300a290 { + compatible = "renesas,ofs-memory"; + reg = <0x0300a290 0x4>; + status = "okay"; + }; + + option_setting_bps_sel: option-setting-bps-sel@300a2c0 { + compatible = "renesas,ofs-memory"; + reg = <0x0300a2c0 0x10>; + status = "okay"; + }; + }; + }; usbfs_phy: usbfs-phy { diff --git a/dts/arm/renesas/ra/ra8/ra8x2.dtsi b/dts/arm/renesas/ra/ra8/ra8x2.dtsi index 6d042877101c0..28b8449f05657 100644 --- a/dts/arm/renesas/ra/ra8/ra8x2.dtsi +++ b/dts/arm/renesas/ra/ra8/ra8x2.dtsi @@ -1039,6 +1039,78 @@ reg = <0x40252400 0x0400>; status = "disabled"; }; + + option_setting_ofs_conf_sec: option-setting-ofs-conf-sec@2c9f040 { + compatible = "zephyr,memory-region"; + reg = <0x02c9f040 0x3c0>; + zephyr,memory-region = "OFS_CONF_SEC_MEMORY"; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + option_setting_ofs0: option-setting-ofs0@2c9f040 { + compatible = "renesas,ofs-memory"; + reg = <0x02c9f040 0x4>; + status = "okay"; + }; + + option_setting_ofs2: option-setting-ofs2@2c9f044 { + compatible = "renesas,ofs-memory"; + reg = <0x02c9f044 0x4>; + status = "okay"; + }; + + option_setting_sas: option-setting-sas@2c9f074 { + compatible = "renesas,ofs-memory"; + reg = <0x02c9f074 0x4>; + status = "okay"; + }; + + option_setting_ofs1_sec: option-setting-ofs1-sec@2c9f0c0 { + compatible = "renesas,ofs-memory"; + reg = <0x02c9f0c0 0x4>; + status = "okay"; + }; + + option_setting_ofs3_sec: option-setting-ofs3-sec@2c9f0c4 { + compatible = "renesas,ofs-memory"; + reg = <0x02c9f0c4 0x4>; + status = "okay"; + }; + + option_setting_ofs1_sel: option-setting-ofs1-sel@2c9f120 { + compatible = "renesas,ofs-memory"; + reg = <0x02c9f120 0x4>; + status = "okay"; + }; + + option_setting_ofs3_sel: option-setting-ofs3-sel@2c9f124 { + compatible = "renesas,ofs-memory"; + reg = <0x02c9f124 0x4>; + status = "okay"; + }; + + option_setting_bps_sec: option-setting-bps-sec@2c9f200 { + compatible = "renesas,ofs-memory"; + reg = <0x02c9f200 0x200>; + status = "okay"; + }; + }; + + option_setting_ofs_otp_sec: option-setting-ofs-otp-sec@2e07400 { + compatible = "zephyr,memory-region"; + reg = <0x02e07400 0xa30>; + zephyr,memory-region = "OFS_OTP_SEC_MEMORY"; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + option_setting_otp_pbps_sec: option-setting-otp-pbps-sec@2e17700 { + compatible = "renesas,ofs-memory"; + reg = <0x02e17700 0x80>; + status = "okay"; + }; + }; }; }; diff --git a/dts/bindings/reserved-memory/renesas,ofs-memory.yaml b/dts/bindings/reserved-memory/renesas,ofs-memory.yaml new file mode 100644 index 0000000000000..d2eeb7bfebf3f --- /dev/null +++ b/dts/bindings/reserved-memory/renesas,ofs-memory.yaml @@ -0,0 +1,17 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +description: | + Renesas Option-Setting Memory + + The option-setting memory determines the state of the MCU after a reset. + The option-setting memory is allocated to the configuration setting area + of the flash memory. + +compatible: "renesas,ofs-memory" + +include: [base.yaml] + +properties: + reg: + required: true diff --git a/soc/renesas/ra/ra2a1/CMakeLists.txt b/soc/renesas/ra/ra2a1/CMakeLists.txt index 223a8efd7a41c..428e74e14452b 100644 --- a/soc/renesas/ra/ra2a1/CMakeLists.txt +++ b/soc/renesas/ra/ra2a1/CMakeLists.txt @@ -1,4 +1,5 @@ # Copyright (c) 2024 TOKITA Hiroshi +# Copyright (c) 2025 Renesas Electronics Corporation # SPDX-License-Identifier: Apache-2.0 zephyr_include_directories(.) @@ -8,7 +9,6 @@ zephyr_sources( ) zephyr_linker_sources(SECTIONS sections.ld) -zephyr_linker_sources(DATA_SECTIONS data_sections.ld) zephyr_linker_sources(RAM_SECTIONS ram_sections.ld) zephyr_linker_sources(ROM_START rom_start.ld) diff --git a/soc/renesas/ra/ra2a1/data_sections.ld b/soc/renesas/ra/ra2a1/data_sections.ld deleted file mode 100644 index 84cb7c088e838..0000000000000 --- a/soc/renesas/ra/ra2a1/data_sections.ld +++ /dev/null @@ -1,13 +0,0 @@ -/* - * Copyright (c) 2024 TOKITA Hiroshi - * - * SPDX-License-Identifier: Apache-2.0 - */ - -.code_in_ram : -{ - . = ALIGN(4); - __Code_In_RAM_Start = .; - KEEP(*(.code_in_ram*)) - __Code_In_RAM_End = .; -} > RAMABLE_REGION diff --git a/soc/renesas/ra/ra2a1/ram_sections.ld b/soc/renesas/ra/ra2a1/ram_sections.ld index 2f1217ef57bdb..ece8ea46fa477 100644 --- a/soc/renesas/ra/ra2a1/ram_sections.ld +++ b/soc/renesas/ra/ra2a1/ram_sections.ld @@ -1,12 +1,17 @@ /* * Copyright (c) 2024 TOKITA Hiroshi + * Copyright (c) 2025 Renesas Electronics Corporation * * SPDX-License-Identifier: Apache-2.0 */ +#include + +#ifdef CONFIG_USE_RA_FSP_DTC SECTION_DATA_PROLOGUE(.fsp_dtc_vector_table,(NOLOAD),) { /* If DTC is used, put the DTC vector table at the start of SRAM. This avoids memory holes due to 1K alignment required by it. */ *(.fsp_dtc_vector_table) } GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION) +#endif /* CONFIG_USE_RA_FSP_DTC */ diff --git a/soc/renesas/ra/ra2a1/rom_start.ld b/soc/renesas/ra/ra2a1/rom_start.ld index 64eb3c891e043..14d4ca6737748 100644 --- a/soc/renesas/ra/ra2a1/rom_start.ld +++ b/soc/renesas/ra/ra2a1/rom_start.ld @@ -1,11 +1,17 @@ /* * Copyright (c) 2024 TOKITA Hiroshi + * Copyright (c) 2025 Renesas Electronics Corporation * * SPDX-License-Identifier: Apache-2.0 */ -/* ROM Registers start at address 0x00000400 */ -. = 0x400; -KEEP(*(.rom_registers*)) -/* Reserving 0x100 bytes of space for ROM registers. */ -. = 0x500; +#include + +. = DT_REG_ADDR(DT_NODELABEL(option_setting_ofs0)); +KEEP(*(.option_setting_ofs0)) + +. = DT_REG_ADDR(DT_NODELABEL(option_setting_ofs1)); +KEEP(*(.option_setting_ofs1)) + +. = DT_REG_ADDR(DT_NODELABEL(option_setting_secmpu)); +KEEP(*(.option_setting_secmpu)) diff --git a/soc/renesas/ra/ra2a1/sections.ld b/soc/renesas/ra/ra2a1/sections.ld index 9338be067c817..0736423ebaa7a 100644 --- a/soc/renesas/ra/ra2a1/sections.ld +++ b/soc/renesas/ra/ra2a1/sections.ld @@ -1,116 +1,15 @@ /* * Copyright (c) 2024 TOKITA Hiroshi + * Copyright (c) 2025 Renesas Electronics Corporation * * SPDX-License-Identifier: Apache-2.0 */ -#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(id_code)) +#include -SECTION_PROLOGUE(.id_code,,) +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_osis)) +SECTION_DATA_PROLOGUE(.option_setting_osis,,) { - KEEP(*(.id_code*)) -} GROUP_LINK_IN(ID_CODE) - -#endif - -#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_ofs)) - -SECTION_PROLOGUE(.option_setting_ofs,,) -{ - __OPTION_SETTING_OFS_Start = .; - KEEP(*(.option_setting_ofs0)) - . = __OPTION_SETTING_OFS_Start + 0x04; - KEEP(*(.option_setting_ofs2)) - . = __OPTION_SETTING_OFS_Start + 0x10; - KEEP(*(.option_setting_dualsel)) - __OPTION_SETTING_OFS_End = .; -} GROUP_LINK_IN(OPTION_SETTING_OFS) = 0xFF - -#endif - -#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_sas)) - -SECTION_PROLOGUE(.option_setting_sas,,) -{ - __OPTION_SETTING_SAS_Start = .; - KEEP(*(.option_setting_sas)) - __OPTION_SETTING_SAS_End = .; -} GROUP_LINK_IN(OPTION_SETTING_SAS) = 0xFF - -#endif - -#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_ns)) - -SECTION_PROLOGUE(.option_setting_ns,,) -{ - __OPTION_SETTING_NS_Start = .; - KEEP(*(.option_setting_ofs1)) - . = __OPTION_SETTING_NS_Start + 0x04; - KEEP(*(.option_setting_ofs3)) - . = __OPTION_SETTING_NS_Start + 0x10; - KEEP(*(.option_setting_banksel)) - . = __OPTION_SETTING_NS_Start + 0x40; - KEEP(*(.option_setting_bps0)) - . = __OPTION_SETTING_NS_Start + 0x44; - KEEP(*(.option_setting_bps1)) - . = __OPTION_SETTING_NS_Start + 0x48; - KEEP(*(.option_setting_bps2)) - . = __OPTION_SETTING_NS_Start + 0x4C; - KEEP(*(.option_setting_bps3)) - . = __OPTION_SETTING_NS_Start + 0x60; - KEEP(*(.option_setting_pbps0)) - . = __OPTION_SETTING_NS_Start + 0x64; - KEEP(*(.option_setting_pbps1)) - . = __OPTION_SETTING_NS_Start + 0x68; - KEEP(*(.option_setting_pbps2)) - . = __OPTION_SETTING_NS_Start + 0x6C; - KEEP(*(.option_setting_pbps3)) - __OPTION_SETTING_NS_End = .; -} GROUP_LINK_IN(OPTION_SETTING) = 0xFF - -#endif - -#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_s)) - -SECTION_PROLOGUE(.option_setting_s,,) -{ - __OPTION_SETTING_S_Start = .; - KEEP(*(.option_setting_ofs1_sec)) - . = __OPTION_SETTING_S_Start + 0x04; - KEEP(*(.option_setting_ofs3_sec)) - . = __OPTION_SETTING_S_Start + 0x10; - KEEP(*(.option_setting_banksel_sec)) - . = __OPTION_SETTING_S_Start + 0x40; - KEEP(*(.option_setting_bps_sec0)) - . = __OPTION_SETTING_S_Start + 0x44; - KEEP(*(.option_setting_bps_sec1)) - . = __OPTION_SETTING_S_Start + 0x48; - KEEP(*(.option_setting_bps_sec2)) - . = __OPTION_SETTING_S_Start + 0x4C; - KEEP(*(.option_setting_bps_sec3)) - . = __OPTION_SETTING_S_Start + 0x60; - KEEP(*(.option_setting_pbps_sec0)) - . = __OPTION_SETTING_S_Start + 0x64; - KEEP(*(.option_setting_pbps_sec1)) - . = __OPTION_SETTING_S_Start + 0x68; - KEEP(*(.option_setting_pbps_sec2)) - . = __OPTION_SETTING_S_Start + 0x6C; - KEEP(*(.option_setting_pbps_sec3)) - . = __OPTION_SETTING_S_Start + 0x80; - KEEP(*(.option_setting_ofs1_sel)) - . = __OPTION_SETTING_S_Start + 0x84; - KEEP(*(.option_setting_ofs3_sel)) - . = __OPTION_SETTING_S_Start + 0x90; - KEEP(*(.option_setting_banksel_sel)) - . = __OPTION_SETTING_S_Start + 0xC0; - KEEP(*(.option_setting_bps_sel0)) - . = __OPTION_SETTING_S_Start + 0xC4; - KEEP(*(.option_setting_bps_sel1)) - . = __OPTION_SETTING_S_Start + 0xC8; - KEEP(*(.option_setting_bps_sel2)) - . = __OPTION_SETTING_S_Start + 0xCC; - KEEP(*(.option_setting_bps_sel3)) - __OPTION_SETTING_S_End = .; -} GROUP_LINK_IN(OPTION_SETTING_S) = 0xFF - + KEEP(*(.option_setting_osis)) +} GROUP_LINK_IN(OFS_CONF_MEMORY) #endif diff --git a/soc/renesas/ra/ra2l1/CMakeLists.txt b/soc/renesas/ra/ra2l1/CMakeLists.txt index 240342ab88d24..7c68d4378516a 100644 --- a/soc/renesas/ra/ra2l1/CMakeLists.txt +++ b/soc/renesas/ra/ra2l1/CMakeLists.txt @@ -8,8 +8,9 @@ zephyr_sources( soc.c ) -zephyr_linker_sources(ROM_START opt_set_mem.ld) +zephyr_linker_sources(ROM_START rom_start.ld) zephyr_linker_sources(SECTIONS sections.ld) +zephyr_linker_sources(RAM_SECTIONS ram_sections.ld) set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/renesas/ra/ra2l1/opt_set_mem.ld b/soc/renesas/ra/ra2l1/opt_set_mem.ld deleted file mode 100644 index 07aef9e92d838..0000000000000 --- a/soc/renesas/ra/ra2l1/opt_set_mem.ld +++ /dev/null @@ -1,11 +0,0 @@ -/* - * Copyright (c) 2024 Renesas Electronics Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/* ROM Registers start at address 0x00000400 */ -. = 0x400; -KEEP(*(.rom_registers*)) -/* Reserving 0x100 bytes of space for ROM registers. */ -. = 0x500; diff --git a/soc/renesas/ra/ra2l1/ram_sections.ld b/soc/renesas/ra/ra2l1/ram_sections.ld new file mode 100644 index 0000000000000..18be2a431de2a --- /dev/null +++ b/soc/renesas/ra/ra2l1/ram_sections.ld @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +#ifdef CONFIG_USE_RA_FSP_DTC +SECTION_DATA_PROLOGUE(.fsp_dtc_vector_table,(NOLOAD),) +{ + /* If DTC is used, put the DTC vector table at the start of SRAM. + This avoids memory holes due to 1K alignment required by it. */ + *(.fsp_dtc_vector_table) +} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION) +#endif /* CONFIG_USE_RA_FSP_DTC */ diff --git a/soc/renesas/ra/ra2l1/rom_start.ld b/soc/renesas/ra/ra2l1/rom_start.ld new file mode 100644 index 0000000000000..835fbfe7a949c --- /dev/null +++ b/soc/renesas/ra/ra2l1/rom_start.ld @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2024-2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +. = DT_REG_ADDR(DT_NODELABEL(option_setting_ofs0)); +KEEP(*(.option_setting_ofs0)) + +. = DT_REG_ADDR(DT_NODELABEL(option_setting_ofs1)); +KEEP(*(.option_setting_ofs1)) + +. = DT_REG_ADDR(DT_NODELABEL(option_setting_secmpu)); +KEEP(*(.option_setting_secmpu)) diff --git a/soc/renesas/ra/ra2l1/sections.ld b/soc/renesas/ra/ra2l1/sections.ld index 5e7aad11ed7c3..cfecea7e3433f 100644 --- a/soc/renesas/ra/ra2l1/sections.ld +++ b/soc/renesas/ra/ra2l1/sections.ld @@ -1,123 +1,14 @@ /* - * Copyright (c) 2024 Renesas Electronics Corporation + * Copyright (c) 2024-2025 Renesas Electronics Corporation * * SPDX-License-Identifier: Apache-2.0 */ -SECTION_DATA_PROLOGUE(.fsp_dtc_vector_table,(NOLOAD),) -{ - /* If DTC is used, put the DTC vector table at the start of SRAM. - This avoids memory holes due to 1K alignment required by it. */ - *(.fsp_dtc_vector_table) -} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION) - -#if DT_NODE_HAS_STATUS(DT_NODELABEL(option_setting_ofs), okay) - -SECTION_PROLOGUE(.option_setting_ofs,,) -{ - __OPTION_SETTING_OFS_Start = .; - KEEP(*(.option_setting_ofs0)) - . = __OPTION_SETTING_OFS_Start + 0x04; - KEEP(*(.option_setting_ofs2)) - . = __OPTION_SETTING_OFS_Start + 0x10; - KEEP(*(.option_setting_dualsel)) - __OPTION_SETTING_OFS_End = .; -} GROUP_LINK_IN(OPTION_SETTING_OFS) = 0xFF - -#endif - -#if DT_NODE_HAS_STATUS(DT_NODELABEL(option_setting_sas), okay) - -SECTION_PROLOGUE(.option_setting_sas,,) -{ - __OPTION_SETTING_SAS_Start = .; - KEEP(*(.option_setting_sas)) - __OPTION_SETTING_SAS_End = .; -} GROUP_LINK_IN(OPTION_SETTING_SAS) = 0xFF - -#endif - -#if DT_NODE_HAS_STATUS(DT_NODELABEL(option_setting_ns), okay) +#include -SECTION_PROLOGUE(.option_setting_ns,,) +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_osis)) +SECTION_DATA_PROLOGUE(.option_setting_osis,,) { - __OPTION_SETTING_NS_Start = .; - KEEP(*(.option_setting_ofs1)) - . = __OPTION_SETTING_NS_Start + 0x04; - KEEP(*(.option_setting_ofs3)) - . = __OPTION_SETTING_NS_Start + 0x10; - KEEP(*(.option_setting_banksel)) - . = __OPTION_SETTING_NS_Start + 0x40; - KEEP(*(.option_setting_bps0)) - . = __OPTION_SETTING_NS_Start + 0x44; - KEEP(*(.option_setting_bps1)) - . = __OPTION_SETTING_NS_Start + 0x48; - KEEP(*(.option_setting_bps2)) - . = __OPTION_SETTING_NS_Start + 0x4C; - KEEP(*(.option_setting_bps3)) - . = __OPTION_SETTING_NS_Start + 0x60; - KEEP(*(.option_setting_pbps0)) - . = __OPTION_SETTING_NS_Start + 0x64; - KEEP(*(.option_setting_pbps1)) - . = __OPTION_SETTING_NS_Start + 0x68; - KEEP(*(.option_setting_pbps2)) - . = __OPTION_SETTING_NS_Start + 0x6C; - KEEP(*(.option_setting_pbps3)) - __OPTION_SETTING_NS_End = .; -} GROUP_LINK_IN(OPTION_SETTING) = 0xFF - -#endif - -#if DT_NODE_HAS_STATUS(DT_NODELABEL(option_setting_s), okay) - -SECTION_PROLOGUE(.option_setting_s,,) -{ - __OPTION_SETTING_S_Start = .; - KEEP(*(.option_setting_ofs1_sec)) - . = __OPTION_SETTING_S_Start + 0x04; - KEEP(*(.option_setting_ofs3_sec)) - . = __OPTION_SETTING_S_Start + 0x10; - KEEP(*(.option_setting_banksel_sec)) - . = __OPTION_SETTING_S_Start + 0x40; - KEEP(*(.option_setting_bps_sec0)) - . = __OPTION_SETTING_S_Start + 0x44; - KEEP(*(.option_setting_bps_sec1)) - . = __OPTION_SETTING_S_Start + 0x48; - KEEP(*(.option_setting_bps_sec2)) - . = __OPTION_SETTING_S_Start + 0x4C; - KEEP(*(.option_setting_bps_sec3)) - . = __OPTION_SETTING_S_Start + 0x60; - KEEP(*(.option_setting_pbps_sec0)) - . = __OPTION_SETTING_S_Start + 0x64; - KEEP(*(.option_setting_pbps_sec1)) - . = __OPTION_SETTING_S_Start + 0x68; - KEEP(*(.option_setting_pbps_sec2)) - . = __OPTION_SETTING_S_Start + 0x6C; - KEEP(*(.option_setting_pbps_sec3)) - . = __OPTION_SETTING_S_Start + 0x80; - KEEP(*(.option_setting_ofs1_sel)) - . = __OPTION_SETTING_S_Start + 0x84; - KEEP(*(.option_setting_ofs3_sel)) - . = __OPTION_SETTING_S_Start + 0x90; - KEEP(*(.option_setting_banksel_sel)) - . = __OPTION_SETTING_S_Start + 0xC0; - KEEP(*(.option_setting_bps_sel0)) - . = __OPTION_SETTING_S_Start + 0xC4; - KEEP(*(.option_setting_bps_sel1)) - . = __OPTION_SETTING_S_Start + 0xC8; - KEEP(*(.option_setting_bps_sel2)) - . = __OPTION_SETTING_S_Start + 0xCC; - KEEP(*(.option_setting_bps_sel3)) - __OPTION_SETTING_S_End = .; -} GROUP_LINK_IN(OPTION_SETTING_S) = 0xFF - -#endif - -#if DT_NODE_HAS_STATUS(DT_NODELABEL(id_code), okay) - -SECTION_PROLOGUE(.id_code,,) -{ - KEEP(*(.id_code*)) -} GROUP_LINK_IN(ID_CODE) - + KEEP(*(.option_setting_osis)) +} GROUP_LINK_IN(OFS_CONF_MEMORY) #endif diff --git a/soc/renesas/ra/ra4e1/CMakeLists.txt b/soc/renesas/ra/ra4e1/CMakeLists.txt index e6758812e492e..9bada9b094e99 100644 --- a/soc/renesas/ra/ra4e1/CMakeLists.txt +++ b/soc/renesas/ra/ra4e1/CMakeLists.txt @@ -8,5 +8,6 @@ zephyr_sources( ) zephyr_linker_sources(SECTIONS sections.ld) +zephyr_linker_sources(RAM_SECTIONS ram_sections.ld) set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/renesas/ra/ra4e1/ram_sections.ld b/soc/renesas/ra/ra4e1/ram_sections.ld new file mode 100644 index 0000000000000..18be2a431de2a --- /dev/null +++ b/soc/renesas/ra/ra4e1/ram_sections.ld @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +#ifdef CONFIG_USE_RA_FSP_DTC +SECTION_DATA_PROLOGUE(.fsp_dtc_vector_table,(NOLOAD),) +{ + /* If DTC is used, put the DTC vector table at the start of SRAM. + This avoids memory holes due to 1K alignment required by it. */ + *(.fsp_dtc_vector_table) +} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION) +#endif /* CONFIG_USE_RA_FSP_DTC */ diff --git a/soc/renesas/ra/ra4e1/sections.ld b/soc/renesas/ra/ra4e1/sections.ld index 24f3f69d86c59..89ffbe6fcdff0 100644 --- a/soc/renesas/ra/ra4e1/sections.ld +++ b/soc/renesas/ra/ra4e1/sections.ld @@ -4,80 +4,46 @@ * SPDX-License-Identifier: Apache-2.0 */ -SECTION_DATA_PROLOGUE(.fsp_dtc_vector_table,(NOLOAD),) -{ - /* If DTC is used, put the DTC vector table at the start of SRAM. - This avoids memory holes due to 1K alignment required by it. */ - *(.fsp_dtc_vector_table) -} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION) - -#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_ofs)) +#include -SECTION_PROLOGUE(.option_setting_ofs,,) +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_ofs0)) +SECTION_DATA_PROLOGUE(.option_setting_ofs0,,) { - __OPTION_SETTING_OFS_Start = .; KEEP(*(.option_setting_ofs0)) - . = __OPTION_SETTING_OFS_Start + 0x04; - KEEP(*(.option_setting_ofs2)) - . = __OPTION_SETTING_OFS_Start + 0x10; - KEEP(*(.option_setting_dualsel)) - __OPTION_SETTING_OFS_End = .; -} GROUP_LINK_IN(OPTION_SETTING_OFS) = 0xFF - +} GROUP_LINK_IN(OFS_CONF_MEMORY) #endif -#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_sas)) - -SECTION_PROLOGUE(.option_setting_sas,,) +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_ofs1_sec)) +SECTION_DATA_PROLOGUE(.option_setting_ofs1_sec,,) { - __OPTION_SETTING_SAS_Start = .; - KEEP(*(.option_setting_sas)) - __OPTION_SETTING_SAS_End = .; -} GROUP_LINK_IN(OPTION_SETTING_SAS) = 0xFF + KEEP(*(.option_setting_ofs1_sec)) +} GROUP_LINK_IN(OFS_CONF_MEMORY) +#endif +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_bps_sec)) +SECTION_DATA_PROLOGUE(.option_setting_bps_sec,,) +{ + KEEP(*(.option_setting_bps_sec)) +} GROUP_LINK_IN(OFS_CONF_MEMORY) #endif -#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_s)) +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_pbps_sec)) +SECTION_DATA_PROLOGUE(.option_setting_pbps_sec,,) +{ + KEEP(*(.option_setting_pbps_sec)) +} GROUP_LINK_IN(OFS_CONF_MEMORY) +#endif -SECTION_PROLOGUE(.option_setting_s,,) +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_ofs1_sel)) +SECTION_DATA_PROLOGUE(.option_setting_ofs1_sel,,) { - __OPTION_SETTING_S_Start = .; - KEEP(*(.option_setting_ofs1_sec)) - . = __OPTION_SETTING_S_Start + 0x04; - KEEP(*(.option_setting_ofs3_sec)) - . = __OPTION_SETTING_S_Start + 0x10; - KEEP(*(.option_setting_banksel_sec)) - . = __OPTION_SETTING_S_Start + 0x40; - KEEP(*(.option_setting_bps_sec0)) - . = __OPTION_SETTING_S_Start + 0x44; - KEEP(*(.option_setting_bps_sec1)) - . = __OPTION_SETTING_S_Start + 0x48; - KEEP(*(.option_setting_bps_sec2)) - . = __OPTION_SETTING_S_Start + 0x4C; - KEEP(*(.option_setting_bps_sec3)) - . = __OPTION_SETTING_S_Start + 0x60; - KEEP(*(.option_setting_pbps_sec0)) - . = __OPTION_SETTING_S_Start + 0x64; - KEEP(*(.option_setting_pbps_sec1)) - . = __OPTION_SETTING_S_Start + 0x68; - KEEP(*(.option_setting_pbps_sec2)) - . = __OPTION_SETTING_S_Start + 0x6C; - KEEP(*(.option_setting_pbps_sec3)) - . = __OPTION_SETTING_S_Start + 0x80; KEEP(*(.option_setting_ofs1_sel)) - . = __OPTION_SETTING_S_Start + 0x84; - KEEP(*(.option_setting_ofs3_sel)) - . = __OPTION_SETTING_S_Start + 0x90; - KEEP(*(.option_setting_banksel_sel)) - . = __OPTION_SETTING_S_Start + 0xC0; - KEEP(*(.option_setting_bps_sel0)) - . = __OPTION_SETTING_S_Start + 0xC4; - KEEP(*(.option_setting_bps_sel1)) - . = __OPTION_SETTING_S_Start + 0xC8; - KEEP(*(.option_setting_bps_sel2)) - . = __OPTION_SETTING_S_Start + 0xCC; - KEEP(*(.option_setting_bps_sel3)) - __OPTION_SETTING_S_End = .; -} GROUP_LINK_IN(OPTION_SETTING_S) = 0xFF +} GROUP_LINK_IN(OFS_CONF_MEMORY) +#endif +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_bps_sel)) +SECTION_DATA_PROLOGUE(.option_setting_bps_sel,,) +{ + KEEP(*(.option_setting_bps_sel)) +} GROUP_LINK_IN(OFS_CONF_MEMORY) #endif diff --git a/soc/renesas/ra/ra4e2/CMakeLists.txt b/soc/renesas/ra/ra4e2/CMakeLists.txt index 2020d20561f95..4dc26d6b401ab 100644 --- a/soc/renesas/ra/ra4e2/CMakeLists.txt +++ b/soc/renesas/ra/ra4e2/CMakeLists.txt @@ -15,8 +15,9 @@ if(CONFIG_CMAKE_LINKER_GENERATOR) zephyr_linker_section(NAME .option_setting_bps_sec0 GROUP OPTION_SETTING_S ADDRESS 0x0100a240) zephyr_linker_section(NAME .option_setting_pbps_sec0 GROUP OPTION_SETTING_S ADDRESS 0x0100a260) zephyr_linker_section(NAME .id_code GROUP ID_CODE) -else() - zephyr_linker_sources_ifdef(CONFIG_LD_LINKER_TEMPLATE SECTIONS sections.ld) +elseif(CONFIG_LD_LINKER_TEMPLATE) + zephyr_linker_sources(SECTIONS sections.ld) + zephyr_linker_sources(RAM_SECTIONS ram_sections.ld) endif() set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/renesas/ra/ra4e2/ram_sections.ld b/soc/renesas/ra/ra4e2/ram_sections.ld new file mode 100644 index 0000000000000..18be2a431de2a --- /dev/null +++ b/soc/renesas/ra/ra4e2/ram_sections.ld @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +#ifdef CONFIG_USE_RA_FSP_DTC +SECTION_DATA_PROLOGUE(.fsp_dtc_vector_table,(NOLOAD),) +{ + /* If DTC is used, put the DTC vector table at the start of SRAM. + This avoids memory holes due to 1K alignment required by it. */ + *(.fsp_dtc_vector_table) +} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION) +#endif /* CONFIG_USE_RA_FSP_DTC */ diff --git a/soc/renesas/ra/ra4e2/sections.ld b/soc/renesas/ra/ra4e2/sections.ld index 78c380e9fa183..3d93c59b7e6d5 100644 --- a/soc/renesas/ra/ra4e2/sections.ld +++ b/soc/renesas/ra/ra4e2/sections.ld @@ -1,92 +1,42 @@ /* - * Copyright (c) 2024 Renesas Electronics Corporation + * Copyright (c) 2024-2025 Renesas Electronics Corporation * * SPDX-License-Identifier: Apache-2.0 */ -SECTION_DATA_PROLOGUE(.fsp_dtc_vector_table,(NOLOAD),) -{ - /* If DTC is used, put the DTC vector table at the start of SRAM. - This avoids memory holes due to 1K alignment required by it. */ - *(.fsp_dtc_vector_table) -} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION) - -#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_ofs)) +#include -SECTION_PROLOGUE(.option_setting_ofs,,) +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_ofs0)) +SECTION_DATA_PROLOGUE(.option_setting_ofs0,,) { - __OPTION_SETTING_OFS_Start = .; KEEP(*(.option_setting_ofs0)) - . = __OPTION_SETTING_OFS_Start + 0x04; - KEEP(*(.option_setting_ofs2)) - . = __OPTION_SETTING_OFS_Start + 0x10; - KEEP(*(.option_setting_dualsel)) - __OPTION_SETTING_OFS_End = .; -} GROUP_LINK_IN(OPTION_SETTING_OFS) = 0xFF - +} GROUP_LINK_IN(OFS_CONF_MEMORY) #endif -#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_sas)) - -SECTION_PROLOGUE(.option_setting_sas,,) +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_osis)) +SECTION_DATA_PROLOGUE(.option_setting_osis,,) { - __OPTION_SETTING_SAS_Start = .; - KEEP(*(.option_setting_sas)) - __OPTION_SETTING_SAS_End = .; -} GROUP_LINK_IN(OPTION_SETTING_SAS) = 0xFF - + KEEP(*(.option_setting_osis)) +} GROUP_LINK_IN(OFS_CONF_MEMORY) #endif -#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_s)) - -SECTION_PROLOGUE(.option_setting_s,,) +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_ofs1_sec)) +SECTION_DATA_PROLOGUE(.option_setting_ofs1_sec,,) { - __OPTION_SETTING_S_Start = .; KEEP(*(.option_setting_ofs1_sec)) - . = __OPTION_SETTING_S_Start + 0x04; - KEEP(*(.option_setting_ofs3_sec)) - . = __OPTION_SETTING_S_Start + 0x10; - KEEP(*(.option_setting_banksel_sec)) - . = __OPTION_SETTING_S_Start + 0x40; - KEEP(*(.option_setting_bps_sec0)) - . = __OPTION_SETTING_S_Start + 0x44; - KEEP(*(.option_setting_bps_sec1)) - . = __OPTION_SETTING_S_Start + 0x48; - KEEP(*(.option_setting_bps_sec2)) - . = __OPTION_SETTING_S_Start + 0x4C; - KEEP(*(.option_setting_bps_sec3)) - . = __OPTION_SETTING_S_Start + 0x60; - KEEP(*(.option_setting_pbps_sec0)) - . = __OPTION_SETTING_S_Start + 0x64; - KEEP(*(.option_setting_pbps_sec1)) - . = __OPTION_SETTING_S_Start + 0x68; - KEEP(*(.option_setting_pbps_sec2)) - . = __OPTION_SETTING_S_Start + 0x6C; - KEEP(*(.option_setting_pbps_sec3)) - . = __OPTION_SETTING_S_Start + 0x80; - KEEP(*(.option_setting_ofs1_sel)) - . = __OPTION_SETTING_S_Start + 0x84; - KEEP(*(.option_setting_ofs3_sel)) - . = __OPTION_SETTING_S_Start + 0x90; - KEEP(*(.option_setting_banksel_sel)) - . = __OPTION_SETTING_S_Start + 0xC0; - KEEP(*(.option_setting_bps_sel0)) - . = __OPTION_SETTING_S_Start + 0xC4; - KEEP(*(.option_setting_bps_sel1)) - . = __OPTION_SETTING_S_Start + 0xC8; - KEEP(*(.option_setting_bps_sel2)) - . = __OPTION_SETTING_S_Start + 0xCC; - KEEP(*(.option_setting_bps_sel3)) - __OPTION_SETTING_S_End = .; -} GROUP_LINK_IN(OPTION_SETTING_S) = 0xFF - +} GROUP_LINK_IN(OFS_CONF_MEMORY) #endif -#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(id_code)) - -SECTION_PROLOGUE(.id_code,,) +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_bps_sec)) +SECTION_DATA_PROLOGUE(.option_setting_bps_sec,,) { - KEEP(*(.id_code*)) -} GROUP_LINK_IN(ID_CODE) + KEEP(*(.option_setting_bps_sec)) +} GROUP_LINK_IN(OFS_CONF_MEMORY) +#endif +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_pbps_sec)) +SECTION_DATA_PROLOGUE(.option_setting_pbps_sec,,) +{ + KEEP(*(.option_setting_pbps_sec)) +} GROUP_LINK_IN(OFS_CONF_MEMORY) #endif diff --git a/soc/renesas/ra/ra4l1/CMakeLists.txt b/soc/renesas/ra/ra4l1/CMakeLists.txt index e6758812e492e..9bada9b094e99 100644 --- a/soc/renesas/ra/ra4l1/CMakeLists.txt +++ b/soc/renesas/ra/ra4l1/CMakeLists.txt @@ -8,5 +8,6 @@ zephyr_sources( ) zephyr_linker_sources(SECTIONS sections.ld) +zephyr_linker_sources(RAM_SECTIONS ram_sections.ld) set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/renesas/ra/ra4l1/ram_sections.ld b/soc/renesas/ra/ra4l1/ram_sections.ld new file mode 100644 index 0000000000000..18be2a431de2a --- /dev/null +++ b/soc/renesas/ra/ra4l1/ram_sections.ld @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +#ifdef CONFIG_USE_RA_FSP_DTC +SECTION_DATA_PROLOGUE(.fsp_dtc_vector_table,(NOLOAD),) +{ + /* If DTC is used, put the DTC vector table at the start of SRAM. + This avoids memory holes due to 1K alignment required by it. */ + *(.fsp_dtc_vector_table) +} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION) +#endif /* CONFIG_USE_RA_FSP_DTC */ diff --git a/soc/renesas/ra/ra4l1/sections.ld b/soc/renesas/ra/ra4l1/sections.ld index d9eb2cd4a9a34..74f5ac02b7174 100644 --- a/soc/renesas/ra/ra4l1/sections.ld +++ b/soc/renesas/ra/ra4l1/sections.ld @@ -4,74 +4,67 @@ * SPDX-License-Identifier: Apache-2.0 */ -SECTION_DATA_PROLOGUE(.fsp_dtc_vector_table,(NOLOAD),) -{ - /* If DTC is used, put the DTC vector table at the start of SRAM. - This avoids memory holes due to 1K alignment required by it. */ - *(.fsp_dtc_vector_table) -} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION) +#include -#if DT_NODE_HAS_STATUS(DT_NODELABEL(option_setting_ofs), okay) -SECTION_PROLOGUE(.option_setting_ofs,,) +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_ofs0)) +SECTION_DATA_PROLOGUE(.option_setting_ofs0,,) { - __OPTION_SETTING_OFS_Start = .; KEEP(*(.option_setting_ofs0)) - . = __OPTION_SETTING_OFS_Start + 0x04; - KEEP(*(.option_setting_ofs2)) - . = __OPTION_SETTING_OFS_Start + 0x10; - KEEP(*(.option_setting_dualsel)) - __OPTION_SETTING_OFS_End = .; -} GROUP_LINK_IN(OPTION_SETTING_OFS) = 0xFF +} GROUP_LINK_IN(OFS_CONF_MEMORY) #endif -#if DT_NODE_HAS_STATUS(DT_NODELABEL(option_setting_sas), okay) -SECTION_PROLOGUE(.option_setting_sas,,) +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_dualsel)) +SECTION_DATA_PROLOGUE(.option_setting_dualsel,,) { - __OPTION_SETTING_SAS_Start = .; - KEEP(*(.option_setting_sas)) - __OPTION_SETTING_SAS_End = .; -} GROUP_LINK_IN(OPTION_SETTING_SAS) = 0xFF + KEEP(*(.option_setting_dualsel)) +} GROUP_LINK_IN(OFS_CONF_MEMORY) #endif -#if DT_NODE_HAS_STATUS(DT_NODELABEL(option_setting_s), okay) -SECTION_PROLOGUE(.option_setting_s,,) +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_ofs1_sec)) +SECTION_DATA_PROLOGUE(.option_setting_ofs1_sec,,) { - __OPTION_SETTING_S_Start = .; KEEP(*(.option_setting_ofs1_sec)) - . = __OPTION_SETTING_S_Start + 0x04; - KEEP(*(.option_setting_ofs3_sec)) - . = __OPTION_SETTING_S_Start + 0x10; +} GROUP_LINK_IN(OFS_CONF_MEMORY) +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_banksel_sec)) +SECTION_DATA_PROLOGUE(.option_setting_banksel_sec,,) +{ KEEP(*(.option_setting_banksel_sec)) - . = __OPTION_SETTING_S_Start + 0x40; - KEEP(*(.option_setting_bps_sec0)) - . = __OPTION_SETTING_S_Start + 0x44; - KEEP(*(.option_setting_bps_sec1)) - . = __OPTION_SETTING_S_Start + 0x48; - KEEP(*(.option_setting_bps_sec2)) - . = __OPTION_SETTING_S_Start + 0x4C; - KEEP(*(.option_setting_bps_sec3)) - . = __OPTION_SETTING_S_Start + 0x60; - KEEP(*(.option_setting_pbps_sec0)) - . = __OPTION_SETTING_S_Start + 0x64; - KEEP(*(.option_setting_pbps_sec1)) - . = __OPTION_SETTING_S_Start + 0x68; - KEEP(*(.option_setting_pbps_sec2)) - . = __OPTION_SETTING_S_Start + 0x6C; - KEEP(*(.option_setting_pbps_sec3)) - . = __OPTION_SETTING_S_Start + 0x80; +} GROUP_LINK_IN(OFS_CONF_MEMORY) +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_bps_sec)) +SECTION_DATA_PROLOGUE(.option_setting_bps_sec,,) +{ + KEEP(*(.option_setting_bps_sec)) +} GROUP_LINK_IN(OFS_CONF_MEMORY) +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_pbps_sec)) +SECTION_DATA_PROLOGUE(.option_setting_pbps_sec,,) +{ + KEEP(*(.option_setting_pbps_sec)) +} GROUP_LINK_IN(OFS_CONF_MEMORY) +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_ofs1_sel)) +SECTION_DATA_PROLOGUE(.option_setting_ofs1_sel,,) +{ KEEP(*(.option_setting_ofs1_sel)) - . = __OPTION_SETTING_S_Start + 0x84; - KEEP(*(.option_setting_ofs3_sel)) - . = __OPTION_SETTING_S_Start + 0x90; +} GROUP_LINK_IN(OFS_CONF_MEMORY) +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_banksel_sel)) +SECTION_DATA_PROLOGUE(.option_setting_banksel_sel,,) +{ KEEP(*(.option_setting_banksel_sel)) - . = __OPTION_SETTING_S_Start + 0xC0; - KEEP(*(.option_setting_bps_sel0)) - . = __OPTION_SETTING_S_Start + 0xC4; - KEEP(*(.option_setting_bps_sel1)) - . = __OPTION_SETTING_S_Start + 0xC8; - KEEP(*(.option_setting_bps_sel2)) - . = __OPTION_SETTING_S_Start + 0xCC; - KEEP(*(.option_setting_bps_sel3)) - __OPTION_SETTING_S_End = .; -} GROUP_LINK_IN(OPTION_SETTING_S) = 0xFF +} GROUP_LINK_IN(OFS_CONF_MEMORY) +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_bps_sel)) +SECTION_DATA_PROLOGUE(.option_setting_bps_sel,,) +{ + KEEP(*(.option_setting_bps_sel)) +} GROUP_LINK_IN(OFS_CONF_MEMORY) #endif diff --git a/soc/renesas/ra/ra4m1/CMakeLists.txt b/soc/renesas/ra/ra4m1/CMakeLists.txt index e9637ecd9e69b..43812e3cd7e68 100644 --- a/soc/renesas/ra/ra4m1/CMakeLists.txt +++ b/soc/renesas/ra/ra4m1/CMakeLists.txt @@ -1,4 +1,5 @@ # Copyright (c) 2023 TOKITA Hiroshi +# Copyright (c) 2025 Renesas Electronics Corporation # SPDX-License-Identifier: Apache-2.0 zephyr_include_directories(.) @@ -6,7 +7,6 @@ zephyr_include_directories(.) zephyr_library_sources(soc.c) zephyr_linker_sources(SECTIONS sections.ld) -zephyr_linker_sources(DATA_SECTIONS data_sections.ld) zephyr_linker_sources(RAM_SECTIONS ram_sections.ld) zephyr_linker_sources(ROM_START rom_start.ld) diff --git a/soc/renesas/ra/ra4m1/data_sections.ld b/soc/renesas/ra/ra4m1/data_sections.ld deleted file mode 100644 index 84cb7c088e838..0000000000000 --- a/soc/renesas/ra/ra4m1/data_sections.ld +++ /dev/null @@ -1,13 +0,0 @@ -/* - * Copyright (c) 2024 TOKITA Hiroshi - * - * SPDX-License-Identifier: Apache-2.0 - */ - -.code_in_ram : -{ - . = ALIGN(4); - __Code_In_RAM_Start = .; - KEEP(*(.code_in_ram*)) - __Code_In_RAM_End = .; -} > RAMABLE_REGION diff --git a/soc/renesas/ra/ra4m1/ram_sections.ld b/soc/renesas/ra/ra4m1/ram_sections.ld index 46ad2cc8b9339..ca4598c51305d 100644 --- a/soc/renesas/ra/ra4m1/ram_sections.ld +++ b/soc/renesas/ra/ra4m1/ram_sections.ld @@ -1,12 +1,17 @@ /* * Copyright (c) 2024 TOKITA Hiroshi + * Copyright (c) 2025 Renesas Electronics Corporation * * SPDX-License-Identifier: Apache-2.0 */ +#include + +#ifdef CONFIG_USE_RA_FSP_DTC SECTION_DATA_PROLOGUE(.fsp_dtc_vector_table,(NOLOAD),) { /* If DTC is used, put the DTC vector table at the start of SRAM. This avoids memory holes due to 1K alignment required by it. */ *(.fsp_dtc_vector_table) } GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION) +#endif /* CONFIG_USE_RA_FSP_DTC */ diff --git a/soc/renesas/ra/ra4m1/rom_start.ld b/soc/renesas/ra/ra4m1/rom_start.ld index 64eb3c891e043..14d4ca6737748 100644 --- a/soc/renesas/ra/ra4m1/rom_start.ld +++ b/soc/renesas/ra/ra4m1/rom_start.ld @@ -1,11 +1,17 @@ /* * Copyright (c) 2024 TOKITA Hiroshi + * Copyright (c) 2025 Renesas Electronics Corporation * * SPDX-License-Identifier: Apache-2.0 */ -/* ROM Registers start at address 0x00000400 */ -. = 0x400; -KEEP(*(.rom_registers*)) -/* Reserving 0x100 bytes of space for ROM registers. */ -. = 0x500; +#include + +. = DT_REG_ADDR(DT_NODELABEL(option_setting_ofs0)); +KEEP(*(.option_setting_ofs0)) + +. = DT_REG_ADDR(DT_NODELABEL(option_setting_ofs1)); +KEEP(*(.option_setting_ofs1)) + +. = DT_REG_ADDR(DT_NODELABEL(option_setting_secmpu)); +KEEP(*(.option_setting_secmpu)) diff --git a/soc/renesas/ra/ra4m1/sections.ld b/soc/renesas/ra/ra4m1/sections.ld index 9338be067c817..c866c6ee396e9 100644 --- a/soc/renesas/ra/ra4m1/sections.ld +++ b/soc/renesas/ra/ra4m1/sections.ld @@ -1,116 +1,15 @@ /* * Copyright (c) 2024 TOKITA Hiroshi + * Copyright (c) 2024-2025 Renesas Electronics Corporation * * SPDX-License-Identifier: Apache-2.0 */ -#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(id_code)) +#include -SECTION_PROLOGUE(.id_code,,) +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_osis)) +SECTION_DATA_PROLOGUE(.option_setting_osis,,) { - KEEP(*(.id_code*)) -} GROUP_LINK_IN(ID_CODE) - -#endif - -#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_ofs)) - -SECTION_PROLOGUE(.option_setting_ofs,,) -{ - __OPTION_SETTING_OFS_Start = .; - KEEP(*(.option_setting_ofs0)) - . = __OPTION_SETTING_OFS_Start + 0x04; - KEEP(*(.option_setting_ofs2)) - . = __OPTION_SETTING_OFS_Start + 0x10; - KEEP(*(.option_setting_dualsel)) - __OPTION_SETTING_OFS_End = .; -} GROUP_LINK_IN(OPTION_SETTING_OFS) = 0xFF - -#endif - -#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_sas)) - -SECTION_PROLOGUE(.option_setting_sas,,) -{ - __OPTION_SETTING_SAS_Start = .; - KEEP(*(.option_setting_sas)) - __OPTION_SETTING_SAS_End = .; -} GROUP_LINK_IN(OPTION_SETTING_SAS) = 0xFF - -#endif - -#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_ns)) - -SECTION_PROLOGUE(.option_setting_ns,,) -{ - __OPTION_SETTING_NS_Start = .; - KEEP(*(.option_setting_ofs1)) - . = __OPTION_SETTING_NS_Start + 0x04; - KEEP(*(.option_setting_ofs3)) - . = __OPTION_SETTING_NS_Start + 0x10; - KEEP(*(.option_setting_banksel)) - . = __OPTION_SETTING_NS_Start + 0x40; - KEEP(*(.option_setting_bps0)) - . = __OPTION_SETTING_NS_Start + 0x44; - KEEP(*(.option_setting_bps1)) - . = __OPTION_SETTING_NS_Start + 0x48; - KEEP(*(.option_setting_bps2)) - . = __OPTION_SETTING_NS_Start + 0x4C; - KEEP(*(.option_setting_bps3)) - . = __OPTION_SETTING_NS_Start + 0x60; - KEEP(*(.option_setting_pbps0)) - . = __OPTION_SETTING_NS_Start + 0x64; - KEEP(*(.option_setting_pbps1)) - . = __OPTION_SETTING_NS_Start + 0x68; - KEEP(*(.option_setting_pbps2)) - . = __OPTION_SETTING_NS_Start + 0x6C; - KEEP(*(.option_setting_pbps3)) - __OPTION_SETTING_NS_End = .; -} GROUP_LINK_IN(OPTION_SETTING) = 0xFF - -#endif - -#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_s)) - -SECTION_PROLOGUE(.option_setting_s,,) -{ - __OPTION_SETTING_S_Start = .; - KEEP(*(.option_setting_ofs1_sec)) - . = __OPTION_SETTING_S_Start + 0x04; - KEEP(*(.option_setting_ofs3_sec)) - . = __OPTION_SETTING_S_Start + 0x10; - KEEP(*(.option_setting_banksel_sec)) - . = __OPTION_SETTING_S_Start + 0x40; - KEEP(*(.option_setting_bps_sec0)) - . = __OPTION_SETTING_S_Start + 0x44; - KEEP(*(.option_setting_bps_sec1)) - . = __OPTION_SETTING_S_Start + 0x48; - KEEP(*(.option_setting_bps_sec2)) - . = __OPTION_SETTING_S_Start + 0x4C; - KEEP(*(.option_setting_bps_sec3)) - . = __OPTION_SETTING_S_Start + 0x60; - KEEP(*(.option_setting_pbps_sec0)) - . = __OPTION_SETTING_S_Start + 0x64; - KEEP(*(.option_setting_pbps_sec1)) - . = __OPTION_SETTING_S_Start + 0x68; - KEEP(*(.option_setting_pbps_sec2)) - . = __OPTION_SETTING_S_Start + 0x6C; - KEEP(*(.option_setting_pbps_sec3)) - . = __OPTION_SETTING_S_Start + 0x80; - KEEP(*(.option_setting_ofs1_sel)) - . = __OPTION_SETTING_S_Start + 0x84; - KEEP(*(.option_setting_ofs3_sel)) - . = __OPTION_SETTING_S_Start + 0x90; - KEEP(*(.option_setting_banksel_sel)) - . = __OPTION_SETTING_S_Start + 0xC0; - KEEP(*(.option_setting_bps_sel0)) - . = __OPTION_SETTING_S_Start + 0xC4; - KEEP(*(.option_setting_bps_sel1)) - . = __OPTION_SETTING_S_Start + 0xC8; - KEEP(*(.option_setting_bps_sel2)) - . = __OPTION_SETTING_S_Start + 0xCC; - KEEP(*(.option_setting_bps_sel3)) - __OPTION_SETTING_S_End = .; -} GROUP_LINK_IN(OPTION_SETTING_S) = 0xFF - + KEEP(*(.option_setting_osis)) +} GROUP_LINK_IN(OFS_CONF_MEMORY) #endif diff --git a/soc/renesas/ra/ra4m1/soc.c b/soc/renesas/ra/ra4m1/soc.c index dcdbda4872644..b2dbbd7aae40d 100644 --- a/soc/renesas/ra/ra4m1/soc.c +++ b/soc/renesas/ra/ra4m1/soc.c @@ -37,117 +37,6 @@ LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL); #error "Unsupported HOCO frequency" #endif -struct ofs0_reg { - uint32_t RSVD1: 1; - uint32_t IWDTSTRT: 1; - uint32_t IWDTTOPS: 2; - uint32_t IWDTCKS: 4; - uint32_t IWDTRPES: 2; - uint32_t IWDTRPSS: 2; - uint32_t IWDTRSTIRQS: 1; - uint32_t RSVD2: 1; - uint32_t IWDTSTPCTL: 1; - uint32_t RSVD3: 2; - uint32_t WDTSTRT: 1; - uint32_t WDTTOPS: 2; - uint32_t WDTCKS: 4; - uint32_t WDTRPES: 2; - uint32_t WDTRPSS: 2; - uint32_t WDTRSTIRQS: 1; - uint32_t RSVD4: 1; - uint32_t WDTSTPCTL: 1; - uint32_t RSVD5: 1; -}; - -struct ofs1_reg { - uint32_t RSVD1: 2; - uint32_t LVDAS: 1; - uint32_t VDSEL1: 3; - uint32_t RSVD2: 2; - uint32_t HOCOEN: 1; - uint32_t RSVD3: 3; - uint32_t HOCOFRQ1: 3; - uint32_t RSVD4: 17; -}; - -struct mpu_regs { - uint32_t SECMPUPCSO; - uint32_t SECMPUPCEO; - uint32_t SECMPUPCS1; - uint32_t SECMPUPCE1; - uint32_t SECMPUS0; - uint32_t SECMPUE0; - uint32_t SECMPUS1; - uint32_t SECMPUE1; - uint32_t SECMPUS2; - uint32_t SECMPUE2; - uint32_t SECMPUS3; - uint32_t SECMPUE3; - uint32_t SECMPUAC; -}; - -struct opt_set_mem { - struct ofs0_reg ofs0; - struct ofs1_reg ofs1; - struct mpu_regs mpu; -}; - -#ifdef CONFIG_SOC_OPTION_SETTING_MEMORY -Z_GENERIC_SECTION(".rom_registers") -const struct opt_set_mem ops = { - /* - * Initial settings for watchdog timers. Set all fields to 1, - * disabling watchdog functionality as config options have not - * yet been implemented. - */ - .ofs0 = {.RSVD1 = 0x1, - .IWDTSTRT = 0x1, /* Disable independent watchdog timer */ - .IWDTTOPS = 0x3, - .IWDTCKS = 0xf, - .IWDTRPES = 0x3, - .IWDTRPSS = 0x3, - .IWDTRSTIRQS = 0x1, - .RSVD2 = 0x1, - .IWDTSTPCTL = 0x1, - .RSVD3 = 0x3, - /* Stop watchdog timer following reset */ - .WDTSTRT = !IS_ENABLED(CONFIG_WDT_RENESAS_RA_START_IN_BOOT), - .WDTTOPS = 0x3, - .WDTCKS = 0xf, - .WDTRPES = 0x3, - .WDTRPSS = 0x3, - .WDTRSTIRQS = 0x1, - .RSVD4 = 0x1, - .WDTSTPCTL = 0x1, - .RSVD5 = 0x1}, - .ofs1 = {.RSVD1 = 0x3, - .LVDAS = 0x1, /* Disable voltage monitor 0 following reset */ - .VDSEL1 = 0x3, - .RSVD2 = 0x3, - .HOCOEN = !DT_NODE_HAS_STATUS(DT_PATH(clocks, clock_hoco), okay), - .RSVD3 = 0x7, - .HOCOFRQ1 = OFS1_HOCO_FREQ, - .RSVD4 = 0x1ffff}, - /* - * Initial settings for MPU. Set all areas to maximum values - * essentially disabling MPU functionality as config options - * have not yet been implemented. - */ - .mpu = {.SECMPUPCSO = 0x00fffffc, - .SECMPUPCEO = 0x00ffffff, - .SECMPUPCS1 = 0x00fffffc, - .SECMPUPCE1 = 0x00ffffff, - .SECMPUS0 = 0x00fffffc, - .SECMPUE0 = 0x00ffffff, - .SECMPUS1 = 0x200ffffc, - .SECMPUE1 = 0x200fffff, - .SECMPUS2 = 0x407ffffc, - .SECMPUE2 = 0x407fffff, - .SECMPUS3 = 0x40dffffc, - .SECMPUE3 = 0x40dfffff, - .SECMPUAC = 0xffffffff}}; -#endif - uint32_t SystemCoreClock BSP_SECTION_EARLY_INIT; volatile uint32_t g_protect_pfswe_counter BSP_SECTION_EARLY_INIT; diff --git a/soc/renesas/ra/ra4m2/CMakeLists.txt b/soc/renesas/ra/ra4m2/CMakeLists.txt index 1c7457569ef3e..f8147e8059102 100644 --- a/soc/renesas/ra/ra4m2/CMakeLists.txt +++ b/soc/renesas/ra/ra4m2/CMakeLists.txt @@ -8,5 +8,6 @@ zephyr_sources( ) zephyr_linker_sources(SECTIONS sections.ld) +zephyr_linker_sources(RAM_SECTIONS ram_sections.ld) set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/renesas/ra/ra4m2/ram_sections.ld b/soc/renesas/ra/ra4m2/ram_sections.ld new file mode 100644 index 0000000000000..18be2a431de2a --- /dev/null +++ b/soc/renesas/ra/ra4m2/ram_sections.ld @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +#ifdef CONFIG_USE_RA_FSP_DTC +SECTION_DATA_PROLOGUE(.fsp_dtc_vector_table,(NOLOAD),) +{ + /* If DTC is used, put the DTC vector table at the start of SRAM. + This avoids memory holes due to 1K alignment required by it. */ + *(.fsp_dtc_vector_table) +} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION) +#endif /* CONFIG_USE_RA_FSP_DTC */ diff --git a/soc/renesas/ra/ra4m2/sections.ld b/soc/renesas/ra/ra4m2/sections.ld index 7859d28dea57e..1f13d350905dd 100644 --- a/soc/renesas/ra/ra4m2/sections.ld +++ b/soc/renesas/ra/ra4m2/sections.ld @@ -1,83 +1,49 @@ /* - * Copyright (c) 2024 Renesas Electronics Corporation + * Copyright (c) 2024-2025 Renesas Electronics Corporation * * SPDX-License-Identifier: Apache-2.0 */ -SECTION_DATA_PROLOGUE(.fsp_dtc_vector_table,(NOLOAD),) -{ - /* If DTC is used, put the DTC vector table at the start of SRAM. - This avoids memory holes due to 1K alignment required by it. */ - *(.fsp_dtc_vector_table) -} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION) - -#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_ofs)) +#include -SECTION_PROLOGUE(.option_setting_ofs,,) +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_ofs0)) +SECTION_DATA_PROLOGUE(.option_setting_ofs0,,) { - __OPTION_SETTING_OFS_Start = .; KEEP(*(.option_setting_ofs0)) - . = __OPTION_SETTING_OFS_Start + 0x04; - KEEP(*(.option_setting_ofs2)) - . = __OPTION_SETTING_OFS_Start + 0x10; - KEEP(*(.option_setting_dualsel)) - __OPTION_SETTING_OFS_End = .; -} GROUP_LINK_IN(OPTION_SETTING_OFS) = 0xFF - +} GROUP_LINK_IN(OFS_CONF_MEMORY) #endif -#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_sas)) - -SECTION_PROLOGUE(.option_setting_sas,,) +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_ofs1_sec)) +SECTION_DATA_PROLOGUE(.option_setting_ofs1_sec,,) { - __OPTION_SETTING_SAS_Start = .; - KEEP(*(.option_setting_sas)) - __OPTION_SETTING_SAS_End = .; -} GROUP_LINK_IN(OPTION_SETTING_SAS) = 0xFF + KEEP(*(.option_setting_ofs1_sec)) +} GROUP_LINK_IN(OFS_CONF_MEMORY) +#endif +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_bps_sec)) +SECTION_DATA_PROLOGUE(.option_setting_bps_sec,,) +{ + KEEP(*(.option_setting_bps_sec)) +} GROUP_LINK_IN(OFS_CONF_MEMORY) #endif -#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_s)) +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_pbps_sec)) +SECTION_DATA_PROLOGUE(.option_setting_pbps_sec,,) +{ + KEEP(*(.option_setting_pbps_sec)) +} GROUP_LINK_IN(OFS_CONF_MEMORY) +#endif -SECTION_PROLOGUE(.option_setting_s,,) +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_ofs1_sel)) +SECTION_DATA_PROLOGUE(.option_setting_ofs1_sel,,) { - __OPTION_SETTING_S_Start = .; - KEEP(*(.option_setting_ofs1_sec)) - . = __OPTION_SETTING_S_Start + 0x04; - KEEP(*(.option_setting_ofs3_sec)) - . = __OPTION_SETTING_S_Start + 0x10; - KEEP(*(.option_setting_banksel_sec)) - . = __OPTION_SETTING_S_Start + 0x40; - KEEP(*(.option_setting_bps_sec0)) - . = __OPTION_SETTING_S_Start + 0x44; - KEEP(*(.option_setting_bps_sec1)) - . = __OPTION_SETTING_S_Start + 0x48; - KEEP(*(.option_setting_bps_sec2)) - . = __OPTION_SETTING_S_Start + 0x4C; - KEEP(*(.option_setting_bps_sec3)) - . = __OPTION_SETTING_S_Start + 0x60; - KEEP(*(.option_setting_pbps_sec0)) - . = __OPTION_SETTING_S_Start + 0x64; - KEEP(*(.option_setting_pbps_sec1)) - . = __OPTION_SETTING_S_Start + 0x68; - KEEP(*(.option_setting_pbps_sec2)) - . = __OPTION_SETTING_S_Start + 0x6C; - KEEP(*(.option_setting_pbps_sec3)) - . = __OPTION_SETTING_S_Start + 0x80; KEEP(*(.option_setting_ofs1_sel)) - . = __OPTION_SETTING_S_Start + 0x84; - KEEP(*(.option_setting_ofs3_sel)) - . = __OPTION_SETTING_S_Start + 0x90; - KEEP(*(.option_setting_banksel_sel)) - . = __OPTION_SETTING_S_Start + 0xC0; - KEEP(*(.option_setting_bps_sel0)) - . = __OPTION_SETTING_S_Start + 0xC4; - KEEP(*(.option_setting_bps_sel1)) - . = __OPTION_SETTING_S_Start + 0xC8; - KEEP(*(.option_setting_bps_sel2)) - . = __OPTION_SETTING_S_Start + 0xCC; - KEEP(*(.option_setting_bps_sel3)) - __OPTION_SETTING_S_End = .; -} GROUP_LINK_IN(OPTION_SETTING_S) = 0xFF +} GROUP_LINK_IN(OFS_CONF_MEMORY) +#endif +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_bps_sel)) +SECTION_DATA_PROLOGUE(.option_setting_bps_sel,,) +{ + KEEP(*(.option_setting_bps_sel)) +} GROUP_LINK_IN(OFS_CONF_MEMORY) #endif diff --git a/soc/renesas/ra/ra4m3/CMakeLists.txt b/soc/renesas/ra/ra4m3/CMakeLists.txt index 1c7457569ef3e..f8147e8059102 100644 --- a/soc/renesas/ra/ra4m3/CMakeLists.txt +++ b/soc/renesas/ra/ra4m3/CMakeLists.txt @@ -8,5 +8,6 @@ zephyr_sources( ) zephyr_linker_sources(SECTIONS sections.ld) +zephyr_linker_sources(RAM_SECTIONS ram_sections.ld) set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/renesas/ra/ra4m3/ram_sections.ld b/soc/renesas/ra/ra4m3/ram_sections.ld new file mode 100644 index 0000000000000..18be2a431de2a --- /dev/null +++ b/soc/renesas/ra/ra4m3/ram_sections.ld @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +#ifdef CONFIG_USE_RA_FSP_DTC +SECTION_DATA_PROLOGUE(.fsp_dtc_vector_table,(NOLOAD),) +{ + /* If DTC is used, put the DTC vector table at the start of SRAM. + This avoids memory holes due to 1K alignment required by it. */ + *(.fsp_dtc_vector_table) +} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION) +#endif /* CONFIG_USE_RA_FSP_DTC */ diff --git a/soc/renesas/ra/ra4m3/sections.ld b/soc/renesas/ra/ra4m3/sections.ld index 7859d28dea57e..9db01e471ed0a 100644 --- a/soc/renesas/ra/ra4m3/sections.ld +++ b/soc/renesas/ra/ra4m3/sections.ld @@ -1,83 +1,63 @@ /* - * Copyright (c) 2024 Renesas Electronics Corporation + * Copyright (c) 2024-2025 Renesas Electronics Corporation * * SPDX-License-Identifier: Apache-2.0 */ -SECTION_DATA_PROLOGUE(.fsp_dtc_vector_table,(NOLOAD),) -{ - /* If DTC is used, put the DTC vector table at the start of SRAM. - This avoids memory holes due to 1K alignment required by it. */ - *(.fsp_dtc_vector_table) -} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION) - -#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_ofs)) +#include -SECTION_PROLOGUE(.option_setting_ofs,,) +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_ofs0)) +SECTION_DATA_PROLOGUE(.option_setting_ofs0,,) { - __OPTION_SETTING_OFS_Start = .; KEEP(*(.option_setting_ofs0)) - . = __OPTION_SETTING_OFS_Start + 0x04; - KEEP(*(.option_setting_ofs2)) - . = __OPTION_SETTING_OFS_Start + 0x10; - KEEP(*(.option_setting_dualsel)) - __OPTION_SETTING_OFS_End = .; -} GROUP_LINK_IN(OPTION_SETTING_OFS) = 0xFF - +} GROUP_LINK_IN(OFS_CONF_MEMORY) #endif -#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_sas)) +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_ofs1_sec)) +SECTION_DATA_PROLOGUE(.option_setting_ofs1_sec,,) +{ + KEEP(*(.option_setting_ofs1_sec)) +} GROUP_LINK_IN(OFS_CONF_MEMORY) +#endif -SECTION_PROLOGUE(.option_setting_sas,,) +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_banksel_sec)) +SECTION_DATA_PROLOGUE(.option_setting_banksel_sec,,) { - __OPTION_SETTING_SAS_Start = .; - KEEP(*(.option_setting_sas)) - __OPTION_SETTING_SAS_End = .; -} GROUP_LINK_IN(OPTION_SETTING_SAS) = 0xFF + KEEP(*(.option_setting_banksel_sec)) +} GROUP_LINK_IN(OFS_CONF_MEMORY) +#endif +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_bps_sec)) +SECTION_DATA_PROLOGUE(.option_setting_bps_sec,,) +{ + KEEP(*(.option_setting_bps_sec)) +} GROUP_LINK_IN(OFS_CONF_MEMORY) #endif -#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_s)) +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_pbps_sec)) +SECTION_DATA_PROLOGUE(.option_setting_pbps_sec,,) +{ + KEEP(*(.option_setting_pbps_sec)) +} GROUP_LINK_IN(OFS_CONF_MEMORY) +#endif -SECTION_PROLOGUE(.option_setting_s,,) +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_ofs1_sel)) +SECTION_DATA_PROLOGUE(.option_setting_ofs1_sel,,) { - __OPTION_SETTING_S_Start = .; - KEEP(*(.option_setting_ofs1_sec)) - . = __OPTION_SETTING_S_Start + 0x04; - KEEP(*(.option_setting_ofs3_sec)) - . = __OPTION_SETTING_S_Start + 0x10; - KEEP(*(.option_setting_banksel_sec)) - . = __OPTION_SETTING_S_Start + 0x40; - KEEP(*(.option_setting_bps_sec0)) - . = __OPTION_SETTING_S_Start + 0x44; - KEEP(*(.option_setting_bps_sec1)) - . = __OPTION_SETTING_S_Start + 0x48; - KEEP(*(.option_setting_bps_sec2)) - . = __OPTION_SETTING_S_Start + 0x4C; - KEEP(*(.option_setting_bps_sec3)) - . = __OPTION_SETTING_S_Start + 0x60; - KEEP(*(.option_setting_pbps_sec0)) - . = __OPTION_SETTING_S_Start + 0x64; - KEEP(*(.option_setting_pbps_sec1)) - . = __OPTION_SETTING_S_Start + 0x68; - KEEP(*(.option_setting_pbps_sec2)) - . = __OPTION_SETTING_S_Start + 0x6C; - KEEP(*(.option_setting_pbps_sec3)) - . = __OPTION_SETTING_S_Start + 0x80; KEEP(*(.option_setting_ofs1_sel)) - . = __OPTION_SETTING_S_Start + 0x84; - KEEP(*(.option_setting_ofs3_sel)) - . = __OPTION_SETTING_S_Start + 0x90; +} GROUP_LINK_IN(OFS_CONF_MEMORY) +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_banksel_sel)) +SECTION_DATA_PROLOGUE(.option_setting_banksel_sel,,) +{ KEEP(*(.option_setting_banksel_sel)) - . = __OPTION_SETTING_S_Start + 0xC0; - KEEP(*(.option_setting_bps_sel0)) - . = __OPTION_SETTING_S_Start + 0xC4; - KEEP(*(.option_setting_bps_sel1)) - . = __OPTION_SETTING_S_Start + 0xC8; - KEEP(*(.option_setting_bps_sel2)) - . = __OPTION_SETTING_S_Start + 0xCC; - KEEP(*(.option_setting_bps_sel3)) - __OPTION_SETTING_S_End = .; -} GROUP_LINK_IN(OPTION_SETTING_S) = 0xFF +} GROUP_LINK_IN(OFS_CONF_MEMORY) +#endif +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_bps_sel)) +SECTION_DATA_PROLOGUE(.option_setting_bps_sel,,) +{ + KEEP(*(.option_setting_bps_sel)) +} GROUP_LINK_IN(OFS_CONF_MEMORY) #endif diff --git a/soc/renesas/ra/ra4w1/CMakeLists.txt b/soc/renesas/ra/ra4w1/CMakeLists.txt index ccc5f9899ae8c..6d685a4999652 100644 --- a/soc/renesas/ra/ra4w1/CMakeLists.txt +++ b/soc/renesas/ra/ra4w1/CMakeLists.txt @@ -7,8 +7,9 @@ zephyr_sources( soc.c ) -zephyr_linker_sources(ROM_START opt_set_mem.ld) +zephyr_linker_sources(ROM_START rom_start.ld) zephyr_linker_sources(SECTIONS sections.ld) +zephyr_linker_sources(RAM_SECTIONS ram_sections.ld) set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/renesas/ra/ra4w1/opt_set_mem.ld b/soc/renesas/ra/ra4w1/opt_set_mem.ld deleted file mode 100644 index 07aef9e92d838..0000000000000 --- a/soc/renesas/ra/ra4w1/opt_set_mem.ld +++ /dev/null @@ -1,11 +0,0 @@ -/* - * Copyright (c) 2024 Renesas Electronics Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/* ROM Registers start at address 0x00000400 */ -. = 0x400; -KEEP(*(.rom_registers*)) -/* Reserving 0x100 bytes of space for ROM registers. */ -. = 0x500; diff --git a/soc/renesas/ra/ra4w1/ram_sections.ld b/soc/renesas/ra/ra4w1/ram_sections.ld new file mode 100644 index 0000000000000..18be2a431de2a --- /dev/null +++ b/soc/renesas/ra/ra4w1/ram_sections.ld @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +#ifdef CONFIG_USE_RA_FSP_DTC +SECTION_DATA_PROLOGUE(.fsp_dtc_vector_table,(NOLOAD),) +{ + /* If DTC is used, put the DTC vector table at the start of SRAM. + This avoids memory holes due to 1K alignment required by it. */ + *(.fsp_dtc_vector_table) +} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION) +#endif /* CONFIG_USE_RA_FSP_DTC */ diff --git a/soc/renesas/ra/ra4w1/rom_start.ld b/soc/renesas/ra/ra4w1/rom_start.ld new file mode 100644 index 0000000000000..835fbfe7a949c --- /dev/null +++ b/soc/renesas/ra/ra4w1/rom_start.ld @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2024-2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +. = DT_REG_ADDR(DT_NODELABEL(option_setting_ofs0)); +KEEP(*(.option_setting_ofs0)) + +. = DT_REG_ADDR(DT_NODELABEL(option_setting_ofs1)); +KEEP(*(.option_setting_ofs1)) + +. = DT_REG_ADDR(DT_NODELABEL(option_setting_secmpu)); +KEEP(*(.option_setting_secmpu)) diff --git a/soc/renesas/ra/ra4w1/sections.ld b/soc/renesas/ra/ra4w1/sections.ld index f86dac778f7d2..cfecea7e3433f 100644 --- a/soc/renesas/ra/ra4w1/sections.ld +++ b/soc/renesas/ra/ra4w1/sections.ld @@ -1,29 +1,14 @@ /* - * Copyright (c) 2024 Renesas Electronics Corporation + * Copyright (c) 2024-2025 Renesas Electronics Corporation * * SPDX-License-Identifier: Apache-2.0 */ -.code_in_ram : -{ - . = ALIGN(4); - __Code_In_RAM_Start = .; - KEEP(*(.code_in_ram*)) - __Code_In_RAM_End = .; -} > RAMABLE_REGION +#include -SECTION_DATA_PROLOGUE(.fsp_dtc_vector_table,(NOLOAD),) +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_osis)) +SECTION_DATA_PROLOGUE(.option_setting_osis,,) { - /* If DTC is used, put the DTC vector table at the start of SRAM. - This avoids memory holes due to 1K alignment required by it. */ - *(.fsp_dtc_vector_table) -} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION) - -#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(id_code)) - -SECTION_PROLOGUE(.id_code,,) -{ - KEEP(*(.id_code*)) -} GROUP_LINK_IN(ID_CODE) - + KEEP(*(.option_setting_osis)) +} GROUP_LINK_IN(OFS_CONF_MEMORY) #endif diff --git a/soc/renesas/ra/ra6e1/CMakeLists.txt b/soc/renesas/ra/ra6e1/CMakeLists.txt index 1c7457569ef3e..f8147e8059102 100644 --- a/soc/renesas/ra/ra6e1/CMakeLists.txt +++ b/soc/renesas/ra/ra6e1/CMakeLists.txt @@ -8,5 +8,6 @@ zephyr_sources( ) zephyr_linker_sources(SECTIONS sections.ld) +zephyr_linker_sources(RAM_SECTIONS ram_sections.ld) set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/renesas/ra/ra6e1/ram_sections.ld b/soc/renesas/ra/ra6e1/ram_sections.ld new file mode 100644 index 0000000000000..18be2a431de2a --- /dev/null +++ b/soc/renesas/ra/ra6e1/ram_sections.ld @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +#ifdef CONFIG_USE_RA_FSP_DTC +SECTION_DATA_PROLOGUE(.fsp_dtc_vector_table,(NOLOAD),) +{ + /* If DTC is used, put the DTC vector table at the start of SRAM. + This avoids memory holes due to 1K alignment required by it. */ + *(.fsp_dtc_vector_table) +} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION) +#endif /* CONFIG_USE_RA_FSP_DTC */ diff --git a/soc/renesas/ra/ra6e1/sections.ld b/soc/renesas/ra/ra6e1/sections.ld index 7859d28dea57e..7ae5f0fac2d59 100644 --- a/soc/renesas/ra/ra6e1/sections.ld +++ b/soc/renesas/ra/ra6e1/sections.ld @@ -1,83 +1,70 @@ /* - * Copyright (c) 2024 Renesas Electronics Corporation + * Copyright (c) 2024-2025 Renesas Electronics Corporation * * SPDX-License-Identifier: Apache-2.0 */ -SECTION_DATA_PROLOGUE(.fsp_dtc_vector_table,(NOLOAD),) -{ - /* If DTC is used, put the DTC vector table at the start of SRAM. - This avoids memory holes due to 1K alignment required by it. */ - *(.fsp_dtc_vector_table) -} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION) - -#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_ofs)) +#include -SECTION_PROLOGUE(.option_setting_ofs,,) +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_ofs0)) +SECTION_DATA_PROLOGUE(.option_setting_ofs0,,) { - __OPTION_SETTING_OFS_Start = .; KEEP(*(.option_setting_ofs0)) - . = __OPTION_SETTING_OFS_Start + 0x04; - KEEP(*(.option_setting_ofs2)) - . = __OPTION_SETTING_OFS_Start + 0x10; - KEEP(*(.option_setting_dualsel)) - __OPTION_SETTING_OFS_End = .; -} GROUP_LINK_IN(OPTION_SETTING_OFS) = 0xFF +} GROUP_LINK_IN(OFS_CONF_MEMORY) +#endif +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_dualsel)) +SECTION_DATA_PROLOGUE(.option_setting_dualsel,,) +{ + KEEP(*(.option_setting_dualsel)) +} GROUP_LINK_IN(OFS_CONF_MEMORY) #endif -#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_sas)) +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_ofs1_sec)) +SECTION_DATA_PROLOGUE(.option_setting_ofs1_sec,,) +{ + KEEP(*(.option_setting_ofs1_sec)) +} GROUP_LINK_IN(OFS_CONF_MEMORY) +#endif -SECTION_PROLOGUE(.option_setting_sas,,) +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_banksel_sec)) +SECTION_DATA_PROLOGUE(.option_setting_banksel_sec,,) { - __OPTION_SETTING_SAS_Start = .; - KEEP(*(.option_setting_sas)) - __OPTION_SETTING_SAS_End = .; -} GROUP_LINK_IN(OPTION_SETTING_SAS) = 0xFF + KEEP(*(.option_setting_banksel_sec)) +} GROUP_LINK_IN(OFS_CONF_MEMORY) +#endif +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_bps_sec)) +SECTION_DATA_PROLOGUE(.option_setting_bps_sec,,) +{ + KEEP(*(.option_setting_bps_sec)) +} GROUP_LINK_IN(OFS_CONF_MEMORY) #endif -#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_s)) +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_pbps_sec)) +SECTION_DATA_PROLOGUE(.option_setting_pbps_sec,,) +{ + KEEP(*(.option_setting_pbps_sec)) +} GROUP_LINK_IN(OFS_CONF_MEMORY) +#endif -SECTION_PROLOGUE(.option_setting_s,,) +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_ofs1_sel)) +SECTION_DATA_PROLOGUE(.option_setting_ofs1_sel,,) { - __OPTION_SETTING_S_Start = .; - KEEP(*(.option_setting_ofs1_sec)) - . = __OPTION_SETTING_S_Start + 0x04; - KEEP(*(.option_setting_ofs3_sec)) - . = __OPTION_SETTING_S_Start + 0x10; - KEEP(*(.option_setting_banksel_sec)) - . = __OPTION_SETTING_S_Start + 0x40; - KEEP(*(.option_setting_bps_sec0)) - . = __OPTION_SETTING_S_Start + 0x44; - KEEP(*(.option_setting_bps_sec1)) - . = __OPTION_SETTING_S_Start + 0x48; - KEEP(*(.option_setting_bps_sec2)) - . = __OPTION_SETTING_S_Start + 0x4C; - KEEP(*(.option_setting_bps_sec3)) - . = __OPTION_SETTING_S_Start + 0x60; - KEEP(*(.option_setting_pbps_sec0)) - . = __OPTION_SETTING_S_Start + 0x64; - KEEP(*(.option_setting_pbps_sec1)) - . = __OPTION_SETTING_S_Start + 0x68; - KEEP(*(.option_setting_pbps_sec2)) - . = __OPTION_SETTING_S_Start + 0x6C; - KEEP(*(.option_setting_pbps_sec3)) - . = __OPTION_SETTING_S_Start + 0x80; KEEP(*(.option_setting_ofs1_sel)) - . = __OPTION_SETTING_S_Start + 0x84; - KEEP(*(.option_setting_ofs3_sel)) - . = __OPTION_SETTING_S_Start + 0x90; +} GROUP_LINK_IN(OFS_CONF_MEMORY) +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_banksel_sel)) +SECTION_DATA_PROLOGUE(.option_setting_banksel_sel,,) +{ KEEP(*(.option_setting_banksel_sel)) - . = __OPTION_SETTING_S_Start + 0xC0; - KEEP(*(.option_setting_bps_sel0)) - . = __OPTION_SETTING_S_Start + 0xC4; - KEEP(*(.option_setting_bps_sel1)) - . = __OPTION_SETTING_S_Start + 0xC8; - KEEP(*(.option_setting_bps_sel2)) - . = __OPTION_SETTING_S_Start + 0xCC; - KEEP(*(.option_setting_bps_sel3)) - __OPTION_SETTING_S_End = .; -} GROUP_LINK_IN(OPTION_SETTING_S) = 0xFF +} GROUP_LINK_IN(OFS_CONF_MEMORY) +#endif +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_bps_sel)) +SECTION_DATA_PROLOGUE(.option_setting_bps_sel,,) +{ + KEEP(*(.option_setting_bps_sel)) +} GROUP_LINK_IN(OFS_CONF_MEMORY) #endif diff --git a/soc/renesas/ra/ra6e2/CMakeLists.txt b/soc/renesas/ra/ra6e2/CMakeLists.txt index 1c7457569ef3e..f8147e8059102 100644 --- a/soc/renesas/ra/ra6e2/CMakeLists.txt +++ b/soc/renesas/ra/ra6e2/CMakeLists.txt @@ -8,5 +8,6 @@ zephyr_sources( ) zephyr_linker_sources(SECTIONS sections.ld) +zephyr_linker_sources(RAM_SECTIONS ram_sections.ld) set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/renesas/ra/ra6e2/ram_sections.ld b/soc/renesas/ra/ra6e2/ram_sections.ld new file mode 100644 index 0000000000000..18be2a431de2a --- /dev/null +++ b/soc/renesas/ra/ra6e2/ram_sections.ld @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +#ifdef CONFIG_USE_RA_FSP_DTC +SECTION_DATA_PROLOGUE(.fsp_dtc_vector_table,(NOLOAD),) +{ + /* If DTC is used, put the DTC vector table at the start of SRAM. + This avoids memory holes due to 1K alignment required by it. */ + *(.fsp_dtc_vector_table) +} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION) +#endif /* CONFIG_USE_RA_FSP_DTC */ diff --git a/soc/renesas/ra/ra6e2/sections.ld b/soc/renesas/ra/ra6e2/sections.ld index 78c380e9fa183..e4dba2ff7f0e1 100644 --- a/soc/renesas/ra/ra6e2/sections.ld +++ b/soc/renesas/ra/ra6e2/sections.ld @@ -1,92 +1,43 @@ /* - * Copyright (c) 2024 Renesas Electronics Corporation + * Copyright (c) 2024-2025 Renesas Electronics Corporation * * SPDX-License-Identifier: Apache-2.0 */ -SECTION_DATA_PROLOGUE(.fsp_dtc_vector_table,(NOLOAD),) -{ - /* If DTC is used, put the DTC vector table at the start of SRAM. - This avoids memory holes due to 1K alignment required by it. */ - *(.fsp_dtc_vector_table) -} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION) +#include -#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_ofs)) -SECTION_PROLOGUE(.option_setting_ofs,,) +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_ofs0)) +SECTION_DATA_PROLOGUE(.option_setting_ofs0,,) { - __OPTION_SETTING_OFS_Start = .; KEEP(*(.option_setting_ofs0)) - . = __OPTION_SETTING_OFS_Start + 0x04; - KEEP(*(.option_setting_ofs2)) - . = __OPTION_SETTING_OFS_Start + 0x10; - KEEP(*(.option_setting_dualsel)) - __OPTION_SETTING_OFS_End = .; -} GROUP_LINK_IN(OPTION_SETTING_OFS) = 0xFF - +} GROUP_LINK_IN(OFS_CONF_MEMORY) #endif -#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_sas)) - -SECTION_PROLOGUE(.option_setting_sas,,) +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_osis)) +SECTION_DATA_PROLOGUE(.option_setting_osis,,) { - __OPTION_SETTING_SAS_Start = .; - KEEP(*(.option_setting_sas)) - __OPTION_SETTING_SAS_End = .; -} GROUP_LINK_IN(OPTION_SETTING_SAS) = 0xFF - + KEEP(*(.option_setting_osis)) +} GROUP_LINK_IN(OFS_CONF_MEMORY) #endif -#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_s)) - -SECTION_PROLOGUE(.option_setting_s,,) +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_ofs1_sec)) +SECTION_DATA_PROLOGUE(.option_setting_ofs1_sec,,) { - __OPTION_SETTING_S_Start = .; KEEP(*(.option_setting_ofs1_sec)) - . = __OPTION_SETTING_S_Start + 0x04; - KEEP(*(.option_setting_ofs3_sec)) - . = __OPTION_SETTING_S_Start + 0x10; - KEEP(*(.option_setting_banksel_sec)) - . = __OPTION_SETTING_S_Start + 0x40; - KEEP(*(.option_setting_bps_sec0)) - . = __OPTION_SETTING_S_Start + 0x44; - KEEP(*(.option_setting_bps_sec1)) - . = __OPTION_SETTING_S_Start + 0x48; - KEEP(*(.option_setting_bps_sec2)) - . = __OPTION_SETTING_S_Start + 0x4C; - KEEP(*(.option_setting_bps_sec3)) - . = __OPTION_SETTING_S_Start + 0x60; - KEEP(*(.option_setting_pbps_sec0)) - . = __OPTION_SETTING_S_Start + 0x64; - KEEP(*(.option_setting_pbps_sec1)) - . = __OPTION_SETTING_S_Start + 0x68; - KEEP(*(.option_setting_pbps_sec2)) - . = __OPTION_SETTING_S_Start + 0x6C; - KEEP(*(.option_setting_pbps_sec3)) - . = __OPTION_SETTING_S_Start + 0x80; - KEEP(*(.option_setting_ofs1_sel)) - . = __OPTION_SETTING_S_Start + 0x84; - KEEP(*(.option_setting_ofs3_sel)) - . = __OPTION_SETTING_S_Start + 0x90; - KEEP(*(.option_setting_banksel_sel)) - . = __OPTION_SETTING_S_Start + 0xC0; - KEEP(*(.option_setting_bps_sel0)) - . = __OPTION_SETTING_S_Start + 0xC4; - KEEP(*(.option_setting_bps_sel1)) - . = __OPTION_SETTING_S_Start + 0xC8; - KEEP(*(.option_setting_bps_sel2)) - . = __OPTION_SETTING_S_Start + 0xCC; - KEEP(*(.option_setting_bps_sel3)) - __OPTION_SETTING_S_End = .; -} GROUP_LINK_IN(OPTION_SETTING_S) = 0xFF - +} GROUP_LINK_IN(OFS_CONF_MEMORY) #endif -#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(id_code)) - -SECTION_PROLOGUE(.id_code,,) +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_bps_sec)) +SECTION_DATA_PROLOGUE(.option_setting_bps_sec,,) { - KEEP(*(.id_code*)) -} GROUP_LINK_IN(ID_CODE) + KEEP(*(.option_setting_bps_sec)) +} GROUP_LINK_IN(OFS_CONF_MEMORY) +#endif +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_pbps_sec)) +SECTION_DATA_PROLOGUE(.option_setting_pbps_sec,,) +{ + KEEP(*(.option_setting_pbps_sec)) +} GROUP_LINK_IN(OFS_CONF_MEMORY) #endif diff --git a/soc/renesas/ra/ra6m1/CMakeLists.txt b/soc/renesas/ra/ra6m1/CMakeLists.txt index ccc5f9899ae8c..6d685a4999652 100644 --- a/soc/renesas/ra/ra6m1/CMakeLists.txt +++ b/soc/renesas/ra/ra6m1/CMakeLists.txt @@ -7,8 +7,9 @@ zephyr_sources( soc.c ) -zephyr_linker_sources(ROM_START opt_set_mem.ld) +zephyr_linker_sources(ROM_START rom_start.ld) zephyr_linker_sources(SECTIONS sections.ld) +zephyr_linker_sources(RAM_SECTIONS ram_sections.ld) set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/renesas/ra/ra6m1/opt_set_mem.ld b/soc/renesas/ra/ra6m1/opt_set_mem.ld deleted file mode 100644 index 07aef9e92d838..0000000000000 --- a/soc/renesas/ra/ra6m1/opt_set_mem.ld +++ /dev/null @@ -1,11 +0,0 @@ -/* - * Copyright (c) 2024 Renesas Electronics Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/* ROM Registers start at address 0x00000400 */ -. = 0x400; -KEEP(*(.rom_registers*)) -/* Reserving 0x100 bytes of space for ROM registers. */ -. = 0x500; diff --git a/soc/renesas/ra/ra6m1/ram_sections.ld b/soc/renesas/ra/ra6m1/ram_sections.ld new file mode 100644 index 0000000000000..18be2a431de2a --- /dev/null +++ b/soc/renesas/ra/ra6m1/ram_sections.ld @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +#ifdef CONFIG_USE_RA_FSP_DTC +SECTION_DATA_PROLOGUE(.fsp_dtc_vector_table,(NOLOAD),) +{ + /* If DTC is used, put the DTC vector table at the start of SRAM. + This avoids memory holes due to 1K alignment required by it. */ + *(.fsp_dtc_vector_table) +} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION) +#endif /* CONFIG_USE_RA_FSP_DTC */ diff --git a/soc/renesas/ra/ra6m1/rom_start.ld b/soc/renesas/ra/ra6m1/rom_start.ld new file mode 100644 index 0000000000000..835fbfe7a949c --- /dev/null +++ b/soc/renesas/ra/ra6m1/rom_start.ld @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2024-2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +. = DT_REG_ADDR(DT_NODELABEL(option_setting_ofs0)); +KEEP(*(.option_setting_ofs0)) + +. = DT_REG_ADDR(DT_NODELABEL(option_setting_ofs1)); +KEEP(*(.option_setting_ofs1)) + +. = DT_REG_ADDR(DT_NODELABEL(option_setting_secmpu)); +KEEP(*(.option_setting_secmpu)) diff --git a/soc/renesas/ra/ra6m1/sections.ld b/soc/renesas/ra/ra6m1/sections.ld index fb5ec4d7e24dc..cfecea7e3433f 100644 --- a/soc/renesas/ra/ra6m1/sections.ld +++ b/soc/renesas/ra/ra6m1/sections.ld @@ -1,21 +1,14 @@ /* - * Copyright (c) 2024 Renesas Electronics Corporation + * Copyright (c) 2024-2025 Renesas Electronics Corporation * * SPDX-License-Identifier: Apache-2.0 */ -SECTION_DATA_PROLOGUE(.fsp_dtc_vector_table,(NOLOAD),) -{ - /* If DTC is used, put the DTC vector table at the start of SRAM. - This avoids memory holes due to 1K alignment required by it. */ - *(.fsp_dtc_vector_table) -} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION) - -#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(id_code)) +#include -SECTION_PROLOGUE(.id_code,,) +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_osis)) +SECTION_DATA_PROLOGUE(.option_setting_osis,,) { - KEEP(*(.id_code*)) -} GROUP_LINK_IN(ID_CODE) - + KEEP(*(.option_setting_osis)) +} GROUP_LINK_IN(OFS_CONF_MEMORY) #endif diff --git a/soc/renesas/ra/ra6m2/CMakeLists.txt b/soc/renesas/ra/ra6m2/CMakeLists.txt index ccc5f9899ae8c..6d685a4999652 100644 --- a/soc/renesas/ra/ra6m2/CMakeLists.txt +++ b/soc/renesas/ra/ra6m2/CMakeLists.txt @@ -7,8 +7,9 @@ zephyr_sources( soc.c ) -zephyr_linker_sources(ROM_START opt_set_mem.ld) +zephyr_linker_sources(ROM_START rom_start.ld) zephyr_linker_sources(SECTIONS sections.ld) +zephyr_linker_sources(RAM_SECTIONS ram_sections.ld) set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/renesas/ra/ra6m2/opt_set_mem.ld b/soc/renesas/ra/ra6m2/opt_set_mem.ld deleted file mode 100644 index 07aef9e92d838..0000000000000 --- a/soc/renesas/ra/ra6m2/opt_set_mem.ld +++ /dev/null @@ -1,11 +0,0 @@ -/* - * Copyright (c) 2024 Renesas Electronics Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/* ROM Registers start at address 0x00000400 */ -. = 0x400; -KEEP(*(.rom_registers*)) -/* Reserving 0x100 bytes of space for ROM registers. */ -. = 0x500; diff --git a/soc/renesas/ra/ra6m2/ram_sections.ld b/soc/renesas/ra/ra6m2/ram_sections.ld new file mode 100644 index 0000000000000..18be2a431de2a --- /dev/null +++ b/soc/renesas/ra/ra6m2/ram_sections.ld @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +#ifdef CONFIG_USE_RA_FSP_DTC +SECTION_DATA_PROLOGUE(.fsp_dtc_vector_table,(NOLOAD),) +{ + /* If DTC is used, put the DTC vector table at the start of SRAM. + This avoids memory holes due to 1K alignment required by it. */ + *(.fsp_dtc_vector_table) +} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION) +#endif /* CONFIG_USE_RA_FSP_DTC */ diff --git a/soc/renesas/ra/ra6m2/rom_start.ld b/soc/renesas/ra/ra6m2/rom_start.ld new file mode 100644 index 0000000000000..835fbfe7a949c --- /dev/null +++ b/soc/renesas/ra/ra6m2/rom_start.ld @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2024-2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +. = DT_REG_ADDR(DT_NODELABEL(option_setting_ofs0)); +KEEP(*(.option_setting_ofs0)) + +. = DT_REG_ADDR(DT_NODELABEL(option_setting_ofs1)); +KEEP(*(.option_setting_ofs1)) + +. = DT_REG_ADDR(DT_NODELABEL(option_setting_secmpu)); +KEEP(*(.option_setting_secmpu)) diff --git a/soc/renesas/ra/ra6m2/sections.ld b/soc/renesas/ra/ra6m2/sections.ld index fb5ec4d7e24dc..cfecea7e3433f 100644 --- a/soc/renesas/ra/ra6m2/sections.ld +++ b/soc/renesas/ra/ra6m2/sections.ld @@ -1,21 +1,14 @@ /* - * Copyright (c) 2024 Renesas Electronics Corporation + * Copyright (c) 2024-2025 Renesas Electronics Corporation * * SPDX-License-Identifier: Apache-2.0 */ -SECTION_DATA_PROLOGUE(.fsp_dtc_vector_table,(NOLOAD),) -{ - /* If DTC is used, put the DTC vector table at the start of SRAM. - This avoids memory holes due to 1K alignment required by it. */ - *(.fsp_dtc_vector_table) -} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION) - -#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(id_code)) +#include -SECTION_PROLOGUE(.id_code,,) +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_osis)) +SECTION_DATA_PROLOGUE(.option_setting_osis,,) { - KEEP(*(.id_code*)) -} GROUP_LINK_IN(ID_CODE) - + KEEP(*(.option_setting_osis)) +} GROUP_LINK_IN(OFS_CONF_MEMORY) #endif diff --git a/soc/renesas/ra/ra6m3/CMakeLists.txt b/soc/renesas/ra/ra6m3/CMakeLists.txt index ccc5f9899ae8c..6d685a4999652 100644 --- a/soc/renesas/ra/ra6m3/CMakeLists.txt +++ b/soc/renesas/ra/ra6m3/CMakeLists.txt @@ -7,8 +7,9 @@ zephyr_sources( soc.c ) -zephyr_linker_sources(ROM_START opt_set_mem.ld) +zephyr_linker_sources(ROM_START rom_start.ld) zephyr_linker_sources(SECTIONS sections.ld) +zephyr_linker_sources(RAM_SECTIONS ram_sections.ld) set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/renesas/ra/ra6m3/opt_set_mem.ld b/soc/renesas/ra/ra6m3/opt_set_mem.ld deleted file mode 100644 index 07aef9e92d838..0000000000000 --- a/soc/renesas/ra/ra6m3/opt_set_mem.ld +++ /dev/null @@ -1,11 +0,0 @@ -/* - * Copyright (c) 2024 Renesas Electronics Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/* ROM Registers start at address 0x00000400 */ -. = 0x400; -KEEP(*(.rom_registers*)) -/* Reserving 0x100 bytes of space for ROM registers. */ -. = 0x500; diff --git a/soc/renesas/ra/ra6m3/ram_sections.ld b/soc/renesas/ra/ra6m3/ram_sections.ld new file mode 100644 index 0000000000000..18be2a431de2a --- /dev/null +++ b/soc/renesas/ra/ra6m3/ram_sections.ld @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +#ifdef CONFIG_USE_RA_FSP_DTC +SECTION_DATA_PROLOGUE(.fsp_dtc_vector_table,(NOLOAD),) +{ + /* If DTC is used, put the DTC vector table at the start of SRAM. + This avoids memory holes due to 1K alignment required by it. */ + *(.fsp_dtc_vector_table) +} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION) +#endif /* CONFIG_USE_RA_FSP_DTC */ diff --git a/soc/renesas/ra/ra6m3/rom_start.ld b/soc/renesas/ra/ra6m3/rom_start.ld new file mode 100644 index 0000000000000..835fbfe7a949c --- /dev/null +++ b/soc/renesas/ra/ra6m3/rom_start.ld @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2024-2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +. = DT_REG_ADDR(DT_NODELABEL(option_setting_ofs0)); +KEEP(*(.option_setting_ofs0)) + +. = DT_REG_ADDR(DT_NODELABEL(option_setting_ofs1)); +KEEP(*(.option_setting_ofs1)) + +. = DT_REG_ADDR(DT_NODELABEL(option_setting_secmpu)); +KEEP(*(.option_setting_secmpu)) diff --git a/soc/renesas/ra/ra6m3/sections.ld b/soc/renesas/ra/ra6m3/sections.ld index fb5ec4d7e24dc..cfecea7e3433f 100644 --- a/soc/renesas/ra/ra6m3/sections.ld +++ b/soc/renesas/ra/ra6m3/sections.ld @@ -1,21 +1,14 @@ /* - * Copyright (c) 2024 Renesas Electronics Corporation + * Copyright (c) 2024-2025 Renesas Electronics Corporation * * SPDX-License-Identifier: Apache-2.0 */ -SECTION_DATA_PROLOGUE(.fsp_dtc_vector_table,(NOLOAD),) -{ - /* If DTC is used, put the DTC vector table at the start of SRAM. - This avoids memory holes due to 1K alignment required by it. */ - *(.fsp_dtc_vector_table) -} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION) - -#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(id_code)) +#include -SECTION_PROLOGUE(.id_code,,) +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_osis)) +SECTION_DATA_PROLOGUE(.option_setting_osis,,) { - KEEP(*(.id_code*)) -} GROUP_LINK_IN(ID_CODE) - + KEEP(*(.option_setting_osis)) +} GROUP_LINK_IN(OFS_CONF_MEMORY) #endif diff --git a/soc/renesas/ra/ra6m4/CMakeLists.txt b/soc/renesas/ra/ra6m4/CMakeLists.txt index 1c7457569ef3e..f8147e8059102 100644 --- a/soc/renesas/ra/ra6m4/CMakeLists.txt +++ b/soc/renesas/ra/ra6m4/CMakeLists.txt @@ -8,5 +8,6 @@ zephyr_sources( ) zephyr_linker_sources(SECTIONS sections.ld) +zephyr_linker_sources(RAM_SECTIONS ram_sections.ld) set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/renesas/ra/ra6m4/ram_sections.ld b/soc/renesas/ra/ra6m4/ram_sections.ld new file mode 100644 index 0000000000000..18be2a431de2a --- /dev/null +++ b/soc/renesas/ra/ra6m4/ram_sections.ld @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +#ifdef CONFIG_USE_RA_FSP_DTC +SECTION_DATA_PROLOGUE(.fsp_dtc_vector_table,(NOLOAD),) +{ + /* If DTC is used, put the DTC vector table at the start of SRAM. + This avoids memory holes due to 1K alignment required by it. */ + *(.fsp_dtc_vector_table) +} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION) +#endif /* CONFIG_USE_RA_FSP_DTC */ diff --git a/soc/renesas/ra/ra6m4/sections.ld b/soc/renesas/ra/ra6m4/sections.ld index 7859d28dea57e..7ae5f0fac2d59 100644 --- a/soc/renesas/ra/ra6m4/sections.ld +++ b/soc/renesas/ra/ra6m4/sections.ld @@ -1,83 +1,70 @@ /* - * Copyright (c) 2024 Renesas Electronics Corporation + * Copyright (c) 2024-2025 Renesas Electronics Corporation * * SPDX-License-Identifier: Apache-2.0 */ -SECTION_DATA_PROLOGUE(.fsp_dtc_vector_table,(NOLOAD),) -{ - /* If DTC is used, put the DTC vector table at the start of SRAM. - This avoids memory holes due to 1K alignment required by it. */ - *(.fsp_dtc_vector_table) -} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION) - -#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_ofs)) +#include -SECTION_PROLOGUE(.option_setting_ofs,,) +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_ofs0)) +SECTION_DATA_PROLOGUE(.option_setting_ofs0,,) { - __OPTION_SETTING_OFS_Start = .; KEEP(*(.option_setting_ofs0)) - . = __OPTION_SETTING_OFS_Start + 0x04; - KEEP(*(.option_setting_ofs2)) - . = __OPTION_SETTING_OFS_Start + 0x10; - KEEP(*(.option_setting_dualsel)) - __OPTION_SETTING_OFS_End = .; -} GROUP_LINK_IN(OPTION_SETTING_OFS) = 0xFF +} GROUP_LINK_IN(OFS_CONF_MEMORY) +#endif +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_dualsel)) +SECTION_DATA_PROLOGUE(.option_setting_dualsel,,) +{ + KEEP(*(.option_setting_dualsel)) +} GROUP_LINK_IN(OFS_CONF_MEMORY) #endif -#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_sas)) +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_ofs1_sec)) +SECTION_DATA_PROLOGUE(.option_setting_ofs1_sec,,) +{ + KEEP(*(.option_setting_ofs1_sec)) +} GROUP_LINK_IN(OFS_CONF_MEMORY) +#endif -SECTION_PROLOGUE(.option_setting_sas,,) +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_banksel_sec)) +SECTION_DATA_PROLOGUE(.option_setting_banksel_sec,,) { - __OPTION_SETTING_SAS_Start = .; - KEEP(*(.option_setting_sas)) - __OPTION_SETTING_SAS_End = .; -} GROUP_LINK_IN(OPTION_SETTING_SAS) = 0xFF + KEEP(*(.option_setting_banksel_sec)) +} GROUP_LINK_IN(OFS_CONF_MEMORY) +#endif +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_bps_sec)) +SECTION_DATA_PROLOGUE(.option_setting_bps_sec,,) +{ + KEEP(*(.option_setting_bps_sec)) +} GROUP_LINK_IN(OFS_CONF_MEMORY) #endif -#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_s)) +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_pbps_sec)) +SECTION_DATA_PROLOGUE(.option_setting_pbps_sec,,) +{ + KEEP(*(.option_setting_pbps_sec)) +} GROUP_LINK_IN(OFS_CONF_MEMORY) +#endif -SECTION_PROLOGUE(.option_setting_s,,) +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_ofs1_sel)) +SECTION_DATA_PROLOGUE(.option_setting_ofs1_sel,,) { - __OPTION_SETTING_S_Start = .; - KEEP(*(.option_setting_ofs1_sec)) - . = __OPTION_SETTING_S_Start + 0x04; - KEEP(*(.option_setting_ofs3_sec)) - . = __OPTION_SETTING_S_Start + 0x10; - KEEP(*(.option_setting_banksel_sec)) - . = __OPTION_SETTING_S_Start + 0x40; - KEEP(*(.option_setting_bps_sec0)) - . = __OPTION_SETTING_S_Start + 0x44; - KEEP(*(.option_setting_bps_sec1)) - . = __OPTION_SETTING_S_Start + 0x48; - KEEP(*(.option_setting_bps_sec2)) - . = __OPTION_SETTING_S_Start + 0x4C; - KEEP(*(.option_setting_bps_sec3)) - . = __OPTION_SETTING_S_Start + 0x60; - KEEP(*(.option_setting_pbps_sec0)) - . = __OPTION_SETTING_S_Start + 0x64; - KEEP(*(.option_setting_pbps_sec1)) - . = __OPTION_SETTING_S_Start + 0x68; - KEEP(*(.option_setting_pbps_sec2)) - . = __OPTION_SETTING_S_Start + 0x6C; - KEEP(*(.option_setting_pbps_sec3)) - . = __OPTION_SETTING_S_Start + 0x80; KEEP(*(.option_setting_ofs1_sel)) - . = __OPTION_SETTING_S_Start + 0x84; - KEEP(*(.option_setting_ofs3_sel)) - . = __OPTION_SETTING_S_Start + 0x90; +} GROUP_LINK_IN(OFS_CONF_MEMORY) +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_banksel_sel)) +SECTION_DATA_PROLOGUE(.option_setting_banksel_sel,,) +{ KEEP(*(.option_setting_banksel_sel)) - . = __OPTION_SETTING_S_Start + 0xC0; - KEEP(*(.option_setting_bps_sel0)) - . = __OPTION_SETTING_S_Start + 0xC4; - KEEP(*(.option_setting_bps_sel1)) - . = __OPTION_SETTING_S_Start + 0xC8; - KEEP(*(.option_setting_bps_sel2)) - . = __OPTION_SETTING_S_Start + 0xCC; - KEEP(*(.option_setting_bps_sel3)) - __OPTION_SETTING_S_End = .; -} GROUP_LINK_IN(OPTION_SETTING_S) = 0xFF +} GROUP_LINK_IN(OFS_CONF_MEMORY) +#endif +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_bps_sel)) +SECTION_DATA_PROLOGUE(.option_setting_bps_sel,,) +{ + KEEP(*(.option_setting_bps_sel)) +} GROUP_LINK_IN(OFS_CONF_MEMORY) #endif diff --git a/soc/renesas/ra/ra6m5/CMakeLists.txt b/soc/renesas/ra/ra6m5/CMakeLists.txt index 1c7457569ef3e..f8147e8059102 100644 --- a/soc/renesas/ra/ra6m5/CMakeLists.txt +++ b/soc/renesas/ra/ra6m5/CMakeLists.txt @@ -8,5 +8,6 @@ zephyr_sources( ) zephyr_linker_sources(SECTIONS sections.ld) +zephyr_linker_sources(RAM_SECTIONS ram_sections.ld) set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/renesas/ra/ra6m5/ram_sections.ld b/soc/renesas/ra/ra6m5/ram_sections.ld new file mode 100644 index 0000000000000..18be2a431de2a --- /dev/null +++ b/soc/renesas/ra/ra6m5/ram_sections.ld @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +#ifdef CONFIG_USE_RA_FSP_DTC +SECTION_DATA_PROLOGUE(.fsp_dtc_vector_table,(NOLOAD),) +{ + /* If DTC is used, put the DTC vector table at the start of SRAM. + This avoids memory holes due to 1K alignment required by it. */ + *(.fsp_dtc_vector_table) +} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION) +#endif /* CONFIG_USE_RA_FSP_DTC */ diff --git a/soc/renesas/ra/ra6m5/sections.ld b/soc/renesas/ra/ra6m5/sections.ld index 7859d28dea57e..7ae5f0fac2d59 100644 --- a/soc/renesas/ra/ra6m5/sections.ld +++ b/soc/renesas/ra/ra6m5/sections.ld @@ -1,83 +1,70 @@ /* - * Copyright (c) 2024 Renesas Electronics Corporation + * Copyright (c) 2024-2025 Renesas Electronics Corporation * * SPDX-License-Identifier: Apache-2.0 */ -SECTION_DATA_PROLOGUE(.fsp_dtc_vector_table,(NOLOAD),) -{ - /* If DTC is used, put the DTC vector table at the start of SRAM. - This avoids memory holes due to 1K alignment required by it. */ - *(.fsp_dtc_vector_table) -} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION) - -#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_ofs)) +#include -SECTION_PROLOGUE(.option_setting_ofs,,) +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_ofs0)) +SECTION_DATA_PROLOGUE(.option_setting_ofs0,,) { - __OPTION_SETTING_OFS_Start = .; KEEP(*(.option_setting_ofs0)) - . = __OPTION_SETTING_OFS_Start + 0x04; - KEEP(*(.option_setting_ofs2)) - . = __OPTION_SETTING_OFS_Start + 0x10; - KEEP(*(.option_setting_dualsel)) - __OPTION_SETTING_OFS_End = .; -} GROUP_LINK_IN(OPTION_SETTING_OFS) = 0xFF +} GROUP_LINK_IN(OFS_CONF_MEMORY) +#endif +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_dualsel)) +SECTION_DATA_PROLOGUE(.option_setting_dualsel,,) +{ + KEEP(*(.option_setting_dualsel)) +} GROUP_LINK_IN(OFS_CONF_MEMORY) #endif -#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_sas)) +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_ofs1_sec)) +SECTION_DATA_PROLOGUE(.option_setting_ofs1_sec,,) +{ + KEEP(*(.option_setting_ofs1_sec)) +} GROUP_LINK_IN(OFS_CONF_MEMORY) +#endif -SECTION_PROLOGUE(.option_setting_sas,,) +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_banksel_sec)) +SECTION_DATA_PROLOGUE(.option_setting_banksel_sec,,) { - __OPTION_SETTING_SAS_Start = .; - KEEP(*(.option_setting_sas)) - __OPTION_SETTING_SAS_End = .; -} GROUP_LINK_IN(OPTION_SETTING_SAS) = 0xFF + KEEP(*(.option_setting_banksel_sec)) +} GROUP_LINK_IN(OFS_CONF_MEMORY) +#endif +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_bps_sec)) +SECTION_DATA_PROLOGUE(.option_setting_bps_sec,,) +{ + KEEP(*(.option_setting_bps_sec)) +} GROUP_LINK_IN(OFS_CONF_MEMORY) #endif -#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_s)) +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_pbps_sec)) +SECTION_DATA_PROLOGUE(.option_setting_pbps_sec,,) +{ + KEEP(*(.option_setting_pbps_sec)) +} GROUP_LINK_IN(OFS_CONF_MEMORY) +#endif -SECTION_PROLOGUE(.option_setting_s,,) +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_ofs1_sel)) +SECTION_DATA_PROLOGUE(.option_setting_ofs1_sel,,) { - __OPTION_SETTING_S_Start = .; - KEEP(*(.option_setting_ofs1_sec)) - . = __OPTION_SETTING_S_Start + 0x04; - KEEP(*(.option_setting_ofs3_sec)) - . = __OPTION_SETTING_S_Start + 0x10; - KEEP(*(.option_setting_banksel_sec)) - . = __OPTION_SETTING_S_Start + 0x40; - KEEP(*(.option_setting_bps_sec0)) - . = __OPTION_SETTING_S_Start + 0x44; - KEEP(*(.option_setting_bps_sec1)) - . = __OPTION_SETTING_S_Start + 0x48; - KEEP(*(.option_setting_bps_sec2)) - . = __OPTION_SETTING_S_Start + 0x4C; - KEEP(*(.option_setting_bps_sec3)) - . = __OPTION_SETTING_S_Start + 0x60; - KEEP(*(.option_setting_pbps_sec0)) - . = __OPTION_SETTING_S_Start + 0x64; - KEEP(*(.option_setting_pbps_sec1)) - . = __OPTION_SETTING_S_Start + 0x68; - KEEP(*(.option_setting_pbps_sec2)) - . = __OPTION_SETTING_S_Start + 0x6C; - KEEP(*(.option_setting_pbps_sec3)) - . = __OPTION_SETTING_S_Start + 0x80; KEEP(*(.option_setting_ofs1_sel)) - . = __OPTION_SETTING_S_Start + 0x84; - KEEP(*(.option_setting_ofs3_sel)) - . = __OPTION_SETTING_S_Start + 0x90; +} GROUP_LINK_IN(OFS_CONF_MEMORY) +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_banksel_sel)) +SECTION_DATA_PROLOGUE(.option_setting_banksel_sel,,) +{ KEEP(*(.option_setting_banksel_sel)) - . = __OPTION_SETTING_S_Start + 0xC0; - KEEP(*(.option_setting_bps_sel0)) - . = __OPTION_SETTING_S_Start + 0xC4; - KEEP(*(.option_setting_bps_sel1)) - . = __OPTION_SETTING_S_Start + 0xC8; - KEEP(*(.option_setting_bps_sel2)) - . = __OPTION_SETTING_S_Start + 0xCC; - KEEP(*(.option_setting_bps_sel3)) - __OPTION_SETTING_S_End = .; -} GROUP_LINK_IN(OPTION_SETTING_S) = 0xFF +} GROUP_LINK_IN(OFS_CONF_MEMORY) +#endif +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_bps_sel)) +SECTION_DATA_PROLOGUE(.option_setting_bps_sel,,) +{ + KEEP(*(.option_setting_bps_sel)) +} GROUP_LINK_IN(OFS_CONF_MEMORY) #endif diff --git a/soc/renesas/ra/ra8d1/CMakeLists.txt b/soc/renesas/ra/ra8d1/CMakeLists.txt index d648d3689af46..627bfa4063edc 100644 --- a/soc/renesas/ra/ra8d1/CMakeLists.txt +++ b/soc/renesas/ra/ra8d1/CMakeLists.txt @@ -12,5 +12,6 @@ zephyr_sources_ifdef(CONFIG_PM ) zephyr_linker_sources(SECTIONS sections.ld) +zephyr_linker_sources(RAM_SECTIONS ram_sections.ld) set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/renesas/ra/ra8d1/ram_sections.ld b/soc/renesas/ra/ra8d1/ram_sections.ld new file mode 100644 index 0000000000000..18be2a431de2a --- /dev/null +++ b/soc/renesas/ra/ra8d1/ram_sections.ld @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +#ifdef CONFIG_USE_RA_FSP_DTC +SECTION_DATA_PROLOGUE(.fsp_dtc_vector_table,(NOLOAD),) +{ + /* If DTC is used, put the DTC vector table at the start of SRAM. + This avoids memory holes due to 1K alignment required by it. */ + *(.fsp_dtc_vector_table) +} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION) +#endif /* CONFIG_USE_RA_FSP_DTC */ diff --git a/soc/renesas/ra/ra8d1/sections.ld b/soc/renesas/ra/ra8d1/sections.ld index 7859d28dea57e..ec154061db49d 100644 --- a/soc/renesas/ra/ra8d1/sections.ld +++ b/soc/renesas/ra/ra8d1/sections.ld @@ -1,83 +1,81 @@ /* - * Copyright (c) 2024 Renesas Electronics Corporation + * Copyright (c) 2024-2025 Renesas Electronics Corporation * * SPDX-License-Identifier: Apache-2.0 */ -SECTION_DATA_PROLOGUE(.fsp_dtc_vector_table,(NOLOAD),) -{ - /* If DTC is used, put the DTC vector table at the start of SRAM. - This avoids memory holes due to 1K alignment required by it. */ - *(.fsp_dtc_vector_table) -} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION) +#include -#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_ofs)) +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_ofs_cf_sec)) -SECTION_PROLOGUE(.option_setting_ofs,,) +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_ofs0)) +SECTION_DATA_PROLOGUE(.option_setting_ofs0,,) { - __OPTION_SETTING_OFS_Start = .; KEEP(*(.option_setting_ofs0)) - . = __OPTION_SETTING_OFS_Start + 0x04; +} GROUP_LINK_IN(OFS_CF_SEC_MEMORY) +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_ofs2)) +SECTION_DATA_PROLOGUE(.option_setting_ofs2,,) +{ KEEP(*(.option_setting_ofs2)) - . = __OPTION_SETTING_OFS_Start + 0x10; - KEEP(*(.option_setting_dualsel)) - __OPTION_SETTING_OFS_End = .; -} GROUP_LINK_IN(OPTION_SETTING_OFS) = 0xFF +} GROUP_LINK_IN(OFS_CF_SEC_MEMORY) +#endif +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_dualsel)) +SECTION_DATA_PROLOGUE(.option_setting_dualsel,,) +{ + KEEP(*(.option_setting_dualsel)) +} GROUP_LINK_IN(OFS_CF_SEC_MEMORY) #endif -#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_sas)) +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_ofs1_sec)) +SECTION_DATA_PROLOGUE(.option_setting_ofs1_sec,,) +{ + KEEP(*(.option_setting_ofs1_sec)) +} GROUP_LINK_IN(OFS_CF_SEC_MEMORY) +#endif -SECTION_PROLOGUE(.option_setting_sas,,) +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_banksel_sec)) +SECTION_DATA_PROLOGUE(.option_setting_banksel_sec,,) { - __OPTION_SETTING_SAS_Start = .; - KEEP(*(.option_setting_sas)) - __OPTION_SETTING_SAS_End = .; -} GROUP_LINK_IN(OPTION_SETTING_SAS) = 0xFF + KEEP(*(.option_setting_banksel_sec)) +} GROUP_LINK_IN(OFS_CF_SEC_MEMORY) +#endif +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_bps_sec)) +SECTION_DATA_PROLOGUE(.option_setting_bps_sec,,) +{ + KEEP(*(.option_setting_bps_sec)) +} GROUP_LINK_IN(OFS_CF_SEC_MEMORY) #endif -#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_s)) +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_pbps_sec)) +SECTION_DATA_PROLOGUE(.option_setting_pbps_sec,,) +{ + KEEP(*(.option_setting_pbps_sec)) +} GROUP_LINK_IN(OFS_CF_SEC_MEMORY) +#endif -SECTION_PROLOGUE(.option_setting_s,,) +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_ofs1_sel)) +SECTION_DATA_PROLOGUE(.option_setting_ofs1_sel,,) { - __OPTION_SETTING_S_Start = .; - KEEP(*(.option_setting_ofs1_sec)) - . = __OPTION_SETTING_S_Start + 0x04; - KEEP(*(.option_setting_ofs3_sec)) - . = __OPTION_SETTING_S_Start + 0x10; - KEEP(*(.option_setting_banksel_sec)) - . = __OPTION_SETTING_S_Start + 0x40; - KEEP(*(.option_setting_bps_sec0)) - . = __OPTION_SETTING_S_Start + 0x44; - KEEP(*(.option_setting_bps_sec1)) - . = __OPTION_SETTING_S_Start + 0x48; - KEEP(*(.option_setting_bps_sec2)) - . = __OPTION_SETTING_S_Start + 0x4C; - KEEP(*(.option_setting_bps_sec3)) - . = __OPTION_SETTING_S_Start + 0x60; - KEEP(*(.option_setting_pbps_sec0)) - . = __OPTION_SETTING_S_Start + 0x64; - KEEP(*(.option_setting_pbps_sec1)) - . = __OPTION_SETTING_S_Start + 0x68; - KEEP(*(.option_setting_pbps_sec2)) - . = __OPTION_SETTING_S_Start + 0x6C; - KEEP(*(.option_setting_pbps_sec3)) - . = __OPTION_SETTING_S_Start + 0x80; KEEP(*(.option_setting_ofs1_sel)) - . = __OPTION_SETTING_S_Start + 0x84; - KEEP(*(.option_setting_ofs3_sel)) - . = __OPTION_SETTING_S_Start + 0x90; +} GROUP_LINK_IN(OFS_CF_SEC_MEMORY) +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_banksel_sel)) +SECTION_DATA_PROLOGUE(.option_setting_banksel_sel,,) +{ KEEP(*(.option_setting_banksel_sel)) - . = __OPTION_SETTING_S_Start + 0xC0; - KEEP(*(.option_setting_bps_sel0)) - . = __OPTION_SETTING_S_Start + 0xC4; - KEEP(*(.option_setting_bps_sel1)) - . = __OPTION_SETTING_S_Start + 0xC8; - KEEP(*(.option_setting_bps_sel2)) - . = __OPTION_SETTING_S_Start + 0xCC; - KEEP(*(.option_setting_bps_sel3)) - __OPTION_SETTING_S_End = .; -} GROUP_LINK_IN(OPTION_SETTING_S) = 0xFF +} GROUP_LINK_IN(OFS_CF_SEC_MEMORY) +#endif +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_bps_sel)) +SECTION_DATA_PROLOGUE(.option_setting_bps_sel,,) +{ + KEEP(*(.option_setting_bps_sel)) +} GROUP_LINK_IN(OFS_CF_SEC_MEMORY) #endif + +#endif /* option_setting_ofs_cf_sec */ diff --git a/soc/renesas/ra/ra8m1/CMakeLists.txt b/soc/renesas/ra/ra8m1/CMakeLists.txt index d648d3689af46..627bfa4063edc 100644 --- a/soc/renesas/ra/ra8m1/CMakeLists.txt +++ b/soc/renesas/ra/ra8m1/CMakeLists.txt @@ -12,5 +12,6 @@ zephyr_sources_ifdef(CONFIG_PM ) zephyr_linker_sources(SECTIONS sections.ld) +zephyr_linker_sources(RAM_SECTIONS ram_sections.ld) set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/renesas/ra/ra8m1/ram_sections.ld b/soc/renesas/ra/ra8m1/ram_sections.ld new file mode 100644 index 0000000000000..18be2a431de2a --- /dev/null +++ b/soc/renesas/ra/ra8m1/ram_sections.ld @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +#ifdef CONFIG_USE_RA_FSP_DTC +SECTION_DATA_PROLOGUE(.fsp_dtc_vector_table,(NOLOAD),) +{ + /* If DTC is used, put the DTC vector table at the start of SRAM. + This avoids memory holes due to 1K alignment required by it. */ + *(.fsp_dtc_vector_table) +} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION) +#endif /* CONFIG_USE_RA_FSP_DTC */ diff --git a/soc/renesas/ra/ra8m1/sections.ld b/soc/renesas/ra/ra8m1/sections.ld index 7859d28dea57e..ec154061db49d 100644 --- a/soc/renesas/ra/ra8m1/sections.ld +++ b/soc/renesas/ra/ra8m1/sections.ld @@ -1,83 +1,81 @@ /* - * Copyright (c) 2024 Renesas Electronics Corporation + * Copyright (c) 2024-2025 Renesas Electronics Corporation * * SPDX-License-Identifier: Apache-2.0 */ -SECTION_DATA_PROLOGUE(.fsp_dtc_vector_table,(NOLOAD),) -{ - /* If DTC is used, put the DTC vector table at the start of SRAM. - This avoids memory holes due to 1K alignment required by it. */ - *(.fsp_dtc_vector_table) -} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION) +#include -#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_ofs)) +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_ofs_cf_sec)) -SECTION_PROLOGUE(.option_setting_ofs,,) +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_ofs0)) +SECTION_DATA_PROLOGUE(.option_setting_ofs0,,) { - __OPTION_SETTING_OFS_Start = .; KEEP(*(.option_setting_ofs0)) - . = __OPTION_SETTING_OFS_Start + 0x04; +} GROUP_LINK_IN(OFS_CF_SEC_MEMORY) +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_ofs2)) +SECTION_DATA_PROLOGUE(.option_setting_ofs2,,) +{ KEEP(*(.option_setting_ofs2)) - . = __OPTION_SETTING_OFS_Start + 0x10; - KEEP(*(.option_setting_dualsel)) - __OPTION_SETTING_OFS_End = .; -} GROUP_LINK_IN(OPTION_SETTING_OFS) = 0xFF +} GROUP_LINK_IN(OFS_CF_SEC_MEMORY) +#endif +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_dualsel)) +SECTION_DATA_PROLOGUE(.option_setting_dualsel,,) +{ + KEEP(*(.option_setting_dualsel)) +} GROUP_LINK_IN(OFS_CF_SEC_MEMORY) #endif -#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_sas)) +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_ofs1_sec)) +SECTION_DATA_PROLOGUE(.option_setting_ofs1_sec,,) +{ + KEEP(*(.option_setting_ofs1_sec)) +} GROUP_LINK_IN(OFS_CF_SEC_MEMORY) +#endif -SECTION_PROLOGUE(.option_setting_sas,,) +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_banksel_sec)) +SECTION_DATA_PROLOGUE(.option_setting_banksel_sec,,) { - __OPTION_SETTING_SAS_Start = .; - KEEP(*(.option_setting_sas)) - __OPTION_SETTING_SAS_End = .; -} GROUP_LINK_IN(OPTION_SETTING_SAS) = 0xFF + KEEP(*(.option_setting_banksel_sec)) +} GROUP_LINK_IN(OFS_CF_SEC_MEMORY) +#endif +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_bps_sec)) +SECTION_DATA_PROLOGUE(.option_setting_bps_sec,,) +{ + KEEP(*(.option_setting_bps_sec)) +} GROUP_LINK_IN(OFS_CF_SEC_MEMORY) #endif -#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_s)) +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_pbps_sec)) +SECTION_DATA_PROLOGUE(.option_setting_pbps_sec,,) +{ + KEEP(*(.option_setting_pbps_sec)) +} GROUP_LINK_IN(OFS_CF_SEC_MEMORY) +#endif -SECTION_PROLOGUE(.option_setting_s,,) +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_ofs1_sel)) +SECTION_DATA_PROLOGUE(.option_setting_ofs1_sel,,) { - __OPTION_SETTING_S_Start = .; - KEEP(*(.option_setting_ofs1_sec)) - . = __OPTION_SETTING_S_Start + 0x04; - KEEP(*(.option_setting_ofs3_sec)) - . = __OPTION_SETTING_S_Start + 0x10; - KEEP(*(.option_setting_banksel_sec)) - . = __OPTION_SETTING_S_Start + 0x40; - KEEP(*(.option_setting_bps_sec0)) - . = __OPTION_SETTING_S_Start + 0x44; - KEEP(*(.option_setting_bps_sec1)) - . = __OPTION_SETTING_S_Start + 0x48; - KEEP(*(.option_setting_bps_sec2)) - . = __OPTION_SETTING_S_Start + 0x4C; - KEEP(*(.option_setting_bps_sec3)) - . = __OPTION_SETTING_S_Start + 0x60; - KEEP(*(.option_setting_pbps_sec0)) - . = __OPTION_SETTING_S_Start + 0x64; - KEEP(*(.option_setting_pbps_sec1)) - . = __OPTION_SETTING_S_Start + 0x68; - KEEP(*(.option_setting_pbps_sec2)) - . = __OPTION_SETTING_S_Start + 0x6C; - KEEP(*(.option_setting_pbps_sec3)) - . = __OPTION_SETTING_S_Start + 0x80; KEEP(*(.option_setting_ofs1_sel)) - . = __OPTION_SETTING_S_Start + 0x84; - KEEP(*(.option_setting_ofs3_sel)) - . = __OPTION_SETTING_S_Start + 0x90; +} GROUP_LINK_IN(OFS_CF_SEC_MEMORY) +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_banksel_sel)) +SECTION_DATA_PROLOGUE(.option_setting_banksel_sel,,) +{ KEEP(*(.option_setting_banksel_sel)) - . = __OPTION_SETTING_S_Start + 0xC0; - KEEP(*(.option_setting_bps_sel0)) - . = __OPTION_SETTING_S_Start + 0xC4; - KEEP(*(.option_setting_bps_sel1)) - . = __OPTION_SETTING_S_Start + 0xC8; - KEEP(*(.option_setting_bps_sel2)) - . = __OPTION_SETTING_S_Start + 0xCC; - KEEP(*(.option_setting_bps_sel3)) - __OPTION_SETTING_S_End = .; -} GROUP_LINK_IN(OPTION_SETTING_S) = 0xFF +} GROUP_LINK_IN(OFS_CF_SEC_MEMORY) +#endif +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_bps_sel)) +SECTION_DATA_PROLOGUE(.option_setting_bps_sel,,) +{ + KEEP(*(.option_setting_bps_sel)) +} GROUP_LINK_IN(OFS_CF_SEC_MEMORY) #endif + +#endif /* option_setting_ofs_cf_sec */ diff --git a/soc/renesas/ra/ra8p1/CMakeLists.txt b/soc/renesas/ra/ra8p1/CMakeLists.txt index 89bada919cc4f..7f3c66c46e472 100644 --- a/soc/renesas/ra/ra8p1/CMakeLists.txt +++ b/soc/renesas/ra/ra8p1/CMakeLists.txt @@ -12,5 +12,6 @@ zephyr_sources_ifdef(CONFIG_PM ) zephyr_linker_sources(SECTIONS sections.ld) +zephyr_linker_sources(RAM_SECTIONS ram_sections.ld) set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/renesas/ra/ra8p1/ram_sections.ld b/soc/renesas/ra/ra8p1/ram_sections.ld new file mode 100644 index 0000000000000..18be2a431de2a --- /dev/null +++ b/soc/renesas/ra/ra8p1/ram_sections.ld @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +#ifdef CONFIG_USE_RA_FSP_DTC +SECTION_DATA_PROLOGUE(.fsp_dtc_vector_table,(NOLOAD),) +{ + /* If DTC is used, put the DTC vector table at the start of SRAM. + This avoids memory holes due to 1K alignment required by it. */ + *(.fsp_dtc_vector_table) +} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION) +#endif /* CONFIG_USE_RA_FSP_DTC */ diff --git a/soc/renesas/ra/ra8p1/sections.ld b/soc/renesas/ra/ra8p1/sections.ld index 0bf1291e3fe47..8232b39dede0a 100644 --- a/soc/renesas/ra/ra8p1/sections.ld +++ b/soc/renesas/ra/ra8p1/sections.ld @@ -4,9 +4,75 @@ * SPDX-License-Identifier: Apache-2.0 */ -SECTION_DATA_PROLOGUE(.fsp_dtc_vector_table,(NOLOAD),) +#include + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_ofs_conf_sec)) + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_ofs0)) +SECTION_DATA_PROLOGUE(.option_setting_ofs0,,) +{ + KEEP(*(.option_setting_ofs0)) +} GROUP_LINK_IN(OFS_CONF_SEC_MEMORY) +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_ofs2)) +SECTION_DATA_PROLOGUE(.option_setting_ofs2,,) +{ + KEEP(*(.option_setting_ofs2)) +} GROUP_LINK_IN(OFS_CONF_SEC_MEMORY) +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_sas)) +SECTION_DATA_PROLOGUE(.option_setting_sas,,) { - /* If DTC is used, put the DTC vector table at the start of SRAM. - This avoids memory holes due to 1K alignment required by it. */ - *(.fsp_dtc_vector_table) -} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION) + KEEP(*(.option_setting_sas)) +} GROUP_LINK_IN(OFS_CONF_SEC_MEMORY) +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_ofs1_sec)) +SECTION_DATA_PROLOGUE(.option_setting_ofs1_sec,,) +{ + KEEP(*(.option_setting_ofs1_sec)) +} GROUP_LINK_IN(OFS_CONF_SEC_MEMORY) +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_ofs3_sec)) +SECTION_DATA_PROLOGUE(.option_setting_ofs3_sec,,) +{ + KEEP(*(.option_setting_ofs3_sec)) +} GROUP_LINK_IN(OFS_CONF_SEC_MEMORY) +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_ofs1_sec)) +SECTION_DATA_PROLOGUE(.option_setting_ofs1_sec,,) +{ + KEEP(*(.option_setting_ofs1_sec)) +} GROUP_LINK_IN(OFS_CONF_SEC_MEMORY) +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_ofs3_sec)) +SECTION_DATA_PROLOGUE(.option_setting_ofs3_sec,,) +{ + KEEP(*(.option_setting_ofs3_sec)) +} GROUP_LINK_IN(OFS_CONF_SEC_MEMORY) +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_bps_sec)) +SECTION_DATA_PROLOGUE(.option_setting_bps_sec,,) +{ + KEEP(*(.option_setting_bps_sec)) +} GROUP_LINK_IN(OFS_CONF_SEC_MEMORY) +#endif + +#endif /* option_setting_ofs_conf_sec */ + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_ofs_otp_sec)) + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_otp_pbps_sec)) +SECTION_DATA_PROLOGUE(.option_setting_otp_pbps_sec,,) +{ + KEEP(*(.option_setting_otp_pbps_sec)) +} GROUP_LINK_IN(OFS_OTP_SEC_MEMORY) +#endif + +#endif /* option_setting_ofs_conf_sec */ diff --git a/soc/renesas/ra/ra8t1/CMakeLists.txt b/soc/renesas/ra/ra8t1/CMakeLists.txt index d648d3689af46..627bfa4063edc 100644 --- a/soc/renesas/ra/ra8t1/CMakeLists.txt +++ b/soc/renesas/ra/ra8t1/CMakeLists.txt @@ -12,5 +12,6 @@ zephyr_sources_ifdef(CONFIG_PM ) zephyr_linker_sources(SECTIONS sections.ld) +zephyr_linker_sources(RAM_SECTIONS ram_sections.ld) set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/renesas/ra/ra8t1/ram_sections.ld b/soc/renesas/ra/ra8t1/ram_sections.ld new file mode 100644 index 0000000000000..18be2a431de2a --- /dev/null +++ b/soc/renesas/ra/ra8t1/ram_sections.ld @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +#ifdef CONFIG_USE_RA_FSP_DTC +SECTION_DATA_PROLOGUE(.fsp_dtc_vector_table,(NOLOAD),) +{ + /* If DTC is used, put the DTC vector table at the start of SRAM. + This avoids memory holes due to 1K alignment required by it. */ + *(.fsp_dtc_vector_table) +} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION) +#endif /* CONFIG_USE_RA_FSP_DTC */ diff --git a/soc/renesas/ra/ra8t1/sections.ld b/soc/renesas/ra/ra8t1/sections.ld index 7859d28dea57e..ec154061db49d 100644 --- a/soc/renesas/ra/ra8t1/sections.ld +++ b/soc/renesas/ra/ra8t1/sections.ld @@ -1,83 +1,81 @@ /* - * Copyright (c) 2024 Renesas Electronics Corporation + * Copyright (c) 2024-2025 Renesas Electronics Corporation * * SPDX-License-Identifier: Apache-2.0 */ -SECTION_DATA_PROLOGUE(.fsp_dtc_vector_table,(NOLOAD),) -{ - /* If DTC is used, put the DTC vector table at the start of SRAM. - This avoids memory holes due to 1K alignment required by it. */ - *(.fsp_dtc_vector_table) -} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION) +#include -#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_ofs)) +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_ofs_cf_sec)) -SECTION_PROLOGUE(.option_setting_ofs,,) +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_ofs0)) +SECTION_DATA_PROLOGUE(.option_setting_ofs0,,) { - __OPTION_SETTING_OFS_Start = .; KEEP(*(.option_setting_ofs0)) - . = __OPTION_SETTING_OFS_Start + 0x04; +} GROUP_LINK_IN(OFS_CF_SEC_MEMORY) +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_ofs2)) +SECTION_DATA_PROLOGUE(.option_setting_ofs2,,) +{ KEEP(*(.option_setting_ofs2)) - . = __OPTION_SETTING_OFS_Start + 0x10; - KEEP(*(.option_setting_dualsel)) - __OPTION_SETTING_OFS_End = .; -} GROUP_LINK_IN(OPTION_SETTING_OFS) = 0xFF +} GROUP_LINK_IN(OFS_CF_SEC_MEMORY) +#endif +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_dualsel)) +SECTION_DATA_PROLOGUE(.option_setting_dualsel,,) +{ + KEEP(*(.option_setting_dualsel)) +} GROUP_LINK_IN(OFS_CF_SEC_MEMORY) #endif -#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_sas)) +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_ofs1_sec)) +SECTION_DATA_PROLOGUE(.option_setting_ofs1_sec,,) +{ + KEEP(*(.option_setting_ofs1_sec)) +} GROUP_LINK_IN(OFS_CF_SEC_MEMORY) +#endif -SECTION_PROLOGUE(.option_setting_sas,,) +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_banksel_sec)) +SECTION_DATA_PROLOGUE(.option_setting_banksel_sec,,) { - __OPTION_SETTING_SAS_Start = .; - KEEP(*(.option_setting_sas)) - __OPTION_SETTING_SAS_End = .; -} GROUP_LINK_IN(OPTION_SETTING_SAS) = 0xFF + KEEP(*(.option_setting_banksel_sec)) +} GROUP_LINK_IN(OFS_CF_SEC_MEMORY) +#endif +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_bps_sec)) +SECTION_DATA_PROLOGUE(.option_setting_bps_sec,,) +{ + KEEP(*(.option_setting_bps_sec)) +} GROUP_LINK_IN(OFS_CF_SEC_MEMORY) #endif -#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_s)) +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_pbps_sec)) +SECTION_DATA_PROLOGUE(.option_setting_pbps_sec,,) +{ + KEEP(*(.option_setting_pbps_sec)) +} GROUP_LINK_IN(OFS_CF_SEC_MEMORY) +#endif -SECTION_PROLOGUE(.option_setting_s,,) +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_ofs1_sel)) +SECTION_DATA_PROLOGUE(.option_setting_ofs1_sel,,) { - __OPTION_SETTING_S_Start = .; - KEEP(*(.option_setting_ofs1_sec)) - . = __OPTION_SETTING_S_Start + 0x04; - KEEP(*(.option_setting_ofs3_sec)) - . = __OPTION_SETTING_S_Start + 0x10; - KEEP(*(.option_setting_banksel_sec)) - . = __OPTION_SETTING_S_Start + 0x40; - KEEP(*(.option_setting_bps_sec0)) - . = __OPTION_SETTING_S_Start + 0x44; - KEEP(*(.option_setting_bps_sec1)) - . = __OPTION_SETTING_S_Start + 0x48; - KEEP(*(.option_setting_bps_sec2)) - . = __OPTION_SETTING_S_Start + 0x4C; - KEEP(*(.option_setting_bps_sec3)) - . = __OPTION_SETTING_S_Start + 0x60; - KEEP(*(.option_setting_pbps_sec0)) - . = __OPTION_SETTING_S_Start + 0x64; - KEEP(*(.option_setting_pbps_sec1)) - . = __OPTION_SETTING_S_Start + 0x68; - KEEP(*(.option_setting_pbps_sec2)) - . = __OPTION_SETTING_S_Start + 0x6C; - KEEP(*(.option_setting_pbps_sec3)) - . = __OPTION_SETTING_S_Start + 0x80; KEEP(*(.option_setting_ofs1_sel)) - . = __OPTION_SETTING_S_Start + 0x84; - KEEP(*(.option_setting_ofs3_sel)) - . = __OPTION_SETTING_S_Start + 0x90; +} GROUP_LINK_IN(OFS_CF_SEC_MEMORY) +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_banksel_sel)) +SECTION_DATA_PROLOGUE(.option_setting_banksel_sel,,) +{ KEEP(*(.option_setting_banksel_sel)) - . = __OPTION_SETTING_S_Start + 0xC0; - KEEP(*(.option_setting_bps_sel0)) - . = __OPTION_SETTING_S_Start + 0xC4; - KEEP(*(.option_setting_bps_sel1)) - . = __OPTION_SETTING_S_Start + 0xC8; - KEEP(*(.option_setting_bps_sel2)) - . = __OPTION_SETTING_S_Start + 0xCC; - KEEP(*(.option_setting_bps_sel3)) - __OPTION_SETTING_S_End = .; -} GROUP_LINK_IN(OPTION_SETTING_S) = 0xFF +} GROUP_LINK_IN(OFS_CF_SEC_MEMORY) +#endif +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_bps_sel)) +SECTION_DATA_PROLOGUE(.option_setting_bps_sel,,) +{ + KEEP(*(.option_setting_bps_sel)) +} GROUP_LINK_IN(OFS_CF_SEC_MEMORY) #endif + +#endif /* option_setting_ofs_cf_sec */ diff --git a/tests/drivers/spi/spi_loopback/boards/ek_ra4m1.conf b/tests/drivers/spi/spi_loopback/boards/ek_ra4m1.conf index a231e084368be..054d32bf4a18d 100644 --- a/tests/drivers/spi/spi_loopback/boards/ek_ra4m1.conf +++ b/tests/drivers/spi/spi_loopback/boards/ek_ra4m1.conf @@ -4,3 +4,4 @@ CONFIG_SPI_LOOPBACK_MODE_LOOP=y CONFIG_SPI_INTERRUPT=y CONFIG_SPI_RA_DTC=y +CONFIG_SPI_LARGE_BUFFER_SIZE=4096 diff --git a/west.yml b/west.yml index 3634554334c3a..b70c88a35563a 100644 --- a/west.yml +++ b/west.yml @@ -226,7 +226,7 @@ manifest: - hal - name: hal_renesas path: modules/hal/renesas - revision: 0769fe1520f6c14e6301188588da758a609f181d + revision: pull/119/head groups: - hal - name: hal_rpi_pico