From 5fb3c6899455025824e372f463af305a0e548f8d Mon Sep 17 00:00:00 2001 From: Hieu Nguyen Date: Thu, 10 Jul 2025 17:01:27 +0700 Subject: [PATCH 1/5] manifest: Update commit id for hal_renesas Update commit id for hal_renesas Signed-off-by: Hieu Nguyen Signed-off-by: Tien Nguyen --- west.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/west.yml b/west.yml index fe8253bfa2f2..c12a2c95e171 100644 --- a/west.yml +++ b/west.yml @@ -226,7 +226,7 @@ manifest: - hal - name: hal_renesas path: modules/hal/renesas - revision: 0769fe1520f6c14e6301188588da758a609f181d + revision: pull/118/head groups: - hal - name: hal_rpi_pico From a6957b2667d5a6fff427e9730f5c57d4c4172eee Mon Sep 17 00:00:00 2001 From: Hieu Nguyen Date: Thu, 10 Jul 2025 13:54:45 +0700 Subject: [PATCH 2/5] drivers: pwm: Add PWM support for Renesas RZ/T2M, N2L, V2L Add PWM driver support for Renesas RZ/T2M, N2L, V2L Signed-off-by: Hieu Nguyen Signed-off-by: Tien Nguyen --- drivers/pwm/pwm_renesas_rz_gpt.c | 114 ++++++++++++++++++------------- 1 file changed, 68 insertions(+), 46 deletions(-) diff --git a/drivers/pwm/pwm_renesas_rz_gpt.c b/drivers/pwm/pwm_renesas_rz_gpt.c index faae50c23a0b..0e603d609b27 100644 --- a/drivers/pwm/pwm_renesas_rz_gpt.c +++ b/drivers/pwm/pwm_renesas_rz_gpt.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2024 Renesas Electronics Corporation + * Copyright (c) 2024-2025 Renesas Electronics Corporation * * SPDX-License-Identifier: Apache-2.0 */ @@ -25,6 +25,13 @@ LOG_MODULE_REGISTER(pwm_renesas_rz_gpt, CONFIG_PWM_LOG_LEVEL); #define CAPTURE_BOTH_MODE_FIRST_EVENT_IS_CAPTURE_PULSE 1 #define CAPTURE_BOTH_MODE_SECOND_EVENT_IS_CAPTURE_PERIOD 2 +#define RZ_GPT_GTIOR_OAE_Msk (0x100UL) +#define RZ_GPT_GTIOR_OADFLT_Pos (6UL) +#define RZ_GPT_GTIOR_GTIOA_Pos (0UL) +#define RZ_GPT_GTIOR_GTIOB_Pos (16UL) +#define RZ_GPT_GTIOR_NFAEN_Pos (13UL) +#define RZ_GPT_GTIOR_NFBEN_Pos (29UL) + struct pwm_rz_gpt_capture_data { pwm_capture_callback_handler_t callback; void *user_data; @@ -53,8 +60,8 @@ struct pwm_rz_gpt_config { static uint32_t pwm_rz_gpt_gtior_calculate(gpt_pin_level_t const stop_level) { - /* The stop level is used as both the initial level and the stop level. */ - uint32_t gtior = R_GPT0_GTIOR_OAE_Msk | ((uint32_t)stop_level << R_GPT0_GTIOR_OADFLT_Pos) | + /* The stop level is used as both the initial level and the stop level */ + uint32_t gtior = RZ_GPT_GTIOR_OAE_Msk | ((uint32_t)stop_level << RZ_GPT_GTIOR_OADFLT_Pos) | ((uint32_t)stop_level << GPT_PRV_GTIOR_INITIAL_LEVEL_BIT); uint32_t gtion = GPT_PRV_GTIO_LOW_COMPARE_MATCH_HIGH_CYCLE_END; @@ -69,37 +76,28 @@ static int pwm_rz_gpt_apply_gtior_config(gpt_instance_ctrl_t *const p_ctrl, timer_cfg_t const *const p_cfg) { gpt_extended_cfg_t *p_extend = (gpt_extended_cfg_t *)p_cfg->p_extend; - uint32_t gtior = p_extend->gtior_setting.gtior; + uint32_t gtior = 0; #if GPT_CFG_OUTPUT_SUPPORT_ENABLE - /* Check if custom GTIOR settings are provided. */ - if (p_extend->gtior_setting.gtior == 0) { - /* If custom GTIOR settings are not provided, calculate GTIOR. */ - if (p_extend->gtioca.output_enabled) { - uint32_t gtioca_gtior = - pwm_rz_gpt_gtior_calculate(p_extend->gtioca.stop_level); - gtior |= gtioca_gtior << R_GPT0_GTIOR_GTIOA_Pos; - } + /* Calculate GTIOR */ + if (p_extend->gtioca.output_enabled) { + uint32_t gtioca_gtior = pwm_rz_gpt_gtior_calculate(p_extend->gtioca.stop_level); - if (p_extend->gtiocb.output_enabled) { - uint32_t gtiocb_gtior = - pwm_rz_gpt_gtior_calculate(p_extend->gtiocb.stop_level); - gtior |= gtiocb_gtior << R_GPT0_GTIOR_GTIOB_Pos; - } + gtior |= gtioca_gtior << RZ_GPT_GTIOR_GTIOA_Pos; } -#endif - /* Check if custom GTIOR settings are provided. */ - if (p_extend->gtior_setting.gtior == 0) { - /* - * If custom GTIOR settings are not provided, configure the noise filter for - * the GTIOC pins. - */ - gtior |= (uint32_t)(p_extend->capture_filter_gtioca << R_GPT0_GTIOR_NFAEN_Pos); - gtior |= (uint32_t)(p_extend->capture_filter_gtiocb << R_GPT0_GTIOR_NFBEN_Pos); + if (p_extend->gtiocb.output_enabled) { + uint32_t gtiocb_gtior = pwm_rz_gpt_gtior_calculate(p_extend->gtiocb.stop_level); + + gtior |= gtiocb_gtior << RZ_GPT_GTIOR_GTIOB_Pos; } +#endif + + /* Configure the noise filter for the GTIOC pins */ + gtior |= (uint32_t)(p_extend->capture_filter_gtioca << RZ_GPT_GTIOR_NFAEN_Pos); + gtior |= (uint32_t)(p_extend->capture_filter_gtiocb << RZ_GPT_GTIOR_NFBEN_Pos); - /* Set the I/O control register. */ + /* Set the I/O control register */ p_ctrl->p_reg->GTIOR = gtior; return 0; @@ -115,7 +113,7 @@ static int pwm_rz_gpt_set_cycles(const struct device *dev, uint32_t channel, uin fsp_err_t err; uint32_t pin; - /* gtioca and gtiocb setting */ + /* GTIOCA and GTIOCB setting */ if (channel == RZ_PWM_GPT_IO_A) { pin = GPT_IO_PIN_GTIOCA; fsp_cfg_extend->gtioca.output_enabled = true; @@ -187,12 +185,7 @@ static int pwm_rz_gpt_get_cycles_per_sec(const struct device *dev, uint32_t chan return 0; }; -extern void gpt_capture_a_isr(void); -extern void gpt_capture_b_isr(void); -extern void gpt_counter_overflow_isr(void); - #ifdef CONFIG_PWM_CAPTURE - static int pwm_rz_gpt_configure_capture(const struct device *dev, uint32_t channel, pwm_flags_t flags, pwm_capture_callback_handler_t cb, void *user_data) @@ -546,7 +539,6 @@ static void fsp_callback(timer_callback_args_t *p_args) } } } - #endif /* CONFIG_PWM_CAPTURE */ static DEVICE_API(pwm, pwm_rz_gpt_driver_api) = { @@ -572,10 +564,10 @@ static int pwm_rz_gpt_init(const struct device *dev) return err; } -#if defined(CONFIG_PWM_CAPTURE) +#ifdef CONFIG_PWM_CAPTURE data->fsp_cfg->p_callback = fsp_callback; data->fsp_cfg->p_context = dev; -#endif /* defined(CONFIG_PWM_CAPTURE) */ +#endif /* CONFIG_PWM_CAPTURE */ err = cfg->fsp_api->open(data->fsp_ctrl, data->fsp_cfg); if (err != FSP_SUCCESS) { @@ -591,20 +583,50 @@ static int pwm_rz_gpt_init(const struct device *dev) #define GPT(idx) DT_INST_PARENT(idx) +#ifdef CONFIG_PWM_CAPTURE +extern void gpt_capture_compare_a_isr(void); +extern void gpt_capture_compare_b_isr(void); +extern void gpt_counter_overflow_isr(void); + +static void pwm_rz_gpt_ccmpa_isr(const struct device *dev) +{ + ARG_UNUSED(dev); + gpt_capture_compare_a_isr(); +} + +static void pwm_rz_gpt_ccmpb_isr(const struct device *dev) +{ + ARG_UNUSED(dev); + gpt_capture_compare_b_isr(); +} + +static void pwm_rz_gpt_ovf_isr(const struct device *dev) +{ + ARG_UNUSED(dev); + gpt_counter_overflow_isr(); +} + +#ifdef CONFIG_CPU_CORTEX_M +#define GPT_GET_IRQ_FLAGS(idx, irq_name) 0 +#else /* Cortex-A/R */ +#define GPT_GET_IRQ_FLAGS(idx, irq_name) DT_IRQ_BY_NAME(GPT(idx), irq_name, flags) +#endif + #define PWM_RZ_IRQ_CONFIG_INIT(inst) \ do { \ IRQ_CONNECT(DT_IRQ_BY_NAME(GPT(inst), ccmpa, irq), \ - DT_IRQ_BY_NAME(GPT(inst), ccmpa, priority), gpt_capture_a_isr, NULL, \ - 0); \ + DT_IRQ_BY_NAME(GPT(inst), ccmpa, priority), pwm_rz_gpt_ccmpa_isr, \ + DEVICE_DT_INST_GET(inst), GPT_GET_IRQ_FLAGS(inst, ccmpa)); \ IRQ_CONNECT(DT_IRQ_BY_NAME(GPT(inst), ccmpb, irq), \ - DT_IRQ_BY_NAME(GPT(inst), ccmpb, priority), gpt_capture_b_isr, NULL, \ - 0); \ + DT_IRQ_BY_NAME(GPT(inst), ccmpb, priority), pwm_rz_gpt_ccmpb_isr, \ + DEVICE_DT_INST_GET(inst), GPT_GET_IRQ_FLAGS(inst, ccmpb)); \ IRQ_CONNECT(DT_IRQ_BY_NAME(GPT(inst), ovf, irq), \ - DT_IRQ_BY_NAME(GPT(inst), ovf, priority), gpt_counter_overflow_isr, \ - NULL, 0); \ + DT_IRQ_BY_NAME(GPT(inst), ovf, priority), pwm_rz_gpt_ovf_isr, \ + DEVICE_DT_INST_GET(inst), GPT_GET_IRQ_FLAGS(inst, ovf)); \ } while (0) +#endif /* CONFIG_PWM_CAPTURE */ -#define PWM_RZG_INIT(inst) \ +#define PWM_RZ_INIT(inst) \ PINCTRL_DT_INST_DEFINE(inst); \ static gpt_instance_ctrl_t g_timer##inst##_ctrl; \ static gpt_extended_cfg_t g_timer##inst##_extend = { \ @@ -632,7 +654,6 @@ static int pwm_rz_gpt_init(const struct device *dev) .capture_filter_gtioca = GPT_CAPTURE_FILTER_NONE, \ .capture_filter_gtiocb = GPT_CAPTURE_FILTER_NONE, \ .p_pwm_cfg = NULL, \ - .gtior_setting.gtior = (0x0U), \ }; \ static timer_cfg_t g_timer##inst##_cfg = { \ .mode = TIMER_MODE_PWM, \ @@ -650,7 +671,8 @@ static int pwm_rz_gpt_init(const struct device *dev) .fsp_cfg = &g_timer##inst##_cfg, .fsp_ctrl = &g_timer##inst##_ctrl}; \ static int pwm_rz_gpt_init_##inst(const struct device *dev) \ { \ - PWM_RZ_IRQ_CONFIG_INIT(inst); \ + IF_ENABLED(CONFIG_PWM_CAPTURE, \ + (PWM_RZ_IRQ_CONFIG_INIT(inst);)) \ int err = pwm_rz_gpt_init(dev); \ if (err != 0) { \ return err; \ @@ -661,4 +683,4 @@ static int pwm_rz_gpt_init(const struct device *dev) &pwm_rz_gpt_config_##inst, POST_KERNEL, CONFIG_PWM_INIT_PRIORITY, \ &pwm_rz_gpt_driver_api); -DT_INST_FOREACH_STATUS_OKAY(PWM_RZG_INIT); +DT_INST_FOREACH_STATUS_OKAY(PWM_RZ_INIT); From 1a5e91e60bbd9326f51ff5756ff39153e0447636 Mon Sep 17 00:00:00 2001 From: Hieu Nguyen Date: Thu, 10 Jul 2025 13:56:50 +0700 Subject: [PATCH 3/5] dts: renesas: Add PWM support for Renesas RZ/T2M, N2L, V2L Add GPT nodes to Renesas RZ/T2M, N2L, V2L Signed-off-by: Hieu Nguyen Signed-off-by: Tien Nguyen --- dts/arm/renesas/rz/rzn/r9a07g084.dtsi | 446 ++++++++++++++++++++++++++ dts/arm/renesas/rz/rzt/r9a07g075.dtsi | 446 ++++++++++++++++++++++++++ dts/arm/renesas/rz/rzv/r9a07g054.dtsi | 144 +++++++++ 3 files changed, 1036 insertions(+) diff --git a/dts/arm/renesas/rz/rzn/r9a07g084.dtsi b/dts/arm/renesas/rz/rzn/r9a07g084.dtsi index 91330455337d..920f3a826210 100644 --- a/dts/arm/renesas/rz/rzn/r9a07g084.dtsi +++ b/dts/arm/renesas/rz/rzn/r9a07g084.dtsi @@ -588,5 +588,451 @@ status = "disabled"; }; }; + + gpt0: gpt0@90002000 { + compatible = "renesas,rz-gpt"; + reg = <0x90002000 0x100>; + channel = <0>; + interrupts = , + , + , + , + , + , + , + , + ; + interrupt-names = "ccmpa", "ccmpb", "cmpc", "cmpd", "cmpe", + "cmpf", "ovf", "udf", "dte"; + prescaler = <1>; + status = "disabled"; + + pwm { + compatible = "renesas,rz-gpt-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + }; + + gpt1: gpt1@90002100 { + compatible = "renesas,rz-gpt"; + reg = <0x90002100 0x100>; + channel = <1>; + interrupts = , + , + , + , + , + , + , + , + ; + interrupt-names = "ccmpa", "ccmpb", "cmpc", "cmpd", "cmpe", + "cmpf", "ovf", "udf", "dte"; + prescaler = <1>; + status = "disabled"; + + pwm { + compatible = "renesas,rz-gpt-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + }; + + gpt2: gpt2@90002200 { + compatible = "renesas,rz-gpt"; + reg = <0x90002200 0x100>; + channel = <2>; + interrupts = , + , + , + , + , + , + , + , + ; + interrupt-names = "ccmpa", "ccmpb", "cmpc", "cmpd", "cmpe", + "cmpf", "ovf", "udf", "dte"; + prescaler = <1>; + status = "disabled"; + + pwm { + compatible = "renesas,rz-gpt-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + }; + + gpt3: gpt3@90002300 { + compatible = "renesas,rz-gpt"; + reg = <0x90002300 0x100>; + channel = <3>; + interrupts = , + , + , + , + , + , + , + , + ; + interrupt-names = "ccmpa", "ccmpb", "cmpc", "cmpd", "cmpe", + "cmpf", "ovf", "udf", "dte"; + prescaler = <1>; + status = "disabled"; + + pwm { + compatible = "renesas,rz-gpt-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + }; + + gpt4: gpt4@90002400 { + compatible = "renesas,rz-gpt"; + reg = <0x90002400 0x100>; + channel = <4>; + interrupts = , + , + , + , + , + , + , + , + ; + interrupt-names = "ccmpa", "ccmpb", "cmpc", "cmpd", "cmpe", + "cmpf", "ovf", "udf", "dte"; + prescaler = <1>; + status = "disabled"; + + pwm { + compatible = "renesas,rz-gpt-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + }; + + gpt5: gpt5@90002500 { + compatible = "renesas,rz-gpt"; + reg = <0x90002500 0x100>; + channel = <5>; + interrupts = , + , + , + , + , + , + , + , + ; + interrupt-names = "ccmpa", "ccmpb", "cmpc", "cmpd", "cmpe", + "cmpf", "ovf", "udf", "dte"; + prescaler = <1>; + status = "disabled"; + + pwm { + compatible = "renesas,rz-gpt-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + }; + + gpt6: gpt6@90002600 { + compatible = "renesas,rz-gpt"; + reg = <0x90002600 0x100>; + channel = <6>; + interrupts = , + , + , + , + , + , + , + , + ; + interrupt-names = "ccmpa", "ccmpb", "cmpc", "cmpd", "cmpe", + "cmpf", "ovf", "udf", "dte"; + prescaler = <1>; + status = "disabled"; + + pwm { + compatible = "renesas,rz-gpt-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + }; + + gpt7: gpt7@80000000 { + compatible = "renesas,rz-gpt"; + reg = <0x80000000 0x100>; + channel = <7>; + interrupts = , + , + , + , + , + , + , + , + ; + interrupt-names = "ccmpa", "ccmpb", "cmpc", "cmpd", "cmpe", + "cmpf", "ovf", "udf", "dte"; + prescaler = <1>; + status = "disabled"; + + pwm { + compatible = "renesas,rz-gpt-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + }; + + gpt8: gpt8@80000100 { + compatible = "renesas,rz-gpt"; + reg = <0x80000100 0x100>; + channel = <8>; + interrupts = , + , + , + , + , + , + , + , + ; + interrupt-names = "ccmpa", "ccmpb", "cmpc", "cmpd", "cmpe", + "cmpf", "ovf", "udf", "dte"; + prescaler = <1>; + status = "disabled"; + + pwm { + compatible = "renesas,rz-gpt-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + }; + + gpt9: gpt9@80000200 { + compatible = "renesas,rz-gpt"; + reg = <0x80000200 0x100>; + channel = <9>; + interrupts = , + , + , + , + , + , + , + , + ; + interrupt-names = "ccmpa", "ccmpb", "cmpc", "cmpd", "cmpe", + "cmpf", "ovf", "udf", "dte"; + prescaler = <1>; + status = "disabled"; + + pwm { + compatible = "renesas,rz-gpt-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + }; + + gpt10: gpt10@80000300 { + compatible = "renesas,rz-gpt"; + reg = <0x80000300 0x100>; + channel = <10>; + interrupts = , + , + , + , + , + , + , + , + ; + interrupt-names = "ccmpa", "ccmpb", "cmpc", "cmpd", "cmpe", + "cmpf", "ovf", "udf", "dte"; + prescaler = <1>; + status = "disabled"; + + pwm { + compatible = "renesas,rz-gpt-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + }; + + gpt11: gpt11@80000400 { + compatible = "renesas,rz-gpt"; + reg = <0x80000400 0x100>; + channel = <11>; + interrupts = , + , + , + , + , + , + , + , + ; + interrupt-names = "ccmpa", "ccmpb", "cmpc", "cmpd", "cmpe", + "cmpf", "ovf", "udf", "dte"; + prescaler = <1>; + status = "disabled"; + + pwm { + compatible = "renesas,rz-gpt-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + }; + + gpt12: gpt12@80000500 { + compatible = "renesas,rz-gpt"; + reg = <0x80000500 0x100>; + channel = <12>; + interrupts = , + , + , + , + , + , + , + , + ; + interrupt-names = "ccmpa", "ccmpb", "cmpc", "cmpd", "cmpe", + "cmpf", "ovf", "udf", "dte"; + prescaler = <1>; + status = "disabled"; + + pwm { + compatible = "renesas,rz-gpt-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + }; + + gpt13: gpt13@80000600 { + compatible = "renesas,rz-gpt"; + reg = <0x80000600 0x100>; + channel = <13>; + interrupts = , + , + , + , + , + , + , + , + ; + interrupt-names = "ccmpa", "ccmpb", "cmpc", "cmpd", "cmpe", + "cmpf", "ovf", "udf", "dte"; + prescaler = <1>; + status = "disabled"; + + pwm { + compatible = "renesas,rz-gpt-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + }; + + gpt14: gpt14@81000000 { + compatible = "renesas,rz-gpt"; + reg = <0x81000000 0x100>; + channel = <14>; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "ccmpa", "ccmpb", "cmpc", "cmpd", "cmpe", + "cmpf", "ovf", "udf"; + prescaler = <1>; + status = "disabled"; + + pwm { + compatible = "renesas,rz-gpt-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + }; + + gpt15: gpt15@81000100 { + compatible = "renesas,rz-gpt"; + reg = <0x81000100 0x100>; + channel = <15>; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "ccmpa", "ccmpb", "cmpc", "cmpd", "cmpe", + "cmpf", "ovf", "udf"; + prescaler = <1>; + status = "disabled"; + + pwm { + compatible = "renesas,rz-gpt-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + }; + + gpt16: gpt16@81000200 { + compatible = "renesas,rz-gpt"; + reg = <0x81000200 0x100>; + channel = <16>; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "ccmpa", "ccmpb", "cmpc", "cmpd", "cmpe", + "cmpf", "ovf", "udf"; + prescaler = <1>; + status = "disabled"; + + pwm { + compatible = "renesas,rz-gpt-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + }; + + gpt17: gpt17@81000300 { + compatible = "renesas,rz-gpt"; + reg = <0x81000300 0x100>; + channel = <17>; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "ccmpa", "ccmpb", "cmpc", "cmpd", "cmpe", + "cmpf", "ovf", "udf"; + prescaler = <1>; + status = "disabled"; + + pwm { + compatible = "renesas,rz-gpt-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + }; }; }; diff --git a/dts/arm/renesas/rz/rzt/r9a07g075.dtsi b/dts/arm/renesas/rz/rzt/r9a07g075.dtsi index 209238629d0d..67f28e51c310 100644 --- a/dts/arm/renesas/rz/rzt/r9a07g075.dtsi +++ b/dts/arm/renesas/rz/rzt/r9a07g075.dtsi @@ -586,5 +586,451 @@ status = "disabled"; }; }; + + gpt0: gpt0@90002000 { + compatible = "renesas,rz-gpt"; + reg = <0x90002000 0x100>; + channel = <0>; + interrupts = , + , + , + , + , + , + , + , + ; + interrupt-names = "ccmpa", "ccmpb", "cmpc", "cmpd", "cmpe", + "cmpf", "ovf", "udf", "dte"; + prescaler = <1>; + status = "disabled"; + + pwm { + compatible = "renesas,rz-gpt-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + }; + + gpt1: gpt1@90002100 { + compatible = "renesas,rz-gpt"; + reg = <0x90002100 0x100>; + channel = <1>; + interrupts = , + , + , + , + , + , + , + , + ; + interrupt-names = "ccmpa", "ccmpb", "cmpc", "cmpd", "cmpe", + "cmpf", "ovf", "udf", "dte"; + prescaler = <1>; + status = "disabled"; + + pwm { + compatible = "renesas,rz-gpt-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + }; + + gpt2: gpt2@90002200 { + compatible = "renesas,rz-gpt"; + reg = <0x90002200 0x100>; + channel = <2>; + interrupts = , + , + , + , + , + , + , + , + ; + interrupt-names = "ccmpa", "ccmpb", "cmpc", "cmpd", "cmpe", + "cmpf", "ovf", "udf", "dte"; + prescaler = <1>; + status = "disabled"; + + pwm { + compatible = "renesas,rz-gpt-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + }; + + gpt3: gpt3@90002300 { + compatible = "renesas,rz-gpt"; + reg = <0x90002300 0x100>; + channel = <3>; + interrupts = , + , + , + , + , + , + , + , + ; + interrupt-names = "ccmpa", "ccmpb", "cmpc", "cmpd", "cmpe", + "cmpf", "ovf", "udf", "dte"; + prescaler = <1>; + status = "disabled"; + + pwm { + compatible = "renesas,rz-gpt-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + }; + + gpt4: gpt4@90002400 { + compatible = "renesas,rz-gpt"; + reg = <0x90002400 0x100>; + channel = <4>; + interrupts = , + , + , + , + , + , + , + , + ; + interrupt-names = "ccmpa", "ccmpb", "cmpc", "cmpd", "cmpe", + "cmpf", "ovf", "udf", "dte"; + prescaler = <1>; + status = "disabled"; + + pwm { + compatible = "renesas,rz-gpt-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + }; + + gpt5: gpt5@90002500 { + compatible = "renesas,rz-gpt"; + reg = <0x90002500 0x100>; + channel = <5>; + interrupts = , + , + , + , + , + , + , + , + ; + interrupt-names = "ccmpa", "ccmpb", "cmpc", "cmpd", "cmpe", + "cmpf", "ovf", "udf", "dte"; + prescaler = <1>; + status = "disabled"; + + pwm { + compatible = "renesas,rz-gpt-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + }; + + gpt6: gpt6@90002600 { + compatible = "renesas,rz-gpt"; + reg = <0x90002600 0x100>; + channel = <6>; + interrupts = , + , + , + , + , + , + , + , + ; + interrupt-names = "ccmpa", "ccmpb", "cmpc", "cmpd", "cmpe", + "cmpf", "ovf", "udf", "dte"; + prescaler = <1>; + status = "disabled"; + + pwm { + compatible = "renesas,rz-gpt-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + }; + + gpt7: gpt7@80000000 { + compatible = "renesas,rz-gpt"; + reg = <0x80000000 0x100>; + channel = <7>; + interrupts = , + , + , + , + , + , + , + , + ; + interrupt-names = "ccmpa", "ccmpb", "cmpc", "cmpd", "cmpe", + "cmpf", "ovf", "udf", "dte"; + prescaler = <1>; + status = "disabled"; + + pwm { + compatible = "renesas,rz-gpt-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + }; + + gpt8: gpt8@80000100 { + compatible = "renesas,rz-gpt"; + reg = <0x80000100 0x100>; + channel = <8>; + interrupts = , + , + , + , + , + , + , + , + ; + interrupt-names = "ccmpa", "ccmpb", "cmpc", "cmpd", "cmpe", + "cmpf", "ovf", "udf", "dte"; + prescaler = <1>; + status = "disabled"; + + pwm { + compatible = "renesas,rz-gpt-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + }; + + gpt9: gpt9@80000200 { + compatible = "renesas,rz-gpt"; + reg = <0x80000200 0x100>; + channel = <9>; + interrupts = , + , + , + , + , + , + , + , + ; + interrupt-names = "ccmpa", "ccmpb", "cmpc", "cmpd", "cmpe", + "cmpf", "ovf", "udf", "dte"; + prescaler = <1>; + status = "disabled"; + + pwm { + compatible = "renesas,rz-gpt-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + }; + + gpt10: gpt10@80000300 { + compatible = "renesas,rz-gpt"; + reg = <0x80000300 0x100>; + channel = <10>; + interrupts = , + , + , + , + , + , + , + , + ; + interrupt-names = "ccmpa", "ccmpb", "cmpc", "cmpd", "cmpe", + "cmpf", "ovf", "udf", "dte"; + prescaler = <1>; + status = "disabled"; + + pwm { + compatible = "renesas,rz-gpt-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + }; + + gpt11: gpt11@80000400 { + compatible = "renesas,rz-gpt"; + reg = <0x80000400 0x100>; + channel = <11>; + interrupts = , + , + , + , + , + , + , + , + ; + interrupt-names = "ccmpa", "ccmpb", "cmpc", "cmpd", "cmpe", + "cmpf", "ovf", "udf", "dte"; + prescaler = <1>; + status = "disabled"; + + pwm { + compatible = "renesas,rz-gpt-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + }; + + gpt12: gpt12@80000500 { + compatible = "renesas,rz-gpt"; + reg = <0x80000500 0x100>; + channel = <12>; + interrupts = , + , + , + , + , + , + , + , + ; + interrupt-names = "ccmpa", "ccmpb", "cmpc", "cmpd", "cmpe", + "cmpf", "ovf", "udf", "dte"; + prescaler = <1>; + status = "disabled"; + + pwm { + compatible = "renesas,rz-gpt-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + }; + + gpt13: gpt13@80000600 { + compatible = "renesas,rz-gpt"; + reg = <0x80000600 0x100>; + channel = <13>; + interrupts = , + , + , + , + , + , + , + , + ; + interrupt-names = "ccmpa", "ccmpb", "cmpc", "cmpd", "cmpe", + "cmpf", "ovf", "udf", "dte"; + prescaler = <1>; + status = "disabled"; + + pwm { + compatible = "renesas,rz-gpt-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + }; + + gpt14: gpt14@81000000 { + compatible = "renesas,rz-gpt"; + reg = <0x81000000 0x100>; + channel = <14>; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "ccmpa", "ccmpb", "cmpc", "cmpd", "cmpe", + "cmpf", "ovf", "udf"; + prescaler = <1>; + status = "disabled"; + + pwm { + compatible = "renesas,rz-gpt-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + }; + + gpt15: gpt15@81000100 { + compatible = "renesas,rz-gpt"; + reg = <0x81000100 0x100>; + channel = <15>; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "ccmpa", "ccmpb", "cmpc", "cmpd", "cmpe", + "cmpf", "ovf", "udf"; + prescaler = <1>; + status = "disabled"; + + pwm { + compatible = "renesas,rz-gpt-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + }; + + gpt16: gpt16@81000200 { + compatible = "renesas,rz-gpt"; + reg = <0x81000200 0x100>; + channel = <16>; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "ccmpa", "ccmpb", "cmpc", "cmpd", "cmpe", + "cmpf", "ovf", "udf"; + prescaler = <1>; + status = "disabled"; + + pwm { + compatible = "renesas,rz-gpt-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + }; + + gpt17: gpt17@81000300 { + compatible = "renesas,rz-gpt"; + reg = <0x81000300 0x100>; + channel = <17>; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "ccmpa", "ccmpb", "cmpc", "cmpd", "cmpe", + "cmpf", "ovf", "udf"; + prescaler = <1>; + status = "disabled"; + + pwm { + compatible = "renesas,rz-gpt-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + }; }; }; diff --git a/dts/arm/renesas/rz/rzv/r9a07g054.dtsi b/dts/arm/renesas/rz/rzv/r9a07g054.dtsi index fc98bcf74f8d..1c236ced4ccb 100644 --- a/dts/arm/renesas/rz/rzv/r9a07g054.dtsi +++ b/dts/arm/renesas/rz/rzv/r9a07g054.dtsi @@ -539,6 +539,150 @@ interrupt-names = "eri", "bri", "rxi", "txi", "tei"; status = "disabled"; }; + + gpt32e0: gpt32e@40048000 { + compatible = "renesas,rz-gpt"; + reg = <0x40048000 0xa4>; + channel = <0>; + interrupts = <218 1>, <219 1>, <220 1>, <221 1>, <222 1>, + <223 1>, <224 1>, <225 1>, <226 1>, <227 1>; + interrupt-names = "ccmpa", "ccmpb", "cmpc", "cmpd", "cmpe", + "cmpf", "adtrga", "adtrgb", "ovf", "unf"; + prescaler = <1>; + status = "disabled"; + + pwm { + compatible = "renesas,rz-gpt-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + }; + + gpt32e1: gpt32e@40048100 { + compatible = "renesas,rz-gpt"; + reg = <0x40048100 0xa4>; + channel = <1>; + interrupts = <231 1>, <232 1>, <233 1>, <234 1>, <235 1>, + <236 1>, <237 1>, <238 1>, <239 1>, <240 1>; + interrupt-names = "ccmpa", "ccmpb", "cmpc", "cmpd", "cmpe", + "cmpf", "adtrga", "adtrgb", "ovf", "unf"; + prescaler = <1>; + status = "disabled"; + + pwm { + compatible = "renesas,rz-gpt-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + }; + + gpt32e2: gpt32e@40048200 { + compatible = "renesas,rz-gpt"; + reg = <0x40048200 0xa4>; + channel = <2>; + interrupts = <244 1>, <245 1>, <246 1>, <247 1>, <248 1>, + <249 1>, <250 1>, <251 1>, <252 1>, <253 1>; + interrupt-names = "ccmpa", "ccmpb", "cmpc", "cmpd", "cmpe", + "cmpf", "adtrga", "adtrgb", "ovf", "unf"; + prescaler = <1>; + status = "disabled"; + + pwm { + compatible = "renesas,rz-gpt-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + }; + + gpt32e3: gpt32e@40048300 { + compatible = "renesas,rz-gpt"; + reg = <0x40048300 0xa4>; + channel = <3>; + interrupts = <257 1>, <258 1>, <259 1>, <260 1>, <261 1>, + <262 1>, <263 1>, <264 1>, <265 1>, <266 1>; + interrupt-names = "ccmpa", "ccmpb", "cmpc", "cmpd", "cmpe", + "cmpf", "adtrga", "adtrgb", "ovf", "unf"; + prescaler = <1>; + status = "disabled"; + + pwm { + compatible = "renesas,rz-gpt-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + }; + + gpt32e4: gpt32e@40048400 { + compatible = "renesas,rz-gpt"; + reg = <0x40048400 0xa4>; + channel = <4>; + interrupts = <270 1>, <271 1>, <272 1>, <273 1>, <274 1>, + <275 1>, <276 1>, <277 1>, <278 1>, <279 1>; + interrupt-names = "ccmpa", "ccmpb", "cmpc", "cmpd", "cmpe", + "cmpf", "adtrga", "adtrgb", "ovf", "unf"; + prescaler = <1>; + status = "disabled"; + + pwm { + compatible = "renesas,rz-gpt-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + }; + + gpt32e5: gpt32e@40048500 { + compatible = "renesas,rz-gpt"; + reg = <0x40048500 0xa4>; + channel = <5>; + interrupts = <283 1>, <284 1>, <285 1>, <286 1>, <287 1>, + <288 1>, <289 1>, <290 1>, <291 1>, <292 1>; + interrupt-names = "ccmpa", "ccmpb", "cmpc", "cmpd", "cmpe", + "cmpf", "adtrga", "adtrgb", "ovf", "unf"; + prescaler = <1>; + status = "disabled"; + + pwm { + compatible = "renesas,rz-gpt-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + }; + + gpt32e6: gpt32e@40048600 { + compatible = "renesas,rz-gpt"; + reg = <0x40048600 0xa4>; + channel = <6>; + interrupts = <296 1>, <297 1>, <298 1>, <299 1>, <300 1>, + <301 1>, <302 1>, <303 1>, <304 1>, <305 1>; + interrupt-names = "ccmpa", "ccmpb", "cmpc", "cmpd", "cmpe", + "cmpf", "adtrga", "adtrgb", "ovf", "unf"; + prescaler = <1>; + status = "disabled"; + + pwm { + compatible = "renesas,rz-gpt-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + }; + + gpt32e7: gpt32e@40048700 { + compatible = "renesas,rz-gpt"; + reg = <0x40048700 0xa4>; + channel = <7>; + interrupts = <309 1>, <310 1>, <311 1>, <312 1>, <313 1>, + <314 1>, <315 1>, <316 1>, <317 1>, <318 1>; + interrupt-names = "ccmpa", "ccmpb", "cmpc", "cmpd", "cmpe", + "cmpf", "adtrga", "adtrgb", "ovf", "unf"; + prescaler = <1>; + status = "disabled"; + + pwm { + compatible = "renesas,rz-gpt-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + }; }; }; From cd7dc539529eda2a6913c48df668d9f481e13a98 Mon Sep 17 00:00:00 2001 From: Hieu Nguyen Date: Thu, 10 Jul 2025 14:03:36 +0700 Subject: [PATCH 4/5] boards: renesas: Add PWM support for Renesas RZ/T2M, N2L, V2L Add PWM support for board Renesas RZ/T2M-RSK, RZ/N2L-RSK, RZ/V2L-SMARC Signed-off-by: Hieu Nguyen Signed-off-by: Tien Nguyen --- boards/renesas/rzn2l_rsk/rzn2l_rsk-pinctrl.dtsi | 14 ++++++++++++++ boards/renesas/rzn2l_rsk/rzn2l_rsk.yaml | 1 + boards/renesas/rzt2m_rsk/rzt2m_rsk-pinctrl.dtsi | 13 +++++++++++++ .../rzt2m_rsk/rzt2m_rsk_r9a07g075m24gbg_cr520.yaml | 1 + .../renesas/rzv2l_smarc/rzv2l_smarc-pinctrl.dtsi | 12 ++++++++++++ .../rzv2l_smarc_r9a07g054l23gbg_cm33.yaml | 1 + 6 files changed, 42 insertions(+) diff --git a/boards/renesas/rzn2l_rsk/rzn2l_rsk-pinctrl.dtsi b/boards/renesas/rzn2l_rsk/rzn2l_rsk-pinctrl.dtsi index ab95fd84a7ef..c5a1476d9a95 100644 --- a/boards/renesas/rzn2l_rsk/rzn2l_rsk-pinctrl.dtsi +++ b/boards/renesas/rzn2l_rsk/rzn2l_rsk-pinctrl.dtsi @@ -27,4 +27,18 @@ input-enable; }; }; + + /omit-if-no-ref/ gpt4_pins: gpt4 { + gpt4-pinmux { + pinmux = , /* GTIOCA */ + ; /* GTIOCB */ + }; + }; + + /omit-if-no-ref/ gpt5_pins: gpt5 { + gpt5-pinmux { + pinmux = , /* GTIOCA */ + ; /* GTIOCB */ + }; + }; }; diff --git a/boards/renesas/rzn2l_rsk/rzn2l_rsk.yaml b/boards/renesas/rzn2l_rsk/rzn2l_rsk.yaml index 196b812a193d..1d982f206235 100644 --- a/boards/renesas/rzn2l_rsk/rzn2l_rsk.yaml +++ b/boards/renesas/rzn2l_rsk/rzn2l_rsk.yaml @@ -7,4 +7,5 @@ toolchain: supported: - uart - gpio + - pwm vendor: renesas diff --git a/boards/renesas/rzt2m_rsk/rzt2m_rsk-pinctrl.dtsi b/boards/renesas/rzt2m_rsk/rzt2m_rsk-pinctrl.dtsi index 3bb24fd431b1..66deaced4294 100644 --- a/boards/renesas/rzt2m_rsk/rzt2m_rsk-pinctrl.dtsi +++ b/boards/renesas/rzt2m_rsk/rzt2m_rsk-pinctrl.dtsi @@ -20,4 +20,17 @@ input-enable; }; }; + + /omit-if-no-ref/ gpt0_pins: gpt0 { + gpt0-pinmux { + pinmux = ; /* GTIOCA */ + }; + }; + + /omit-if-no-ref/ gpt4_pins: gpt4 { + gpt4-pinmux { + pinmux = , /* GTIOCA */ + ; /* GTIOCB */ + }; + }; }; diff --git a/boards/renesas/rzt2m_rsk/rzt2m_rsk_r9a07g075m24gbg_cr520.yaml b/boards/renesas/rzt2m_rsk/rzt2m_rsk_r9a07g075m24gbg_cr520.yaml index 2fbd50880f02..d8e608cb4554 100644 --- a/boards/renesas/rzt2m_rsk/rzt2m_rsk_r9a07g075m24gbg_cr520.yaml +++ b/boards/renesas/rzt2m_rsk/rzt2m_rsk_r9a07g075m24gbg_cr520.yaml @@ -12,4 +12,5 @@ toolchain: supported: - uart - gpio + - pwm vendor: renesas diff --git a/boards/renesas/rzv2l_smarc/rzv2l_smarc-pinctrl.dtsi b/boards/renesas/rzv2l_smarc/rzv2l_smarc-pinctrl.dtsi index 3795c701c8fe..35f17d017fa0 100644 --- a/boards/renesas/rzv2l_smarc/rzv2l_smarc-pinctrl.dtsi +++ b/boards/renesas/rzv2l_smarc/rzv2l_smarc-pinctrl.dtsi @@ -13,4 +13,16 @@ ; /* RXD */ }; }; + + /omit-if-no-ref/ gpt6_pins: gpt6 { + gpt6-pinmux { + pinmux = ; /* GTIOCA */ + }; + }; + + /omit-if-no-ref/ gpt7_pins: gpt7 { + gpt7-pinmux { + pinmux = ; /* GTIOCA */ + }; + }; }; diff --git a/boards/renesas/rzv2l_smarc/rzv2l_smarc_r9a07g054l23gbg_cm33.yaml b/boards/renesas/rzv2l_smarc/rzv2l_smarc_r9a07g054l23gbg_cm33.yaml index e3d17a6daf5a..0eb470ab5dbf 100644 --- a/boards/renesas/rzv2l_smarc/rzv2l_smarc_r9a07g054l23gbg_cm33.yaml +++ b/boards/renesas/rzv2l_smarc/rzv2l_smarc_r9a07g054l23gbg_cm33.yaml @@ -8,4 +8,5 @@ toolchain: supported: - uart - gpio + - pwm vendor: renesas From df20b0516e1be6a44972cb4ffff8742bc45483a5 Mon Sep 17 00:00:00 2001 From: Hieu Nguyen Date: Thu, 10 Jul 2025 14:06:04 +0700 Subject: [PATCH 5/5] tests: drivers: pwm: Add PWM support for Renesas RZ/T2M, N2L, V2L Add PWM test support for Renesas RZ/T2M-RSK, RZ/N2L-RSK, RZ/V2L-SMARC Signed-off-by: Hieu Nguyen Signed-off-by: Tien Nguyen --- .../pwm/pwm_api/boards/rzn2l_rsk.overlay | 15 ++++++++ .../rzt2m_rsk_r9a07g075m24gbg_cr520.overlay | 15 ++++++++ .../rzv2l_smarc_r9a07g054l23gbg_cm33.overlay | 15 ++++++++ .../pwm/pwm_loopback/boards/rzn2l_rsk.overlay | 36 +++++++++++++++++++ .../rzt2m_rsk_r9a07g075m24gbg_cr520.overlay | 36 +++++++++++++++++++ .../rzv2l_smarc_r9a07g054l23gbg_cm33.overlay | 36 +++++++++++++++++++ 6 files changed, 153 insertions(+) create mode 100644 tests/drivers/pwm/pwm_api/boards/rzn2l_rsk.overlay create mode 100644 tests/drivers/pwm/pwm_api/boards/rzt2m_rsk_r9a07g075m24gbg_cr520.overlay create mode 100644 tests/drivers/pwm/pwm_api/boards/rzv2l_smarc_r9a07g054l23gbg_cm33.overlay create mode 100644 tests/drivers/pwm/pwm_loopback/boards/rzn2l_rsk.overlay create mode 100644 tests/drivers/pwm/pwm_loopback/boards/rzt2m_rsk_r9a07g075m24gbg_cr520.overlay create mode 100644 tests/drivers/pwm/pwm_loopback/boards/rzv2l_smarc_r9a07g054l23gbg_cm33.overlay diff --git a/tests/drivers/pwm/pwm_api/boards/rzn2l_rsk.overlay b/tests/drivers/pwm/pwm_api/boards/rzn2l_rsk.overlay new file mode 100644 index 000000000000..56d6c3219423 --- /dev/null +++ b/tests/drivers/pwm/pwm_api/boards/rzn2l_rsk.overlay @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&gpt4 { + status = "okay"; + + pwm4: pwm { + status = "okay"; + pinctrl-0 = <&gpt4_pins>; + pinctrl-names = "default"; + }; +}; diff --git a/tests/drivers/pwm/pwm_api/boards/rzt2m_rsk_r9a07g075m24gbg_cr520.overlay b/tests/drivers/pwm/pwm_api/boards/rzt2m_rsk_r9a07g075m24gbg_cr520.overlay new file mode 100644 index 000000000000..db7c74ec7687 --- /dev/null +++ b/tests/drivers/pwm/pwm_api/boards/rzt2m_rsk_r9a07g075m24gbg_cr520.overlay @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&gpt0 { + status = "okay"; + + pwm0: pwm { + status = "okay"; + pinctrl-0 = <&gpt0_pins>; + pinctrl-names = "default"; + }; +}; diff --git a/tests/drivers/pwm/pwm_api/boards/rzv2l_smarc_r9a07g054l23gbg_cm33.overlay b/tests/drivers/pwm/pwm_api/boards/rzv2l_smarc_r9a07g054l23gbg_cm33.overlay new file mode 100644 index 000000000000..abe02fc9dd31 --- /dev/null +++ b/tests/drivers/pwm/pwm_api/boards/rzv2l_smarc_r9a07g054l23gbg_cm33.overlay @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&gpt32e6 { + status = "okay"; + + pwm6: pwm { + status = "okay"; + pinctrl-0 = <&gpt6_pins>; + pinctrl-names = "default"; + }; +}; diff --git a/tests/drivers/pwm/pwm_loopback/boards/rzn2l_rsk.overlay b/tests/drivers/pwm/pwm_loopback/boards/rzn2l_rsk.overlay new file mode 100644 index 000000000000..26a7faf4fca1 --- /dev/null +++ b/tests/drivers/pwm/pwm_loopback/boards/rzn2l_rsk.overlay @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + pwm_loopback_0 { + compatible = "test-pwm-loopback"; + pwms = <&pwm4 RZ_PWM_GPT_IO_A 0 PWM_POLARITY_NORMAL>, + <&pwm5 RZ_PWM_GPT_IO_B 0 PWM_POLARITY_NORMAL>; + }; +}; + +&gpt4 { + status = "okay"; + + pwm4: pwm { + status = "okay"; + pinctrl-0 = <&gpt4_pins>; + pinctrl-names = "default"; + }; +}; + +&gpt5 { + status = "okay"; + + pwm5: pwm { + status = "okay"; + pinctrl-0 = <&gpt5_pins>; + pinctrl-names = "default"; + }; +}; diff --git a/tests/drivers/pwm/pwm_loopback/boards/rzt2m_rsk_r9a07g075m24gbg_cr520.overlay b/tests/drivers/pwm/pwm_loopback/boards/rzt2m_rsk_r9a07g075m24gbg_cr520.overlay new file mode 100644 index 000000000000..1afe5d1227be --- /dev/null +++ b/tests/drivers/pwm/pwm_loopback/boards/rzt2m_rsk_r9a07g075m24gbg_cr520.overlay @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + pwm_loopback_0 { + compatible = "test-pwm-loopback"; + pwms = <&pwm0 RZ_PWM_GPT_IO_A 0 PWM_POLARITY_NORMAL>, + <&pwm4 RZ_PWM_GPT_IO_A 0 PWM_POLARITY_NORMAL>; + }; +}; + +&gpt0 { + status = "okay"; + + pwm0: pwm { + status = "okay"; + pinctrl-0 = <&gpt0_pins>; + pinctrl-names = "default"; + }; +}; + +&gpt4 { + status = "okay"; + + pwm4: pwm { + status = "okay"; + pinctrl-0 = <&gpt4_pins>; + pinctrl-names = "default"; + }; +}; diff --git a/tests/drivers/pwm/pwm_loopback/boards/rzv2l_smarc_r9a07g054l23gbg_cm33.overlay b/tests/drivers/pwm/pwm_loopback/boards/rzv2l_smarc_r9a07g054l23gbg_cm33.overlay new file mode 100644 index 000000000000..910dd67c7ce3 --- /dev/null +++ b/tests/drivers/pwm/pwm_loopback/boards/rzv2l_smarc_r9a07g054l23gbg_cm33.overlay @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + pwm_loopback_0 { + compatible = "test-pwm-loopback"; + pwms = <&pwm6 RZ_PWM_GPT_IO_A 0 PWM_POLARITY_NORMAL>, + <&pwm7 RZ_PWM_GPT_IO_A 0 PWM_POLARITY_NORMAL>; + }; +}; + +&gpt32e6 { + status = "okay"; + + pwm6: pwm { + status = "okay"; + pinctrl-0 = <&gpt6_pins>; + pinctrl-names = "default"; + }; +}; + +&gpt32e7 { + status = "okay"; + + pwm7: pwm { + status = "okay"; + pinctrl-0 = <&gpt7_pins>; + pinctrl-names = "default"; + }; +};