From e4041809c008f42716a2de4373419939c259a0ed Mon Sep 17 00:00:00 2001
From: Fabrice DJIATSA <fabrice.djiatsa-ext@st.com>
Date: Thu, 10 Jul 2025 14:33:27 +0200
Subject: [PATCH] boards: st: nucleo_u385rg_q: update clock domain source for
 rng

Several tests failed due to a low clock frequency for
the RNG peripheral.
Increase the RNG clock frequency by providing MSIK with
96 MHz as the domain source.

Signed-off-by: Fabrice DJIATSA <fabrice.djiatsa-ext@st.com>
---
 boards/st/nucleo_u385rg_q/nucleo_u385rg_q.dts | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/boards/st/nucleo_u385rg_q/nucleo_u385rg_q.dts b/boards/st/nucleo_u385rg_q/nucleo_u385rg_q.dts
index 42b8c67b3f35b..f4e48499301f2 100644
--- a/boards/st/nucleo_u385rg_q/nucleo_u385rg_q.dts
+++ b/boards/st/nucleo_u385rg_q/nucleo_u385rg_q.dts
@@ -110,6 +110,10 @@
 	status = "okay";
 };
 
+&clk_msik {
+	status = "okay";
+};
+
 &clk_msis {
 	status = "okay";
 	msi-pll-mode;
@@ -160,6 +164,8 @@
 };
 
 &rng {
+	clocks = <&rcc STM32_CLOCK(AHB2, 18)>,
+		 <&rcc STM32_SRC_MSIK RNG_SEL(1)>;
 	status = "okay";
 };