diff --git a/arch/arm64/core/Kconfig b/arch/arm64/core/Kconfig
index 57d87e016f16c..a2368adc81240 100644
--- a/arch/arm64/core/Kconfig
+++ b/arch/arm64/core/Kconfig
@@ -72,6 +72,13 @@ config CPU_CORTEX_A76_A55
 	help
 	  This option signifies the use of a Cortex-A76 and A55 big little CPU cluster
 
+config CPU_CORTEX_A78
+	bool
+	select CPU_CORTEX_A
+	select ARMV8_A
+	help
+	  This option signifies the use of a Cortex-A78 CPU
+
 config CPU_CORTEX_R82
 	bool
 	select CPU_AARCH64_CORTEX_R
diff --git a/boards/amd/versalnet_apu/CMakeLists.txt b/boards/amd/versalnet_apu/CMakeLists.txt
new file mode 100644
index 0000000000000..bd0a687ea487e
--- /dev/null
+++ b/boards/amd/versalnet_apu/CMakeLists.txt
@@ -0,0 +1,19 @@
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+# Copyright (c) 2025 Advanced Micro Devices, Inc.
+#
+
+find_package(Dtc 1.4.6 REQUIRED)
+
+# Check if the board-specific qemu.dts file exists
+if(EXISTS "${BOARD_DIR}/${BOARD}-qemu.dts")
+  # Ensure DTC executable is available
+  if(DTC_FOUND)
+    set_property(GLOBAL APPEND PROPERTY extra_post_build_commands
+      COMMAND ${DTC} -I dts -O dtb -q "${BOARD_DIR}/${BOARD}-qemu.dts" -o "${PROJECT_BINARY_DIR}/${BOARD}-qemu.dtb"
+    )
+  else()
+    message(FATAL_ERROR "DTC not found, but required for compiling ${BOARD}-qemu.dts")
+  endif()
+endif()
diff --git a/boards/amd/versalnet_apu/Kconfig.versalnet_apu b/boards/amd/versalnet_apu/Kconfig.versalnet_apu
new file mode 100644
index 0000000000000..feb28a17b275f
--- /dev/null
+++ b/boards/amd/versalnet_apu/Kconfig.versalnet_apu
@@ -0,0 +1,8 @@
+#
+# Copyright (c) 2025 Advanced Micro Devices, Inc.
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+config BOARD_VERSALNET_APU
+	select SOC_AMD_VERSALNET_APU
diff --git a/boards/amd/versalnet_apu/board.cmake b/boards/amd/versalnet_apu/board.cmake
new file mode 100644
index 0000000000000..c086f6706de16
--- /dev/null
+++ b/boards/amd/versalnet_apu/board.cmake
@@ -0,0 +1,22 @@
+#
+# Copyright (c) 2025 Advanced Micro Devices, Inc.
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+include(${ZEPHYR_BASE}/boards/common/xsdb.board.cmake)
+set(SUPPORTED_EMU_PLATFORMS qemu)
+set(QEMU_ARCH xilinx-aarch64)
+set(QEMU_CPU_TYPE_${ARCH} cortexa78)
+
+set(QEMU_FLAGS_${ARCH}
+	-machine arm-generic-fdt
+	-hw-dtb ${PROJECT_BINARY_DIR}/${BOARD}-qemu.dtb
+	-device loader,addr=0xEC200300,data=0x3EE,data-len=4 -device loader,addr=0xEC200300,data=0x3DD,data-len=4
+	-nographic
+	-m 2g
+)
+
+set(QEMU_KERNEL_OPTION
+	-device loader,cpu-num=0,file=\$<TARGET_FILE:\${logical_target_for_zephyr_elf}>
+)
diff --git a/boards/amd/versalnet_apu/board.yml b/boards/amd/versalnet_apu/board.yml
new file mode 100644
index 0000000000000..230690e7c71c1
--- /dev/null
+++ b/boards/amd/versalnet_apu/board.yml
@@ -0,0 +1,5 @@
+board:
+  name: versalnet_apu
+  vendor: amd
+  socs:
+  - name: amd_versalnet_apu
diff --git a/boards/amd/versalnet_apu/doc/index.rst b/boards/amd/versalnet_apu/doc/index.rst
new file mode 100644
index 0000000000000..23e160649de47
--- /dev/null
+++ b/boards/amd/versalnet_apu/doc/index.rst
@@ -0,0 +1,74 @@
+.. zephyr:board:: versalnet_apu
+
+Overview
+********
+This configuration provides support for the APU(A78), ARM processing unit on AMD
+Versal Net SOC, it can operate as following:
+
+* Four independent A78 clusters each having 4 A78 cores
+
+This processing unit is based on an ARM Cortex-A78 CPU, it also enables the following devices:
+
+* ARM GIC v3 Interrupt Controller
+* Global Timer Counter
+* SBSA UART
+
+Hardware
+********
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
+
+Devices
+=======
+System Timer
+------------
+
+This board configuration uses a system timer tick frequency of 100 MHz.
+
+Serial Port
+-----------
+
+This board configuration uses a single serial communication channel with the
+on-chip UART0.
+
+Memories
+--------
+
+Although Flash, DDR and OCM memory regions are defined in the DTS file,
+all the code plus data of the application will be loaded in the sram0 region,
+which points to the DDR memory. The ocm0 memory area is currently available
+for usage, although nothing is placed there by default.
+
+Known Problems or Limitations
+=============================
+
+The following platform features are unsupported:
+
+* Only the first cpu in the first cluster of the A78 subsystem is supported.
+
+Programming and Debugging
+*************************
+
+.. zephyr:board-supported-runners::
+
+Build and flash in the usual way. Here is an example for the :zephyr:code-sample:`hello_world` application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: versalnet_apu
+   :goals: build flash
+
+You should see the following message on the console:
+
+.. code-block:: console
+
+   Hello World! versalnet_apu/amd_versalnet_apu
+
+
+References
+**********
+
+1. ARMv8‑A Architecture Reference Manual (ARM DDI 0487)
+2. Arm Cortex‑A78 Core Technical Reference Manual (Doc ID 101430)
diff --git a/boards/amd/versalnet_apu/support/xsdb.cfg b/boards/amd/versalnet_apu/support/xsdb.cfg
new file mode 100644
index 0000000000000..323c22e188234
--- /dev/null
+++ b/boards/amd/versalnet_apu/support/xsdb.cfg
@@ -0,0 +1,28 @@
+# Copyright (c) 2025 Advanced Micro Devices, Inc.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+proc load_image args  {
+	set elf_file [lindex $args 0]
+	set pdi_file [lindex $args 1]
+	set bl31_file [lindex $args 2]
+
+	if { [info exists ::env(HW_SERVER_URL)] } {
+		connect -url $::env(HW_SERVER_URL)
+	} else {
+		connect
+	}
+
+	device program $pdi_file
+	targets -set -nocase -filter {name =~ "Versal*"}
+	after 100
+	targets -set -filter {name =~ "Cortex-A78AE*0.0"}
+	rst -proc
+	after 100
+	dow -force $elf_file
+	dow -force $bl31_file
+	con
+	exit
+}
+
+load_image {*}$argv
diff --git a/boards/amd/versalnet_apu/versalnet_apu-qemu.dts b/boards/amd/versalnet_apu/versalnet_apu-qemu.dts
new file mode 100644
index 0000000000000..7de829d9a4877
--- /dev/null
+++ b/boards/amd/versalnet_apu/versalnet_apu-qemu.dts
@@ -0,0 +1,5422 @@
+/dts-v1/;
+
+/ {
+	#address-cells = <0x02>;
+	#size-cells = <0x02>;
+	#priority-cells = <0x01>;
+
+	pmc_ppu0_ma {
+		doc-ignore = <0x01>;
+		compatible = "qemu:memory-transaction-attr";
+		secure = <0x01>;
+		requester-id = <0x246>;
+		phandle = <0xbe>;
+	};
+
+	pmc_ppu1_ma {
+		doc-ignore = <0x01>;
+		compatible = "qemu:memory-transaction-attr";
+		secure = <0x01>;
+		requester-id = <0x247>;
+		phandle = <0xbf>;
+	};
+
+	psm_ma {
+		doc-ignore = <0x01>;
+		compatible = "qemu:memory-transaction-attr";
+		secure = <0x01>;
+		requester-id = <0x238>;
+		phandle = <0xc0>;
+	};
+
+	ddrmc_ub0_ma {
+		doc-ignore = <0x01>;
+		compatible = "qemu:memory-transaction-attr";
+		secure = <0x01>;
+		requester-id = <0x00>;
+		phandle = <0xc1>;
+	};
+
+	ddrmc_ub1_ma {
+		doc-ignore = <0x01>;
+		compatible = "qemu:memory-transaction-attr";
+		secure = <0x01>;
+		requester-id = <0x00>;
+		phandle = <0xc2>;
+	};
+
+	pmc_dma0_ma {
+		doc-ignore = <0x01>;
+		compatible = "qemu:memory-transaction-attr";
+		secure = <0x01>;
+		requester-id = <0x248>;
+		phandle = <0x68>;
+	};
+
+	pmc_dma1_ma {
+		doc-ignore = <0x01>;
+		compatible = "qemu:memory-transaction-attr";
+		secure = <0x01>;
+		requester-id = <0x24b>;
+		phandle = <0x69>;
+	};
+
+	pmc_qspi_dma_ma_smid {
+		doc-ignore = <0x01>;
+		compatible = "qemu:memory-transaction-attr";
+		requester-id = <0x244>;
+		phandle = <0x5d>;
+	};
+
+	pmc_qspi_dma_w_ma_smid {
+		doc-ignore = <0x01>;
+		compatible = "qemu:memory-transaction-attr";
+		requester-id = <0x244>;
+		phandle = <0x5b>;
+	};
+
+	apu0_s_ma {
+		doc-ignore = <0x01>;
+		compatible = "qemu:memory-transaction-attr";
+		secure = <0x01>;
+		requester-id = <0x260>;
+		phandle = <0xc3>;
+	};
+
+	apu0_ns_ma {
+		doc-ignore = <0x01>;
+		compatible = "qemu:memory-transaction-attr";
+		secure = <0x00>;
+		requester-id = <0x260>;
+		phandle = <0xc4>;
+	};
+
+	apu1_s_ma {
+		doc-ignore = <0x01>;
+		compatible = "qemu:memory-transaction-attr";
+		secure = <0x01>;
+		requester-id = <0x261>;
+		phandle = <0xc5>;
+	};
+
+	apu1_ns_ma {
+		doc-ignore = <0x01>;
+		compatible = "qemu:memory-transaction-attr";
+		secure = <0x00>;
+		requester-id = <0x261>;
+		phandle = <0xc6>;
+	};
+
+	rpu0_s_ma {
+		doc-ignore = <0x01>;
+		compatible = "qemu:memory-transaction-attr";
+		secure = <0x01>;
+		requester-id = <0x200>;
+		phandle = <0xad>;
+	};
+
+	rpu1_s_ma {
+		doc-ignore = <0x01>;
+		compatible = "qemu:memory-transaction-attr";
+		secure = <0x01>;
+		requester-id = <0x204>;
+		phandle = <0xb0>;
+	};
+
+	gem0_ma_smid {
+		doc-ignore = <0x01>;
+		compatible = "qemu:memory-transaction-attr";
+		requester-id = <0x234>;
+		phandle = <0x14>;
+	};
+
+	gem0_w_ma_smid {
+		doc-ignore = <0x01>;
+		compatible = "qemu:memory-transaction-attr";
+		requester-id = <0x234>;
+		phandle = <0x15>;
+	};
+
+	gem1_ma_smid {
+		doc-ignore = <0x01>;
+		compatible = "qemu:memory-transaction-attr";
+		requester-id = <0x235>;
+		phandle = <0x19>;
+	};
+
+	gem1_w_ma_smid {
+		doc-ignore = <0x01>;
+		compatible = "qemu:memory-transaction-attr";
+		requester-id = <0x235>;
+		phandle = <0x1a>;
+	};
+
+	ospi_dma_ma_smid {
+		doc-ignore = <0x01>;
+		compatible = "qemu:memory-transaction-attr";
+		requester-id = <0x245>;
+		phandle = <0x61>;
+	};
+
+	ospi_dma_w_ma_smid {
+		doc-ignore = <0x01>;
+		compatible = "qemu:memory-transaction-attr";
+		requester-id = <0x245>;
+		phandle = <0x5c>;
+	};
+
+	sd0_ma_smid {
+		doc-ignore = <0x01>;
+		compatible = "qemu:memory-transaction-attr";
+		requester-id = <0x242>;
+		phandle = <0x57>;
+	};
+
+	sd0_w_ma_smid {
+		doc-ignore = <0x01>;
+		compatible = "qemu:memory-transaction-attr";
+		requester-id = <0x242>;
+		phandle = <0x58>;
+	};
+
+	sd1_ma_smid {
+		doc-ignore = <0x01>;
+		compatible = "qemu:memory-transaction-attr";
+		requester-id = <0x243>;
+		phandle = <0x59>;
+	};
+
+	sd1_w_ma_smid {
+		doc-ignore = <0x01>;
+		compatible = "qemu:memory-transaction-attr";
+		requester-id = <0x243>;
+		phandle = <0x5a>;
+	};
+
+	usb0_ma {
+		doc-ignore = <0x01>;
+		compatible = "qemu:memory-transaction-attr";
+		secure = <0x00>;
+		requester-id = <0x230>;
+		phandle = <0x1c>;
+	};
+
+	amba_root@0 {
+		#address-cells = <0x02>;
+		#size-cells = <0x02>;
+		#priority-cells = <0x01>;
+		#interrupt-cells = <0x01>;
+		interrupt-map-mask = <0x00 0x00 0xffff>;
+		interrupt-map = <0x00 0x00 0x00 0x01 0x00 0x00 0x04 0x00 0x00 0x01 0x01 0x00 0x01
+0x04 0x00 0x00 0x02 0x01 0x00 0x02 0x04 0x00 0x00 0x03 0x01 0x00 0x03 0x04 0x00 0x00 0x04 0x01
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+0x01 0x00 0x7d 0x04 0x00 0x00 0x7e 0x01 0x00 0x7e 0x04 0x00 0x00 0x7f 0x01 0x00 0x7f 0x04
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+0x04 0x00 0x00 0xb9 0x05 0x00 0xb9 0x04 0x00 0x00 0xba 0x05 0x00 0xba 0x04 0x00 0x00 0xbb
+0x05 0x00 0xbb 0x04 0x00 0x00 0xbc 0x05 0x00 0xbc 0x04 0x00 0x00 0xbd 0x05 0x00 0xbd 0x04
+0x00 0x00 0xbe 0x05 0x00 0xbe 0x04 0x00 0x00 0xbf 0x05 0x00 0xbf 0x04 0x00 0x00 0xc0 0x05
+0x00 0xc0 0x04 0x00 0x00 0xc1 0x05 0x00 0xc1 0x04 0x00 0x00 0xc2 0x05 0x00 0xc2 0x04 0x00
+0x00 0xc3 0x05 0x00 0xc3 0x04 0x00 0x00 0xc4 0x05 0x00 0xc4 0x04 0x00 0x00 0xc5 0x05 0x00
+0xc5 0x04 0x00 0x00 0xc6 0x05 0x00 0xc6 0x04 0x00 0x00 0xc7 0x05 0x00 0xc7 0x04 0x00 0x00
+0xc8 0x05 0x00 0xc8 0x04 0x00 0x00 0xc9 0x05 0x00 0xc9 0x04 0x00 0x00 0xca 0x05 0x00 0xca
+0x04 0x00 0x00 0xcb 0x05 0x00 0xcb 0x04 0x00 0x00 0xcc 0x05 0x00 0xcc 0x04 0x00 0x00 0xcd
+0x05 0x00 0xcd 0x04 0x00 0x00 0xce 0x05 0x00 0xce 0x04 0x00 0x00 0xcf 0x05 0x00 0xcf 0x04
+0x00 0x00 0xd0 0x05 0x00 0xd0 0x04 0x00 0x00 0xd1 0x05 0x00 0xd1 0x04 0x00 0x00 0xd2 0x05
+0x00 0xd2 0x04 0x00 0x00 0xd3 0x05 0x00 0xd3 0x04 0x00 0x00 0xd4 0x05 0x00 0xd4 0x04 0x00
+0x00 0xd5 0x05 0x00 0xd5 0x04 0x00 0x00 0xd6 0x05 0x00 0xd6 0x04 0x00 0x00 0xd7 0x05 0x00
+0xd7 0x04 0x00 0x00 0xd8 0x05 0x00 0xd8 0x04 0x00 0x00 0xd9 0x05 0x00 0xd9 0x04 0x00 0x00
+0xda 0x05 0x00 0xda 0x04 0x00 0x00 0xdb 0x05 0x00 0xdb 0x04 0x00 0x00 0xdc 0x05 0x00 0xdc
+0x04 0x00 0x00 0xdd 0x05 0x00 0xdd 0x04 0x00 0x00 0xa0 0x05 0x00 0xa0 0x04 0x00 0x00 0xbca
+0x06 0x12 0x00 0x00 0xbd4 0x06 0x1c 0x00 0x00 0xbd5 0x06 0x1d 0x00 0x00 0xfb2 0x07 0x12>;
+		phandle = <0xc7>;
+
+		amba@0 {
+			#address-cells = <0x02>;
+			#size-cells = <0x02>;
+			#priority-cells = <0x01>;
+			compatible = "simple-bus";
+			ranges;
+			phandle = <0x0b>;
+
+			downstream_amba_lpd {
+				compatible = "qemu:memory-region";
+				alias = <0x08>;
+				reg = <0x00 0x00 0xffffffff 0xffffffff 0xffffffff>;
+			};
+
+			downstream_amba_fpd {
+				compatible = "qemu:memory-region";
+				alias = <0x09>;
+				reg = <0x00 0x00 0xffffffff 0xffffffff 0xffffffff>;
+			};
+
+			downstream_amba_pmc_internal {
+				compatible = "qemu:memory-region";
+				alias = <0x0a>;
+				reg = <0x00 0x00 0xffffffff 0xffffffff 0xffffffff>;
+			};
+
+			xmpu_ocm@0 {
+				compatible = "xlnx,versal-xmpu";
+				interrupts = <0x13>;
+				reg-extended = <0x0b 0x00 0xeb400000 0x00 0x10000
+0x00 0x0b 0x00 0xbbf00000 0x00 0x80000 0x02>;
+				protected-mr = <0x0c>;
+				mr-0 = <0x0b>;
+				protected-base = <0xbbf00000>;
+				phandle = <0xc8>;
+			};
+
+			xmpu_ocm2@0 {
+				compatible = "xlnx,versal-xmpu";
+				interrupts = <0x13>;
+				reg-extended = <0x0b 0x00 0xeb970000 0x00 0x10000
+0x00 0x0d 0x00 0xea800000 0x00 0x800000 0x02>;
+				protected-mr = <0x0e>;
+				mr-0 = <0x08>;
+				protected-base = <0xea800000>;
+				phandle = <0xc9>;
+			};
+
+			loader_write_cpu0_0x1@0xF1110880 {
+				compatible = "loader";
+				addr = <0xf1110880>;
+				data = <0x01>;
+				data-len = <0x04>;
+				cpu-num = <0x00>;
+				attrs-debug = <0x01>;
+				attrs-secure = <0x00>;
+				attrs-requester-id = <0x00>;
+				phandle = <0xca>;
+			};
+
+			loader_write_cpu0_0x5@0xFD1A0050 {
+				compatible = "loader";
+				addr = <0xfd1a0050>;
+				data = <0x05>;
+				data-len = <0x04>;
+				cpu-num = <0x00>;
+				attrs-debug = <0x01>;
+				attrs-secure = <0x00>;
+				attrs-requester-id = <0x00>;
+				phandle = <0xcb>;
+			};
+
+			loader_write_cpu0_0xFF@0xF111010C {
+				compatible = "loader";
+				addr = <0xf111010c>;
+				data = <0xff>;
+				data-len = <0x04>;
+				cpu-num = <0x00>;
+				attrs-debug = <0x01>;
+				attrs-secure = <0x00>;
+				attrs-requester-id = <0x00>;
+				phandle = <0xcc>;
+			};
+
+			s_axi_tcm_a@0 {
+				compatible = "qemu:memory-region";
+				alias = <0x0f>;
+				reg = <0x00 0xeba00000 0x00 0x800000 0x00>;
+				phandle = <0x28>;
+			};
+
+			s_axi_tcm_b@0 {
+				compatible = "qemu:memory-region";
+				alias = <0x10>;
+				reg = <0x00 0xeba80000 0x00 0x800000 0x00>;
+				phandle = <0x2c>;
+			};
+
+			loader_write_cpu0_0x80C@0xF12B0100 {
+				compatible = "loader";
+				addr = <0xf12b0100>;
+				data = <0x80c>;
+				data-len = <0x04>;
+				cpu-num = <0x00>;
+				attrs-debug = <0x01>;
+				attrs-secure = <0x00>;
+				attrs-requester-id = <0x00>;
+				phandle = <0xcd>;
+			};
+		};
+
+		amba_lpd@0 {
+			#address-cells = <0x02>;
+			#size-cells = <0x02>;
+			#priority-cells = <0x01>;
+			compatible = "simple-bus";
+			ranges;
+			phandle = <0x08>;
+
+			downstream_amba_psm {
+				compatible = "qemu:memory-region";
+				alias = <0x11>;
+				reg = <0x00 0x00 0xffffffff 0xffffffff 0xffffffff>;
+			};
+
+			downstream_amba_xram {
+				compatible = "qemu:memory-region";
+				alias = <0x0d>;
+				reg = <0x00 0x00 0xffffffff 0xffffffff 0xffffffff>;
+			};
+
+			xppu_lpd@0xeb990000 {
+				compatible = "xlnx,versal-xppu";
+				reg-extended = <0x08 0x00 0xeb990000 0x00 0x10000 0x00 0x12
+0x00 0xff000000 0x00 0xe00000 0x02 0x12 0x00 0xfe000000 0x00 0x1000000 0x02 0x0b 0x00 0xe0000000
+0x00 0x10000000 0x02>;
+				mr = <0x08>;
+				interrupts = <0x50>;
+				region = <0x00>;
+				phandle = <0xce>;
+			};
+
+			ethernet@0xf19e0000 {
+				#address-cells = <0x01>;
+				#size-cells = <0x00>;
+				#priority-cells = <0x00>;
+				compatible = "cdns,gem";
+				interrupts = <0x27 0x27>;
+				dma = <0x13>;
+				memattr = <0x14>;
+				memattr-write = <0x15>;
+				reg = <0x00 0xf19e0000 0x00 0x10000 0x00>;
+				num-priority-queues = <0x02>;
+				reset-gpios = <0x16 0x01>;
+				power-gpios = <0x17 0x20>;
+				mdio = <0x18>;
+				phandle = <0xcf>;
+			};
+
+			ethernet@0xf19f0000 {
+				#address-cells = <0x01>;
+				#size-cells = <0x00>;
+				#priority-cells = <0x00>;
+				compatible = "cdns,gem";
+				interrupts = <0x29 0x29>;
+				dma = <0x13>;
+				memattr = <0x19>;
+				memattr-write = <0x1a>;
+				reg = <0x00 0xf19f0000 0x00 0x10000 0x00>;
+				num-priority-queues = <0x02>;
+				reset-gpios = <0x16 0x02>;
+				power-gpios = <0x17 0x21>;
+				mdio = <0x18>;
+				phandle = <0xd0>;
+			};
+
+			serial@0xf1920000 {
+				compatible = "pl011";
+				interrupts = <0x19>;
+				reg = <0x00 0xf1920000 0x00 0x10000 0x00>;
+				reset-gpios = <0x16 0x05>;
+				chardev = "con";
+				phandle = <0xd1>;
+			};
+
+			serial@0xf1930000 {
+				compatible = "pl011";
+				interrupts = <0x1a>;
+				reg = <0x00 0xf1930000 0x00 0x10000 0x00>;
+				reset-gpios = <0x16 0x06>;
+				chardev = "serial3";
+				phandle = <0xd2>;
+			};
+
+			canfdbus@0 {
+				compatible = "can-bus";
+				phandle = <0x1b>;
+			};
+
+			can@0xf1980000 {
+				compatible = "xlnx,versal-canfd";
+				rx-fifo0 = <0x40>;
+				rx-fifo1 = <0x40>;
+				enable-rx-fifo1 = <0x01>;
+				canfdbus = <0x1b>;
+				interrupts = <0x1b>;
+				reg = <0x00 0xf1980000 0x00 0x10000 0x00>;
+				reset-gpios = <0x16 0x09>;
+				phandle = <0xd3>;
+			};
+
+			can@0xf1990000 {
+				compatible = "xlnx,versal-canfd";
+				rx-fifo0 = <0x40>;
+				rx-fifo1 = <0x40>;
+				enable-rx-fifo1 = <0x01>;
+				canfdbus = <0x1b>;
+				interrupts = <0x1c>;
+				reg = <0x00 0xf1990000 0x00 0x10000 0x00>;
+				reset-gpios = <0x16 0x0a>;
+				phandle = <0xd4>;
+			};
+
+			crl@0xeb5e0000 {
+				compatible = "xlnx,psx_crl";
+				reg = <0x00 0xeb5e0000 0x00 0x300000 0x00>;
+				gpio-controller;
+				#gpio-cells = <0x01>;
+				phandle = <0x16>;
+			};
+
+			slcr@0xf19a0000 {
+				compatible = "xlnx,versal-lpd-iou-slcr";
+				reg = <0x00 0xf19a0000 0x00 0x20000 0x00>;
+				phandle = <0xd5>;
+			};
+
+			ipi@0xeb300000 {
+				compatible = "xlnx,versal-ipi";
+				reg = <0x00 0xeb300000 0x00 0x100000 0x00>;
+				interrupts = <0xfb2 0xbd4 0x39 0x3a 0x3b 0x3c 0x3d 0x3e
+0x3f 0xbd5 0x46 0x40 0x41 0x42 0x43 0x44 0x45>;
+				reset-gpios = <0x16 0x19>;
+				num-master-ids = <0x20>;
+				phandle = <0xd6>;
+			};
+
+			spi@0xf1960000 {
+				compatible = "cdns,spi-r1p6";
+				interrupts = <0x17>;
+				num-ss-bits = <0x04>;
+				reg = <0x00 0xf1960000 0x00 0x10000 0x00>;
+				#address-cells = <0x01>;
+				#size-cells = <0x00>;
+				#bus-cells = <0x01>;
+				reset-gpios = <0x16 0x07>;
+				phandle = <0xd7>;
+
+				spi0_flash0@0 {
+					#address-cells = <0x01>;
+					#size-cells = <0x01>;
+					#priority-cells = <0x00>;
+					#bus-cells = <0x01>;
+					compatible = "m25p80\0st,m25p80";
+					spi-max-frequency = <0x2faf080>;
+					reg = <0x00 0x00>;
+					blockdev-node-name = "spi0_flash0";
+					phandle = <0xd8>;
+
+					spi0_flash0@0x00000000 {
+						label = "spi0_flash0";
+						reg = <0x00 0x100000>;
+					};
+				};
+			};
+
+			spi@0xf1970000 {
+				compatible = "cdns,spi-r1p6";
+				interrupts = <0x18>;
+				num-ss-bits = <0x04>;
+				reg = <0x00 0xf1970000 0x00 0x10000 0x00>;
+				#address-cells = <0x01>;
+				#size-cells = <0x00>;
+				#bus-cells = <0x01>;
+				reset-gpios = <0x16 0x08>;
+				phandle = <0xd9>;
+
+				spi1_flash0@0 {
+					#address-cells = <0x01>;
+					#size-cells = <0x01>;
+					#priority-cells = <0x00>;
+					#bus-cells = <0x01>;
+					compatible = "m25p80\0st,m25p80";
+					spi-max-frequency = <0x2faf080>;
+					reg = <0x00 0x00>;
+					blockdev-node-name = "spi1_flash0";
+					phandle = <0xda>;
+
+					spi1_flash0@0x00000000 {
+						label = "spi1_flash0";
+						reg = <0x00 0x100000>;
+					};
+				};
+			};
+
+			usb2@USB2_0_XHCI {
+				compatible = "usb_dwc3";
+				reg = <0x00 0xf1b0c100 0x00 0x600 0x00
+0x00 0xf1b00000 0x00 0x100000 0x00>;
+				interrupts = <0x1d 0x1e 0x1f 0x20>;
+				dma = <0x13>;
+				memattr = <0x1c>;
+				reset-gpios = <0x16 0x03>;
+				intrs = <0x04>;
+				slots = <0x02>;
+				phandle = <0xdb>;
+			};
+
+			timer@0xf1dc0000 {
+				compatible = "xlnx,ps7-ttc-1.00.a";
+				interrupts = <0x2b 0x2c 0x2d>;
+				reg = <0x00 0xf1dc0000 0x00 0x10000 0x00>;
+				width = <0x20>;
+				reset-gpios = <0x16 0x12>;
+				phandle = <0xdc>;
+			};
+
+			timer@0xf1dd0000 {
+				compatible = "xlnx,ps7-ttc-1.00.a";
+				interrupts = <0x2e 0x2f 0x30>;
+				reg = <0x00 0xf1dd0000 0x00 0x10000 0x00>;
+				width = <0x20>;
+				reset-gpios = <0x16 0x13>;
+				phandle = <0xdd>;
+			};
+
+			timer@0xf1de0000 {
+				compatible = "xlnx,ps7-ttc-1.00.a";
+				interrupts = <0x31 0x32 0x33>;
+				reg = <0x00 0xf1de0000 0x00 0x10000 0x00>;
+				width = <0x20>;
+				reset-gpios = <0x16 0x14>;
+				phandle = <0xde>;
+			};
+
+			timer@0xf1df0000 {
+				compatible = "xlnx,ps7-ttc-1.00.a";
+				interrupts = <0x34 0x35 0x36>;
+				reg = <0x00 0xf1df0000 0x00 0x10000 0x00>;
+				width = <0x20>;
+				reset-gpios = <0x16 0x15>;
+				phandle = <0xdf>;
+			};
+
+			adma0mattr {
+				compatible = "qemu:memory-transaction-attr";
+				requester-id = <0x210>;
+				phandle = <0x1d>;
+			};
+
+			dma-controller@0xebd00000 {
+				compatible = "xlnx,zdma";
+				reg = <0x00 0xebd00000 0x00 0x10000 0x00>;
+				bus-width = <0x80>;
+				has-parity = <0x01>;
+				interrupts = <0x48>;
+				#stream-id-cells = <0x01>;
+				dma = <0x13>;
+				memattr = <0x1d>;
+				reset-gpios = <0x16 0x00>;
+				#gpio-cells = <0x01>;
+				gpio-names = "memattr-secure";
+				gpios = <0x1e 0x00>;
+				phandle = <0xe0>;
+			};
+
+			adma1mattr {
+				compatible = "qemu:memory-transaction-attr";
+				requester-id = <0x212>;
+				phandle = <0x1f>;
+			};
+
+			dma-controller@0xebd10000 {
+				compatible = "xlnx,zdma";
+				reg = <0x00 0xebd10000 0x00 0x10000 0x00>;
+				bus-width = <0x80>;
+				has-parity = <0x01>;
+				interrupts = <0x49>;
+				#stream-id-cells = <0x01>;
+				dma = <0x13>;
+				memattr = <0x1f>;
+				reset-gpios = <0x16 0x00>;
+				#gpio-cells = <0x01>;
+				gpio-names = "memattr-secure";
+				gpios = <0x1e 0x01>;
+				phandle = <0xe1>;
+			};
+
+			adma2mattr {
+				compatible = "qemu:memory-transaction-attr";
+				requester-id = <0x214>;
+				phandle = <0x20>;
+			};
+
+			dma-controller@0xebd20000 {
+				compatible = "xlnx,zdma";
+				reg = <0x00 0xebd20000 0x00 0x10000 0x00>;
+				bus-width = <0x80>;
+				has-parity = <0x01>;
+				interrupts = <0x4a>;
+				#stream-id-cells = <0x01>;
+				dma = <0x13>;
+				memattr = <0x20>;
+				reset-gpios = <0x16 0x00>;
+				#gpio-cells = <0x01>;
+				gpio-names = "memattr-secure";
+				gpios = <0x1e 0x02>;
+				phandle = <0xe2>;
+			};
+
+			adma3mattr {
+				compatible = "qemu:memory-transaction-attr";
+				requester-id = <0x216>;
+				phandle = <0x21>;
+			};
+
+			dma-controller@0xebd30000 {
+				compatible = "xlnx,zdma";
+				reg = <0x00 0xebd30000 0x00 0x10000 0x00>;
+				bus-width = <0x80>;
+				has-parity = <0x01>;
+				interrupts = <0x4b>;
+				#stream-id-cells = <0x01>;
+				dma = <0x13>;
+				memattr = <0x21>;
+				reset-gpios = <0x16 0x00>;
+				#gpio-cells = <0x01>;
+				gpio-names = "memattr-secure";
+				gpios = <0x1e 0x03>;
+				phandle = <0xe3>;
+			};
+
+			adma4mattr {
+				compatible = "qemu:memory-transaction-attr";
+				requester-id = <0x218>;
+				phandle = <0x22>;
+			};
+
+			dma-controller@0xebd40000 {
+				compatible = "xlnx,zdma";
+				reg = <0x00 0xebd40000 0x00 0x10000 0x00>;
+				bus-width = <0x80>;
+				has-parity = <0x01>;
+				interrupts = <0x4c>;
+				#stream-id-cells = <0x01>;
+				dma = <0x13>;
+				memattr = <0x22>;
+				reset-gpios = <0x16 0x00>;
+				#gpio-cells = <0x01>;
+				gpio-names = "memattr-secure";
+				gpios = <0x1e 0x04>;
+				phandle = <0xe4>;
+			};
+
+			adma5mattr {
+				compatible = "qemu:memory-transaction-attr";
+				requester-id = <0x21a>;
+				phandle = <0x23>;
+			};
+
+			dma-controller@0xebd50000 {
+				compatible = "xlnx,zdma";
+				reg = <0x00 0xebd50000 0x00 0x10000 0x00>;
+				bus-width = <0x80>;
+				has-parity = <0x01>;
+				interrupts = <0x4d>;
+				#stream-id-cells = <0x01>;
+				dma = <0x13>;
+				memattr = <0x23>;
+				reset-gpios = <0x16 0x00>;
+				#gpio-cells = <0x01>;
+				gpio-names = "memattr-secure";
+				gpios = <0x1e 0x05>;
+				phandle = <0xe5>;
+			};
+
+			adma6mattr {
+				compatible = "qemu:memory-transaction-attr";
+				requester-id = <0x21c>;
+				phandle = <0x24>;
+			};
+
+			dma-controller@0xebd60000 {
+				compatible = "xlnx,zdma";
+				reg = <0x00 0xebd60000 0x00 0x10000 0x00>;
+				bus-width = <0x80>;
+				has-parity = <0x01>;
+				interrupts = <0x4e>;
+				#stream-id-cells = <0x01>;
+				dma = <0x13>;
+				memattr = <0x24>;
+				reset-gpios = <0x16 0x00>;
+				#gpio-cells = <0x01>;
+				gpio-names = "memattr-secure";
+				gpios = <0x1e 0x06>;
+				phandle = <0xe6>;
+			};
+
+			adma7mattr {
+				compatible = "qemu:memory-transaction-attr";
+				requester-id = <0x21e>;
+				phandle = <0x25>;
+			};
+
+			dma-controller@0xebd70000 {
+				compatible = "xlnx,zdma";
+				reg = <0x00 0xebd70000 0x00 0x10000 0x00>;
+				bus-width = <0x80>;
+				has-parity = <0x01>;
+				interrupts = <0x4f>;
+				#stream-id-cells = <0x01>;
+				dma = <0x13>;
+				memattr = <0x25>;
+				reset-gpios = <0x16 0x00>;
+				#gpio-cells = <0x01>;
+				gpio-names = "memattr-secure";
+				gpios = <0x1e 0x07>;
+				phandle = <0xe7>;
+			};
+
+			afi_fm@0xeb9b0000 {
+				compatible = "xlnx,versal-afi-fm";
+				reg = <0x00 0xeb9b0000 0x00 0x10000 0x00>;
+			};
+
+			lpd_i2c_wrapper {
+
+				ps_i2c0@0xf1940000 {
+					#address-cells = <0x01>;
+					#size-cells = <0x00>;
+					compatible = "xlnx,ps7-i2c-1.00.a\0cdns,i2c-r1p10";
+					interrupts = <0x15>;
+					reg-extended = <0x08 0x00 0xf1940000 0x00 0x10000 0x00>;
+					reset-gpios = <0x16 0x0b>;
+					phandle = <0xe8>;
+
+					i2c0_bridge@0 {
+						compatible = "i2c-wire";
+						i2cWire-peer = <0x26>;
+						phandle = <0x27>;
+					};
+				};
+
+				ps_i2c0@0xf1950000 {
+					#address-cells = <0x01>;
+					#size-cells = <0x00>;
+					compatible = "xlnx,ps7-i2c-1.00.a\0cdns,i2c-r1p10";
+					interrupts = <0x16>;
+					reg-extended = <0x08 0x00 0xf1950000 0x00 0x10000 0x00>;
+					reset-gpios = <0x16 0x0c>;
+					phandle = <0xe9>;
+
+					eeprom@54 {
+						compatible = "at,24c08";
+						reg = <0x54>;
+						size = <0x2000>;
+						blockdev-node-name = "i2c1.eeprom-54";
+						phandle = <0xea>;
+					};
+
+					eeprom@51 {
+						compatible = "at,24c08";
+						reg = <0x51>;
+						size = <0x2000>;
+						blockdev-node-name = "i2c1.eeprom-51";
+						phandle = <0xeb>;
+					};
+
+					i2c1_bridge@0 {
+						compatible = "i2c-wire";
+						i2cWire-peer = <0x27>;
+						phandle = <0x26>;
+					};
+				};
+			};
+
+			ocm_ctrl@OCM {
+				compatible = "xlnx,zynqmp-ocmc";
+				interrupts = <0x10>;
+				memsize = <0x80000>;
+				reg = <0x00 0xeb5d0000 0x00 0x10000 0x00>;
+				reset-gpios = <0x16 0x18>;
+				phandle = <0xec>;
+			};
+
+			lpd_slcr@0xeb410000 {
+				compatible = "xlnx,versal-lpd-slcr";
+				reg = <0x00 0xeb410000 0x00 0x100000 0x00>;
+			};
+
+			lpd_slcr_secure@0xeb510000 {
+				compatible = "xlnx,versal-lpd-slcr-secure";
+				reg = <0x00 0xeb510000 0x00 0x40000 0x00>;
+				gpio-controller;
+				#gpio-cells = <0x01>;
+				phandle = <0x1e>;
+			};
+
+			lpd_iou_slcr_secure@0xf19c0000 {
+				compatible = "xlnx,versal-lpd-iou-slcr-secure";
+				reg = <0x00 0xf19c0000 0x00 0x10000 0x00>;
+				memattr-gem0 = <0x14>;
+				memattr-write-gem0 = <0x15>;
+				memattr-gem1 = <0x19>;
+				memattr-write-gem1 = <0x1a>;
+				phandle = <0xed>;
+			};
+
+			lpd_gpio@0xf19d0000 {
+				#gpio-cells = <0x01>;
+				compatible = "xlnx,zynqmp-gpio";
+				gpio-controller;
+				interrupts = <0x14>;
+				reg = <0x00 0xf19d0000 0x00 0x10000 0x00>;
+				reset-gpios = <0x16 0x11>;
+				phandle = <0xee>;
+			};
+
+			intlpd@0xea600000 {
+				compatible = "xlnx-intlpd-config";
+				reg = <0x00 0xea600000 0x00 0x200000 0x00>;
+				interrupts = <0x50>;
+				phandle = <0xef>;
+			};
+
+			virtio_mmio_0 {
+				compatible = "virtio-mmio";
+				reg = <0x00 0xf5e00000 0x00 0x1000 0x00>;
+				interrupts = <0x05>;
+			};
+
+			virtio_mmio_1 {
+				compatible = "virtio-mmio";
+				reg = <0x00 0xf5e01000 0x00 0x1000 0x00>;
+				interrupts = <0x06>;
+			};
+
+			virtio_mmio_2 {
+				compatible = "virtio-mmio";
+				reg = <0x00 0xf5e02000 0x00 0x1000 0x00>;
+				interrupts = <0x07>;
+			};
+
+			virtio_mmio_3 {
+				compatible = "virtio-mmio";
+				reg = <0x00 0xf5e03000 0x00 0x1000 0x00>;
+				interrupts = <0x08>;
+			};
+
+			virtio_mmio_4 {
+				compatible = "virtio-mmio";
+				reg = <0x00 0xf5e04000 0x00 0x1000 0x00>;
+				interrupts = <0x09>;
+			};
+
+			virtio_mmio_5 {
+				compatible = "virtio-mmio";
+				reg = <0x00 0xf5e05000 0x00 0x1000 0x00>;
+				interrupts = <0x0a>;
+			};
+
+			virtio_mmio_6 {
+				compatible = "virtio-mmio";
+				reg = <0x00 0xf5e06000 0x00 0x1000 0x00>;
+				interrupts = <0x0b>;
+			};
+
+			virtio_mmio_7 {
+				compatible = "virtio-mmio";
+				reg = <0x00 0xf5e07000 0x00 0x1000 0x00>;
+				interrupts = <0x0c>;
+			};
+
+			rpu_ctrl@0 {
+				#gpio-cells = <0x01>;
+				gpio-controller;
+				phandle = <0xf0>;
+			};
+
+			rpu_cluster@0xeb580000 {
+				compatible = "xlnx,psx_rpu_cluster_2.0";
+				reg = <0x00 0xeb580000 0x00 0x8000 0x00>;
+				#gpio-cells = <0x01>;
+				gpio-controller;
+				tcm-mr = <0x28>;
+				phandle = <0x2a>;
+			};
+
+			rpu_ctrl_a0@0xeb588000 {
+				compatible = "xlnx,psx_rpu_cluster_core0";
+				reg = <0x00 0xeb588000 0x00 0x4000 0x00>;
+				#gpio-cells = <0x01>;
+				gpio-controller;
+				gpios = <0x16 0x23>;
+				core = <0x29>;
+				phandle = <0xae>;
+			};
+
+			rpu_ctrl_a1@0xeb58c000 {
+				compatible = "xlnx,psx_rpu_cluster_core1";
+				reg = <0x00 0xeb58c000 0x00 0x4000 0x00>;
+				#gpio-cells = <0x01>;
+				gpio-controller;
+				gpios = <0x16 0x24 0x2a 0x00>;
+				core = <0x2b>;
+				phandle = <0xb1>;
+			};
+
+			rpu_cluster@0xeb590000 {
+				compatible = "xlnx,psx_rpu_cluster_2.0";
+				reg = <0x00 0xeb590000 0x00 0x8000 0x00>;
+				#gpio-cells = <0x01>;
+				gpio-controller;
+				tcm-mr = <0x2c>;
+				phandle = <0x2e>;
+			};
+
+			rpu_ctrl_b0@0xeb598000 {
+				compatible = "xlnx,psx_rpu_cluster_core0";
+				reg = <0x00 0xeb598000 0x00 0x4000 0x00>;
+				#gpio-cells = <0x01>;
+				gpio-controller;
+				gpios = <0x16 0x25>;
+				core = <0x2d>;
+				phandle = <0xb4>;
+			};
+
+			rpu_ctrl_b1@0xeb59c000 {
+				compatible = "xlnx,psx_rpu_cluster_core1";
+				reg = <0x00 0xeb59c000 0x00 0x4000 0x00>;
+				#gpio-cells = <0x01>;
+				gpio-controller;
+				gpios = <0x16 0x26 0x2e 0x00>;
+				core = <0x2f>;
+				phandle = <0xb7>;
+			};
+
+			rpu_pcil@0xEB420000 {
+				compatible = "xlnx,rpu_pcil";
+				reg = <0x00 0xeb420000 0x00 0x10000 0x00>;
+				gpio-controller;
+				#gpio-cells = <0x01>;
+				phandle = <0x91>;
+			};
+
+			usb2@USB2_0_XHCI1 {
+				compatible = "usb_dwc3";
+				reg = <0x00 0xf1c0c100 0x00 0x600 0x00
+0x00 0xf1c00000 0x00 0x100000 0x00>;
+				interrupts = <0x22 0x23 0x24 0x25>;
+				dma = <0x13>;
+				memattr = <0x30>;
+				reset-gpios = <0x16 0x04>;
+				intrs = <0x04>;
+				slots = <0x02>;
+				phandle = <0xf1>;
+			};
+		};
+
+		amba_fpd@0 {
+			#address-cells = <0x02>;
+			#size-cells = <0x02>;
+			#priority-cells = <0x01>;
+			compatible = "simple-bus";
+			ranges;
+			phandle = <0x09>;
+
+			afi_fm@0xec880000 {
+				compatible = "xlnx,versal-afi-fm";
+				reg = <0x00 0xec880000 0x00 0x10000 0x00>;
+			};
+
+			afi_fm@0xec8a0000 {
+				compatible = "xlnx,versal-afi-fm";
+				reg = <0x00 0xec8a0000 0x00 0x10000 0x00>;
+			};
+
+			cpm_crcpm@0xfca00000 {
+				compatible = "xlnx,versal_cpm_crcpm";
+				reg = <0x00 0xfca00000 0x00 0x10000 0x00>;
+			};
+
+			cpm_pcsr@0xfcff0000 {
+				compatible = "xlnx,versal_cpm_pcsr";
+				reg = <0x00 0xfcff0000 0x00 0x10000 0x00>;
+			};
+
+			fpd_slcr@0xec8c0000 {
+				compatible = "xlnx,versal-fpd-slcr";
+				interrupts = <0xa3>;
+				reg = <0x00 0xec8c0000 0x00 0x10000 0x00>;
+			};
+
+			fpd_slcr_secure@0xec8c0000 {
+				compatible = "xlnx,versal-fpd-slcr-secure";
+				interrupts = <0xa3>;
+				reg = <0x00 0xec8e0000 0x00 0x10000 0x00>;
+			};
+
+			watchdog@0xecc10000 {
+				compatible = "xlnx,versal-wwdt";
+				reg = <0x00 0xecc10000 0x00 0x10000 0x00>;
+				interrupts = <0x8b 0x8c 0x8d 0x8e>;
+				pclk = <0x5f5e100>;
+				reset-gpios = <0x31 0x1b>;
+				phandle = <0xf2>;
+			};
+
+			intfpd@0xec400000 {
+				compatible = "xlnx-intfpd-config";
+				reg = <0x00 0xec400000 0x00 0x400000 0x00>;
+				interrupts = <0xa3>;
+				phandle = <0xf3>;
+			};
+
+			apu_cluster@MM_FPD_FPD_APU_CLUSTER0 {
+				#gpio-cells = <0x01>;
+				gpio-controller;
+				compatible = "xlnx,versal-apu-ctrl";
+				reg = <0x00 0xecc00000 0x00 0x10000 0x00>;
+				cpu0 = <0x32>;
+				cpu1 = <0x33>;
+				cpu2 = <0x34>;
+				cpu3 = <0x35>;
+				cores-per-cluster = <0x04>;
+				phandle = <0xf4>;
+			};
+
+			apu_cluster@MM_FPD_FPD_APU_CLUSTER1 {
+				#gpio-cells = <0x01>;
+				gpio-controller;
+				compatible = "xlnx,versal-apu-ctrl";
+				reg = <0x00 0xecd00000 0x00 0x10000 0x00>;
+				cpu0 = <0x36>;
+				cpu1 = <0x37>;
+				cpu2 = <0x38>;
+				cpu3 = <0x39>;
+				cores-per-cluster = <0x04>;
+				phandle = <0xf5>;
+			};
+
+			apu_cluster@MM_FPD_FPD_APU_CLUSTER2 {
+				#gpio-cells = <0x01>;
+				gpio-controller;
+				compatible = "xlnx,versal-apu-ctrl";
+				reg = <0x00 0xece00000 0x00 0x10000 0x00>;
+				cpu0 = <0x3a>;
+				cpu1 = <0x3b>;
+				cpu2 = <0x3c>;
+				cpu3 = <0x3d>;
+				cores-per-cluster = <0x04>;
+				phandle = <0xf6>;
+			};
+
+			apu_cluster@MM_FPD_FPD_APU_CLUSTER3 {
+				#gpio-cells = <0x01>;
+				gpio-controller;
+				compatible = "xlnx,versal-apu-ctrl";
+				reg = <0x00 0xecf00000 0x00 0x10000 0x00>;
+				cpu0 = <0x3e>;
+				cpu1 = <0x3f>;
+				cpu2 = <0x40>;
+				cpu3 = <0x41>;
+				cores-per-cluster = <0x04>;
+				phandle = <0xf7>;
+			};
+
+			cmn600ae@0xa0000000 {
+				compatible = "arm,cmn600ae";
+				reg = <0x00 0xa0000000 0x00 0x3000000 0x00>;
+			};
+
+			smmuv3@MM_FPD_SMMU {
+				compatible = "arm-smmuv3";
+				reg-extended = <0x09 0x00 0xec000000 0x00 0x200000
+0x00 0x13 0x00 0x00 0xffffffff 0xffffffff 0x00 0x42 0x00 0x00 0xffffffff 0xffffffff
+0x00 0x43 0x00 0x00 0xffffffff 0xffffffff 0x00 0x44 0x00 0x00 0xffffffff 0xffffffff
+0x00 0x45 0x00 0x00 0xffffffff 0xffffffff 0x00 0x46 0x00 0x00 0xffffffff 0xffffffff
+0x00 0x47 0x00 0x00 0xffffffff 0xffffffff 0x00 0x48 0x00 0x00 0xffffffff 0xffffffff
+0x00 0x49 0x00 0x00 0xffffffff 0xffffffff 0x00 0x4a 0x00 0x00 0xffffffff 0xffffffff
+0x00 0x4b 0x00 0x00 0xffffffff 0xffffffff 0x00 0x4c 0x00 0x00 0xffffffff 0xffffffff
+0x00 0x4d 0x00 0x00 0xffffffff 0xffffffff 0x00>;
+				mr-0 = <0x0b>;
+				mr-1 = <0x0b>;
+				mr-2 = <0x0b>;
+				mr-3 = <0x0b>;
+				mr-4 = <0x0b>;
+				mr-5 = <0x0b>;
+				mr-6 = <0x0b>;
+				mr-7 = <0x0b>;
+				mr-8 = <0x0b>;
+				mr-9 = <0x0b>;
+				mr-10 = <0x0b>;
+				mr-11 = <0x0b>;
+				mr-12 = <0x0b>;
+				dma_mr = <0x0b>;
+				primary-bus = <0x4e>;
+				phandle = <0xf8>;
+			};
+
+			dummy_pcie@0x6_0000_0000 {
+				compatible = "PCI";
+				phandle = <0x4e>;
+			};
+
+			pki_rng@0x20400040000ULL {
+				compatible = "xlnx,psx-pki-rng";
+				reg = <0x204 0x40000 0x00 0x20000 0x00>;
+				interrupts = <0x9c>;
+				phandle = <0xf9>;
+			};
+
+			apu_pcil@0xecb10000 {
+				compatible = "xlnx.apu_pcil";
+				reg = <0x00 0xecb10000 0x00 0x10000 0x00>;
+				phandle = <0xfa>;
+			};
+
+			cpm5_crx@0xdc0000 {
+				compatible = "xlnx,cpm5_crx";
+				reg = <0x00 0xe4dc0000 0x00 0x10000 0x00>;
+				phandle = <0xfb>;
+			};
+
+			cpm5_slcr_secure@0xde0000 {
+				compatible = "xlnx,cpm5_slcr_secure";
+				reg = <0x00 0xe4de0000 0x00 0x10000 0x00>;
+			};
+
+			cpm5_gtyp_cfg@0xd00000 {
+				compatible = "xlnx,gtyp_npi_slave";
+				reg = <0x00 0xe4d00000 0x00 0x20000 0x00>;
+			};
+
+			cpm5_gtyp_cfg@0xd20000 {
+				compatible = "xlnx,gtyp_npi_slave";
+				reg = <0x00 0xe4d20000 0x00 0x20000 0x00>;
+			};
+
+			cpm5_gtyp_cfg@0xd40000 {
+				compatible = "xlnx,gtyp_npi_slave";
+				reg = <0x00 0xe4d40000 0x00 0x20000 0x00>;
+			};
+
+			cpm5_gtyp_cfg@0xd60000 {
+				compatible = "xlnx,gtyp_npi_slave";
+				reg = <0x00 0xe4d60000 0x00 0x20000 0x00>;
+			};
+		};
+
+		amba_pmc_internal@0 {
+			doc-ignore = <0x01>;
+			#address-cells = <0x02>;
+			#size-cells = <0x02>;
+			#priority-cells = <0x01>;
+			compatible = "simple-bus";
+			ranges;
+			phandle = <0x0a>;
+
+			downstream_amba_pmc_ppu {
+				compatible = "qemu:memory-region";
+				alias = <0x4f>;
+				reg = <0x00 0x00 0xffffffff 0xffffffff 0xffffffff>;
+			};
+
+			downstream_amba_pmc_iou {
+				compatible = "qemu:memory-region";
+				alias = <0x12>;
+				reg = <0x00 0x00 0xffffffff 0xffffffff 0xffffffff>;
+			};
+
+			downstream_amba_pmc_sec {
+				compatible = "qemu:memory-region";
+				alias = <0x50>;
+				reg = <0x00 0x00 0xffffffff 0xffffffff 0xffffffff>;
+			};
+
+			downstream_amba_pmc_sys {
+				compatible = "qemu:memory-region";
+				alias = <0x51>;
+				reg = <0x00 0x00 0xffffffff 0xffffffff 0xffffffff>;
+			};
+
+			downstream_amba_pmc_pl {
+				compatible = "qemu:memory-region";
+				alias = <0x52>;
+				reg = <0x00 0x00 0xffffffff 0xffffffff 0xffffffff>;
+			};
+
+			downstream_amba_pmc_bat {
+				compatible = "qemu:memory-region";
+				alias = <0x53>;
+				reg = <0x00 0x00 0xffffffff 0xffffffff 0xffffffff>;
+			};
+
+			xmpu_pmc@0 {
+				compatible = "xlnx,versal-xmpu";
+				interrupts = <0xc0>;
+				reg-extended = <0x0a 0x00 0xf12f0000 0x00 0x10000 0x00 0x0a
+0x00 0xf2000000 0x00 0x20000 0x02>;
+				protected-mr = <0x54>;
+				mr-0 = <0x0a>;
+				protected-base = <0xf2000000>;
+				phandle = <0xfc>;
+			};
+
+			xppu_pmc_npi@0xf1300000 {
+				compatible = "xlnx,versal-xppu";
+				reg-extended = <0x0a 0x00 0xf1300000 0x00 0x10000
+0x00 0x0a 0x00 0xf6000000 0x00 0x1000000 0x02 0x0a 0x00 0xf7000000 0x00 0x1000000 0x02>;
+				mr = <0x52>;
+				interrupts = <0xc0>;
+				region = <0x02>;
+				phandle = <0xfd>;
+			};
+
+			xppu_pmc@0xf1310000 {
+				compatible = "xlnx,versal-xppu";
+				reg-extended = <0x0a 0x00 0xf1310000 0x00 0x10000 0x00 0x0b
+0x00 0xf1000000 0x00 0x1000000 0x02 0x0b 0x00 0xf0000000 0x00 0x1000000 0x02 0x0b 0x00
+0xc0000000 0x00 0x20000000 0x02>;
+				mr = <0x0a>;
+				interrupts = <0xc0>;
+				region = <0x01>;
+				phandle = <0xfe>;
+			};
+		};
+
+		amba_pmc@0 {
+			#address-cells = <0x02>;
+			#size-cells = <0x02>;
+			#priority-cells = <0x01>;
+			compatible = "simple-bus";
+			ranges;
+			phandle = <0x55>;
+
+			downstream_amba {
+				compatible = "qemu:memory-region";
+				alias = <0x0b>;
+				reg = <0x00 0x00 0xffffffff 0xffffffff 0xffffffff>;
+			};
+
+			downstream_amba_pmc_internal {
+				compatible = "qemu:memory-region";
+				alias = <0x0a>;
+				reg = <0x00 0x00 0xffffffff 0xffffffff 0xffffffff>;
+			};
+
+			xmpu_pmc_cfu@0xf1340000 {
+				compatible = "xlnx,versal-xmpu";
+				reg-extended = <0x55 0x00 0xf1340000 0x00 0x10000 0x00 0x52
+0x00 0xf12b0000 0x00 0x11000 0x02 0x52 0x00 0xf1f80000 0x00 0x40000 0x02>;
+				protected-mr = <0x56>;
+				mr-0 = <0x52>;
+				protected-base = <0xf12b0000>;
+				phandle = <0xff>;
+			};
+
+			pmx_err_mng@0xf1110000 {
+				compatible = "xlnx,pmx-err-mng";
+				reg = <0x00 0xf1130000 0x00 0x10000 0x01>;
+				phandle = <0x100>;
+			};
+		};
+
+		amba_pmc_iou@0 {
+			#address-cells = <0x02>;
+			#size-cells = <0x02>;
+			#priority-cells = <0x01>;
+			compatible = "simple-bus";
+			ranges;
+			doc-name = "PMC IOU";
+			doc-status = "partial";
+			phandle = <0x12>;
+
+			pmc_iou_slcr@0xf1060000 {
+				doc-status = "partial";
+				compatible = "xlnx,versal-pmx-iou-slcr";
+				reg = <0x00 0xf1060000 0x00 0x1000 0x00>;
+				interrupts = <0xbc>;
+				gpio-controller;
+				#gpio-cells = <0x02>;
+				phandle = <0x65>;
+			};
+
+			pmc_iou_slcr_secure@0xf1070000 {
+				compatible = "xlnx,versal-pmc-iou-slcr-secure";
+				reg = <0x00 0xf1070000 0x00 0x10000 0x00>;
+				interrupts = <0xbca>;
+				memattr-sd0 = <0x57>;
+				memattr-write-sd0 = <0x58>;
+				memattr-sd1 = <0x59>;
+				memattr-write-sd1 = <0x5a>;
+				memattr-write-qspi = <0x5b>;
+				memattr-write-ospi = <0x5c>;
+				phandle = <0x101>;
+			};
+
+			pmc_qspi_dma@QSPI_DMA {
+				doc-status = "complete";
+				compatible = "zynqmp,csu-dma";
+				interrupts = <0xb7>;
+				#stream-id-cells = <0x01>;
+				reg = <0x00 0xf1030800 0x00 0x800 0x00>;
+				dma = <0x55>;
+				memattr = <0x5d>;
+				memattr-write = <0x5b>;
+				is-dst = <0x01>;
+				reset-gpios = <0x5e 0x00>;
+				phandle = <0x5f>;
+			};
+
+			pmc_qspi@0xf1030000 {
+				doc-status = "complete";
+				#address-cells = <0x01>;
+				#size-cells = <0x00>;
+				#bus-cells = <0x01>;
+				compatible = "xlnx,usmp-gqspi\0cdns,spi-r1p6";
+				stream-connected-dma = <0x5f>;
+				dma = <0x55>;
+				interrupts = <0xb7>;
+				num-ss-bits = <0x02>;
+				reg-extended = <0x12 0x00 0xf1030000 0x00 0x1000 0x00 0x60
+0x00 0x00 0x00 0x20000000 0x00>;
+				speed-hz = <0x989680>;
+				xlnx,fb-clk = <0x01>;
+				xlnx,qspi-clk-freq-hz = <0xbebc200>;
+				xlnx,qspi-mode = <0x02>;
+				reset-gpios = <0x5e 0x00>;
+				phandle = <0x102>;
+
+				qspi_flash_lcs_lb@0 {
+					#address-cells = <0x01>;
+					#size-cells = <0x01>;
+					#priority-cells = <0x00>;
+					#bus-cells = <0x01>;
+					compatible = "m25qu02gcbb\0st,m25p80";
+					spi-max-frequency = <0x2faf080>;
+					reg = <0x00 0x00>;
+					drive-index = <0x00>;
+					phandle = <0x103>;
+
+					qspi_flash_lcs_lb@0x00000000 {
+						label = "qspi_flash_lcs_lb";
+						reg = <0x00 0x2000000>;
+					};
+				};
+
+				qspi_flash_ucs_ub@0 {
+					#address-cells = <0x01>;
+					#size-cells = <0x01>;
+					#priority-cells = <0x00>;
+					#bus-cells = <0x01>;
+					compatible = "m25qu02gcbb\0st,m25p80";
+					spi-max-frequency = <0x2faf080>;
+					reg = <0x03 0x01>;
+					drive-index = <0x03>;
+					phandle = <0x104>;
+
+					qspi_flash_ucs_ub@0x00000000 {
+						label = "qspi_flash_ucs_ub";
+						reg = <0x00 0x2000000>;
+					};
+				};
+			};
+
+			ospi_dst_dma@0 {
+				doc-status = "complete";
+				compatible = "zynqmp,csu-dma";
+				interrupts = <0xb6>;
+				reg = <0x00 0xf1011800 0x00 0x800 0x00>;
+				dma = <0x55>;
+				memattr = <0x61>;
+				memattr-write = <0x5c>;
+				is-dst = <0x01>;
+				reset-gpios = <0x5e 0x01>;
+				phandle = <0x63>;
+			};
+
+			ospi_src_dma@0 {
+				doc-status = "complete";
+				compatible = "zynqmp,csu-dma";
+				interrupts = <0xb6>;
+				reg = <0x00 0xf1011000 0x00 0x800 0x00>;
+				dma = <0x62>;
+				memattr = <0x61>;
+				memattr-write = <0x5c>;
+				stream-connected-dma = <0x63>;
+				reset-gpios = <0x5e 0x01>;
+				phandle = <0x64>;
+			};
+
+			spi@0xf1010000 {
+				doc-status = "complete";
+				#address-cells = <0x01>;
+				#size-cells = <0x00>;
+				#bus-cells = <0x01>;
+				compatible = "xlnx,versal-ospi";
+				reg-extended = <0x12 0x00 0xf1010000 0x00 0x1000 0x00 0x62
+0x00 0x00 0x00 0x20000000 0x00>;
+				dma-src = <0x64>;
+				interrupts = <0xb6>;
+				reset-gpios = <0x5e 0x01>;
+				gpios = <0x65 0x03 0x00>;
+				phandle = <0x105>;
+			};
+
+			gpio_mr_mux@0xc0000000 {
+				doc-status = "complete";
+				compatible = "gpio-mr-mux";
+				reg = <0x00 0xc0000000 0x00 0x20000000 0x00>;
+				gpios = <0x65 0x02 0x00 0x65 0x03 0x00>;
+				mr-size = <0x20000000>;
+				mr0 = <0x60>;
+				mr1 = <0x62>;
+				mr2 = <0x60>;
+				mr3 = <0x62>;
+				phandle = <0x106>;
+			};
+
+			pmc_gpio@0xf1020000 {
+				#gpio-cells = <0x01>;
+				compatible = "xlnx,zynqmp-gpio";
+				gpio-controller;
+				interrupts = <0xb4>;
+				reg = <0x00 0xf1020000 0x00 0x10000 0x00>;
+				reset-gpios = <0x5e 0x05>;
+				phandle = <0x107>;
+			};
+
+			mmc@0xf1040000 {
+				doc-status = "complete";
+				compatible = "xilinx,zynqmp-sdhci\0generic-sdhci";
+				drive-index = <0x00>;
+				reg = <0x00 0xf1040000 0x00 0x10000 0x00>;
+				interrupts = <0xb8>;
+				dma = <0x13>;
+				memattr = <0x57>;
+				memattr-write = <0x58>;
+				gpios = <0x65 0x00 0x00>;
+				gpio-names = "SLOTTYPE";
+				reset-gpios = <0x5e 0x08>;
+				is-mmc = <0x00>;
+				xlnx,has-cd = <0x01>;
+				xlnx,has-power = <0x00>;
+				xlnx,has-wp = <0x01>;
+				xlnx,sdio-clk-freq-hz = <0x2faf080>;
+				phandle = <0x108>;
+			};
+
+			mmc@0xf1050000 {
+				doc-status = "complete";
+				compatible = "xlnx,versalnet-emmc";
+				drive-index = <0x01>;
+				reg = <0x00 0xf1050200 0x00 0x100 0x00
+0x00 0xf1050000 0x00 0x100 0x00>;
+				interrupts = <0xba>;
+				dma = <0x13>;
+				memattr = <0x59>;
+				memattr-write = <0x5a>;
+				gpios = <0x65 0x01 0x00>;
+				gpio-names = "SLOTTYPE";
+				reset-gpios = <0x5e 0x03>;
+				is-mmc = <0x00>;
+				xlnx,has-cd = <0x01>;
+				xlnx,has-power = <0x00>;
+				xlnx,has-wp = <0x01>;
+				xlnx,sdio-clk-freq-hz = <0x2faf080>;
+				phandle = <0x109>;
+			};
+
+			pmc_tap@0xf11a0000 {
+				doc-status = "complete";
+				doc-comments = "Just a stub.";
+				compatible = "xlnx,pmc-tap";
+				interrupts-extended = <0x66 0x1e>;
+				interrupt-names = "sec-dbg-int";
+				reg = <0x00 0xf11a0000 0x00 0x80000 0x00>;
+				idcode = <0x14d80093>;
+				platform-ver = <0x05>;
+				phandle = <0x10a>;
+			};
+
+			pmc_i2c_wrapper {
+			};
+
+			wwdt@0xf03f0000 {
+				compatible = "xlnx,versal-wwdt";
+				reg = <0x00 0xf03f0000 0x00 0x10000 0x00>;
+				pclk = <0x5f5e100>;
+				phandle = <0x10b>;
+			};
+		};
+
+		amba_pmc_sec@0 {
+			#address-cells = <0x02>;
+			#size-cells = <0x02>;
+			#priority-cells = <0x01>;
+			compatible = "simple-bus";
+			ranges;
+			doc-name = "PMC Secure";
+			doc-status = "in-progress";
+			qemu-fdt-abort-on-error = "Unable to create PMC security models.\n
+Cannot continue.Try installing libgcrypt.";
+			phandle = <0x50>;
+
+			trng@0xf1230000 {
+				doc-status = "complete";
+				compatible = "xlnx,versal-trng";
+				reg = <0x00 0xf1230000 0x00 0x1000 0x00>;
+				interrupts = <0xc7>;
+			};
+
+			pmc_dma0_src@0 {
+				doc-status = "complete";
+				compatible = "zynqmp,csu-dma";
+				stream-connected-dma0 = <0x67>;
+				reg = <0x00 0xf11c0000 0x00 0x800 0x00>;
+				dma = <0x55>;
+				memattr = <0x68>;
+				dma-width = <0x10>;
+				interrupts = <0xbe>;
+				reset-gpios = <0x5e 0x13>;
+				byte-align = <0x01>;
+				phandle = <0x10c>;
+			};
+
+			pmc_dma0_dst@0 {
+				doc-status = "complete";
+				compatible = "zynqmp,csu-dma";
+				reg = <0x00 0xf11c0800 0x00 0x800 0x00>;
+				dma = <0x55>;
+				memattr = <0x68>;
+				is-dst = <0x01>;
+				dma-width = <0x10>;
+				interrupts = <0xbe>;
+				reset-gpios = <0x5e 0x13>;
+				byte-align = <0x01>;
+				phandle = <0x6a>;
+			};
+
+			pmc_dma1_src@0 {
+				doc-status = "complete";
+				compatible = "zynqmp,csu-dma";
+				stream-connected-dma1 = <0x67>;
+				reg = <0x00 0xf11d0000 0x00 0x800 0x00>;
+				dma = <0x55>;
+				memattr = <0x69>;
+				dma-width = <0x10>;
+				interrupts = <0xbf>;
+				reset-gpios = <0x5e 0x14>;
+				byte-align = <0x01>;
+				phandle = <0x10d>;
+			};
+
+			pmc_dma1_dst@0 {
+				doc-status = "complete";
+				compatible = "zynqmp,csu-dma";
+				reg = <0x00 0xf11d0800 0x00 0x800 0x00>;
+				dma = <0x55>;
+				memattr = <0x69>;
+				is-dst = <0x01>;
+				dma-width = <0x10>;
+				interrupts = <0xbf>;
+				reset-gpios = <0x5e 0x14>;
+				byte-align = <0x01>;
+				phandle = <0x6b>;
+			};
+
+			pmc_stream_switch@0 {
+				doc-status = "complete";
+				compatible = "versal,pmc-sss";
+				reg-extended = <0x51 0x00 0xf1110500 0x00 0x04 0x01>;
+				stream-connected-dma0 = <0x6a>;
+				stream-connected-dma1 = <0x6b>;
+				stream-connected-aes = <0x6c>;
+				stream-connected-sha = <0x6d>;
+				stream-connected-sbi = <0x6e>;
+				stream-connected-sha1 = <0x6f>;
+				phandle = <0x67>;
+			};
+
+			pmc_sha@0xf1210000 {
+				doc-status = "complete";
+				compatible = "zynqmp,csu-sha3";
+				reg = <0x00 0xf1210000 0x00 0x100 0x00>;
+				interrupts = <0xc5>;
+				phandle = <0x6d>;
+			};
+
+			pmc_aes@0xf11e0000 {
+				doc-status = "in-progress";
+				#gpio-cells = <0x01>;
+				gpio-controller;
+				compatible = "xlnx,versal-aes";
+				stream-connected-aes = <0x67>;
+				reg = <0x00 0xf11e0000 0x00 0x100 0x00>;
+				interrupts = <0xc2>;
+				gpios = <0x70 0x00 0x70 0x01>;
+				gpio-names = "busy\0done";
+				aes-core = <0x70>;
+				phandle = <0x6c>;
+
+				xlnx_aes@0 {
+					#gpio-cells = <0x01>;
+					compatible = "xlnx-aes";
+					gpios = <0x6c 0x00>;
+					gpio-names = "reset";
+					phandle = <0x70>;
+				};
+			};
+
+			pmc_rsa@0xf1200000 {
+				doc-status = "complete";
+				reg = <0x00 0xf1200000 0x00 0x6c 0x00>;
+				interrupts = <0xc3>;
+				ram-nr-words = <0x100>;
+				phandle = <0x10e>;
+			};
+
+			xlnx_pmc_efuse_cache@0xf1250000 {
+				doc-status = "complete";
+				compatible = "xlnx,pmx_efuse_cache";
+				reg = <0x00 0xf1250000 0x00 0x10000 0x00>;
+				efuse = <0x71>;
+				phandle = <0x75>;
+			};
+
+			pmc_puf_ctrl@0 {
+				compatible = "xlnx,versal-puf-ctrl";
+				zynqmp-aes-key-sink-puf = <0x6c>;
+				efuse = <0x71>;
+				reg = <0x00 0xf1150000 0x00 0x10000 0x00>;
+				#gpio-cells = <0x01>;
+				gpio-controller;
+				phandle = <0x73>;
+			};
+
+			pmc_efuse@0xf1240000 {
+				doc-status = "complete";
+				compatible = "xlnx,pmx_efuse_ctrl";
+				#gpio-cells = <0x02>;
+				zynqmp-aes-key-sink-efuses = <0x6c>;
+				zynqmp-aes-key-sink-efuses-user0 = <0x6c>;
+				zynqmp-aes-key-sink-efuses-user1 = <0x6c>;
+				reg = <0x00 0xf1240000 0x00 0x10000 0x00>;
+				interrupts = <0xc4>;
+				efuse = <0x71>;
+				phandle = <0x10f>;
+
+				xlnx_efuse@0 {
+					doc-ignore = <0x01>;
+					compatible = "xlnx,efuse";
+					efuse-nr = <0x03>;
+					efuse-size = <0x2000>;
+					init-factory-extidcode = <0x01>;
+					phandle = <0x71>;
+				};
+			};
+
+			pmc_bbram@0xf11f0000 {
+				doc-status = "partial";
+				doc-limitations = "Missing AES key connections.";
+				compatible = "xlnx,bbram-ctrl";
+				reg = <0x00 0xf11f0000 0x00 0x10000 0x00>;
+				interrupts = <0xbca>;
+				zynqmp-aes-key-sink-bbram = <0x6c>;
+				crc-zpads = <0x00>;
+				phandle = <0x74>;
+			};
+
+			pmc_sbi@0xf1220000 {
+				doc-status = "complete";
+				compatible = "pmc,slave-boot";
+				reg = <0x00 0xf1220000 0x00 0x10000 0x00
+0x00 0xf2100000 0x00 0x10000 0x00>;
+				interrupts = <0xc1>;
+				stream-connected-sbi = <0x67>;
+				reset-gpios = <0x5e 0x12>;
+				phandle = <0x6e>;
+			};
+
+			pmc_sha1@0xF1800000 {
+				doc-status = "complete";
+				compatible = "zynqmp,csu-sha3";
+				reg = <0x00 0xf1800000 0x00 0x10000 0x00>;
+				phandle = <0x6f>;
+			};
+		};
+
+		amba_pmc_ppu@0 {
+			#address-cells = <0x02>;
+			#size-cells = <0x02>;
+			#priority-cells = <0x01>;
+			compatible = "simple-bus";
+			ranges;
+			phandle = <0x4f>;
+
+			pmc_gic_proxy@0 {
+				doc-status = "complete";
+				#interrupt-cells = <0x03>;
+				interrupt-controller;
+				compatible = "xlnx,zynqmp-gicp";
+				reg = <0x00 0xf1140000 0x00 0x100 0x00>;
+				interrupt-parent = <0x06>;
+				interrupts = <0x10>;
+				max-ints = <0x100>;
+				phandle = <0x04>;
+			};
+		};
+
+		amba_pmc_sys@0 {
+			#address-cells = <0x02>;
+			#size-cells = <0x02>;
+			#priority-cells = <0x01>;
+			compatible = "simple-bus";
+			ranges;
+			doc-name = "PMC System";
+			doc-status = "partial";
+			phandle = <0x51>;
+
+			pmc_clk_rst@0xf1260000 {
+				doc-status = "partial";
+				compatible = "xlnx,pmx_crp";
+				reg = <0x00 0xf1260000 0x00 0x80000 0x00>;
+				interrupts = <0xbca>;
+				gpio-controller;
+				#gpio-cells = <0x01>;
+				phandle = <0x5e>;
+			};
+
+			pmc_int@0xf1400000 {
+				doc-status = "partial";
+				compatible = "xlnx,versal-pmc-int";
+				reg = <0x00 0xf1400000 0x00 0x300000 0x00>;
+				interrupts = <0xc0>;
+				phandle = <0x110>;
+			};
+
+			pmc_reset_domain@0 {
+				compatible = "qemu,reset-device";
+				gpios = <0x5e 0x02>;
+			};
+
+			pmc_global@0xf1110000 {
+				doc-status = "partial";
+				#gpio-cells = <0x01>;
+				gpio-controller;
+				interrupts-extended = <0x06 0x10 0x06 0x1b 0x06 0x1b 0x06
+0x1b 0x06 0x1b 0x06 0x11 0x06 0x11 0x72 0x00 0x66 0x10 0x66 0x11 0x66 0x12 0x66 0x13 0x66
+0x14 0x66 0x15 0x66 0x16 0x66 0x17 0x66 0x18 0x66 0x19 0x66 0x1a 0x66 0x1b 0x72 0x00 0x66 0x1d>;
+				reg = <0x00 0xf1110000 0x00 0x50000 0x00>;
+				gpios = <0x73 0x00>;
+				bbram = <0x74>;
+				efuse = <0x75>;
+				compatible = "xlnx,pmx_global";
+				phandle = <0x76>;
+			};
+
+			pmc_err_mng@0xF1130000 {
+				compatible = "xlnx,PmcErrMngmnt";
+				reg = <0x00 0xf1130000 0x00 0x10000 0x00>;
+				interrupts = <0xbca>;
+				phandle = <0x111>;
+			};
+
+			pmc_stream_zero@ {
+				compatible = "xlnx,pmc-stream-zero";
+				reg = <0x00 0xf1110518 0x00 0x04 0x01>;
+				stream-connected-pzm = <0x67>;
+				phandle = <0x112>;
+			};
+
+			pmc_analog@0xf1160000 {
+				compatible = "xlnx,pmx_anlg";
+				reg = <0x00 0xf1160000 0x00 0x40000 0x00>;
+				interrupts-extended = <0x04 0x00 0xdd 0x00>;
+				tamper-sink = <0x76>;
+			};
+
+			pmc_sysmon@0xf1270000 {
+				compatible = "xlnx,pmc-sysmon";
+				reg = <0x00 0xf1270000 0x00 0x30000 0x00>;
+				interrupts = <0xca 0xcb>;
+				reset-gpios = <0x5e 0x15>;
+				efuse = <0x75>;
+				ams-sats = <0x77 0x78 0x79 0x7a 0x7b 0x7c 0x7d>;
+				tamper-sink = <0x76>;
+				phandle = <0x113>;
+			};
+
+			pmc_ams_sat@0 {
+				compatible = "xlnx,ams-sat";
+				reg = <0x00 0xf1280000 0x00 0x10000 0x01>;
+				phandle = <0x77>;
+			};
+
+			pmc_ams_sat@1 {
+				compatible = "xlnx,ams-sat";
+				reg = <0x00 0xf1290000 0x00 0x10000 0x01>;
+				phandle = <0x78>;
+			};
+
+			versal_pmc_tamper@ {
+				compatible = "xlnx,pmc_tamper";
+				reg-extended = <0x51 0x00 0xf1110530 0x00 0x38 0x01 0x7e
+0x00 0xf0041100 0x00 0x38 0x02>;
+				phandle = <0x114>;
+			};
+
+			lpd_ams_sat@0 {
+				compatible = "xlnx,ams-sat";
+				reg = <0x00 0xeb550000 0x00 0x10000 0x01>;
+				phandle = <0x79>;
+			};
+
+			fpd_ams_sat@0 {
+				compatible = "xlnx,ams-sat";
+				reg = <0x00 0xecc30000 0x00 0x10000 0x01>;
+				phandle = <0x7a>;
+			};
+
+			fpd_ams_sat@1 {
+				compatible = "xlnx,ams-sat";
+				reg = <0x00 0xecd30000 0x00 0x10000 0x01>;
+				phandle = <0x7b>;
+			};
+
+			fpd_ams_sat@2 {
+				compatible = "xlnx,ams-sat";
+				reg = <0x00 0xece30000 0x00 0x10000 0x01>;
+				phandle = <0x7c>;
+			};
+
+			fpd_ams_sat@3 {
+				compatible = "xlnx,ams-sat";
+				reg = <0x00 0xecf30000 0x00 0x10000 0x01>;
+				phandle = <0x7d>;
+			};
+		};
+
+		amba_pmc_pl@0 {
+			#address-cells = <0x02>;
+			#size-cells = <0x02>;
+			#priority-cells = <0x01>;
+			compatible = "simple-bus";
+			ranges;
+			doc-name = "PMC PL";
+			doc-status = "partial";
+			phandle = <0x52>;
+
+			noc_npi_nir@0xf6000000 {
+				compatible = "xlnx.npi-nir";
+				reg = <0x00 0xf6000000 0x00 0x10000 0x01>;
+				phandle = <0x115>;
+			};
+
+			npi_ddrmc_ub0@0xf67c0000 {
+				doc-limitations = "Only the uB rst is supported";
+				compatible = "xlnx,ddrmc5_ub";
+				reg = <0x00 0xf67c0000 0x00 0x40000 0x01>;
+				reset-gpios = <0x5e 0x0f>;
+				#gpio-cells = <0x01>;
+				gpio-controller;
+				phandle = <0x116>;
+			};
+
+			npi_ddrmc_main0@0xf6790000 {
+				doc-limitations = "Just a stub";
+				compatible = "xlnx,versal-ddrmc-main";
+				reg = <0x00 0xf6790000 0x00 0x10000 0x01>;
+				reset-gpios = <0x5e 0x0f>;
+				phandle = <0xa5>;
+			};
+
+			npi_ddrmc_noc0@0xf67a0000 {
+				doc-limitations = "Just a stub";
+				compatible = "xlnx,versal-ddrmc-noc";
+				reg = <0x00 0xf67a0000 0x00 0x20000 0xffffffff>;
+				reset-gpios = <0x5e 0x0f>;
+				phandle = <0x117>;
+			};
+
+			npi_ddrmc_ub1@0xf68b0000 {
+				doc-limitations = "Only the uB rst is supported";
+				compatible = "xlnx,ddrmc5_ub";
+				reg = <0x00 0xf68b0000 0x00 0x40000 0x01>;
+				reset-gpios = <0x5e 0x0f>;
+				#gpio-cells = <0x01>;
+				gpio-controller;
+				phandle = <0x118>;
+			};
+
+			npi_ddrmc_main1@0xf6880000 {
+				doc-limitations = "Just a stub";
+				compatible = "xlnx,versal-ddrmc-main";
+				reg = <0x00 0xf6880000 0x00 0x10000 0x01>;
+				reset-gpios = <0x5e 0x0f>;
+				phandle = <0x119>;
+			};
+
+			npi_ddrmc_noc1@0xf6890000 {
+				doc-limitations = "Just a stub";
+				compatible = "xlnx,versal-ddrmc-noc";
+				reg = <0x00 0xf6890000 0x00 0x20000 0xffffffff>;
+				reset-gpios = <0x5e 0x0f>;
+				phandle = <0x11a>;
+			};
+
+			npi_ddrmc_ub2@0xf6dc0000 {
+				doc-limitations = "Only the uB rst is supported";
+				compatible = "xlnx,ddrmc5_ub";
+				reg = <0x00 0xf6dc0000 0x00 0x40000 0x01>;
+				reset-gpios = <0x5e 0x0f>;
+				#gpio-cells = <0x01>;
+				gpio-controller;
+				phandle = <0x11b>;
+			};
+
+			npi_ddrmc_main2@0xf6d90000 {
+				doc-limitations = "Just a stub";
+				compatible = "xlnx,versal-ddrmc-main";
+				reg = <0x00 0xf6d90000 0x00 0x10000 0x01>;
+				reset-gpios = <0x5e 0x0f>;
+				phandle = <0x11c>;
+			};
+
+			npi_ddrmc_noc2@0xf6da0000 {
+				doc-limitations = "Just a stub";
+				compatible = "xlnx,versal-ddrmc-noc";
+				reg = <0x00 0xf6da0000 0x00 0x20000 0xffffffff>;
+				reset-gpios = <0x5e 0x0f>;
+				phandle = <0x11d>;
+			};
+
+			npi_ddrmc_ub3@0xf6eb0000 {
+				doc-limitations = "Only the uB rst is supported";
+				compatible = "xlnx,ddrmc5_ub";
+				reg = <0x00 0xf6eb0000 0x00 0x40000 0x01>;
+				reset-gpios = <0x5e 0x0f>;
+				#gpio-cells = <0x01>;
+				gpio-controller;
+				phandle = <0x11e>;
+			};
+
+			npi_ddrmc_main3@0xf6e80000 {
+				doc-limitations = "Just a stub";
+				compatible = "xlnx,versal-ddrmc-main";
+				reg = <0x00 0xf6e80000 0x00 0x10000 0x01>;
+				reset-gpios = <0x5e 0x0f>;
+				phandle = <0x11f>;
+			};
+
+			npi_ddrmc_noc3@0xf6e90000 {
+				doc-limitations = "Just a stub";
+				compatible = "xlnx,versal-ddrmc-noc";
+				reg = <0x00 0xf6e90000 0x00 0x20000 0xffffffff>;
+				reset-gpios = <0x5e 0x0f>;
+				phandle = <0x120>;
+			};
+
+			npi_ddrmc_ub4@0xf6f70000 {
+				doc-limitations = "Only the uB rst is supported";
+				compatible = "xlnx,ddrmc5_ub";
+				reg = <0x00 0xf6f70000 0x00 0x40000 0x01>;
+				reset-gpios = <0x5e 0x0f>;
+				#gpio-cells = <0x01>;
+				gpio-controller;
+				phandle = <0x121>;
+			};
+
+			npi_ddrmc_main4@0xf6f40000 {
+				doc-limitations = "Just a stub";
+				compatible = "xlnx,versal-ddrmc-main";
+				reg = <0x00 0xf6f40000 0x00 0x10000 0x01>;
+				reset-gpios = <0x5e 0x0f>;
+				phandle = <0x122>;
+			};
+
+			npi_ddrmc_noc4@0xf6f50000 {
+				doc-limitations = "Just a stub";
+				compatible = "xlnx,versal-ddrmc-noc";
+				reg = <0x00 0xf6f50000 0x00 0x20000 0xffffffff>;
+				reset-gpios = <0x5e 0x0f>;
+				phandle = <0x123>;
+			};
+
+			npi_ddrmc_ub5@0xf7060000 {
+				doc-limitations = "Only the uB rst is supported";
+				compatible = "xlnx,ddrmc5_ub";
+				reg = <0x00 0xf7060000 0x00 0x40000 0x01>;
+				reset-gpios = <0x5e 0x0f>;
+				#gpio-cells = <0x01>;
+				gpio-controller;
+				phandle = <0x124>;
+			};
+
+			npi_ddrmc_main5@0xf7030000 {
+				doc-limitations = "Just a stub";
+				compatible = "xlnx,versal-ddrmc-main";
+				reg = <0x00 0xf7030000 0x00 0x10000 0x01>;
+				reset-gpios = <0x5e 0x0f>;
+				phandle = <0x125>;
+			};
+
+			npi_ddrmc_noc5@0xf7040000 {
+				doc-limitations = "Just a stub";
+				compatible = "xlnx,versal-ddrmc-noc";
+				reg = <0x00 0xf7040000 0x00 0x20000 0xffffffff>;
+				reset-gpios = <0x5e 0x0f>;
+				phandle = <0x126>;
+			};
+
+			npi_ddrmc_ub6@0xf7320000 {
+				doc-limitations = "Only the uB rst is supported";
+				compatible = "xlnx,ddrmc5_ub";
+				reg = <0x00 0xf7320000 0x00 0x40000 0x01>;
+				reset-gpios = <0x5e 0x0f>;
+				#gpio-cells = <0x01>;
+				gpio-controller;
+				phandle = <0x127>;
+			};
+
+			npi_ddrmc_main6@0xf72f0000 {
+				doc-limitations = "Just a stub";
+				compatible = "xlnx,versal-ddrmc-main";
+				reg = <0x00 0xf72f0000 0x00 0x10000 0x01>;
+				reset-gpios = <0x5e 0x0f>;
+				phandle = <0x128>;
+			};
+
+			npi_ddrmc_noc6@0xf7300000 {
+				doc-limitations = "Just a stub";
+				compatible = "xlnx,versal-ddrmc-noc";
+				reg = <0x00 0xf7300000 0x00 0x20000 0xffffffff>;
+				reset-gpios = <0x5e 0x0f>;
+				phandle = <0x129>;
+			};
+
+			npi_ddrmc_ub7@0xf7400000 {
+				doc-limitations = "Only the uB rst is supported";
+				compatible = "xlnx,ddrmc5_ub";
+				reg = <0x00 0xf7400000 0x00 0x40000 0x01>;
+				reset-gpios = <0x5e 0x0f>;
+				#gpio-cells = <0x01>;
+				gpio-controller;
+				phandle = <0x12a>;
+			};
+
+			npi_ddrmc_main7@0xf73d0000 {
+				doc-limitations = "Just a stub";
+				compatible = "xlnx,versal-ddrmc-main";
+				reg = <0x00 0xf73d0000 0x00 0x10000 0x01>;
+				reset-gpios = <0x5e 0x0f>;
+				phandle = <0x12b>;
+			};
+
+			npi_ddrmc_noc7@0xf73e0000 {
+				doc-limitations = "Just a stub";
+				compatible = "xlnx,versal-ddrmc-noc";
+				reg = <0x00 0xf73e0000 0x00 0x20000 0xffffffff>;
+				reset-gpios = <0x5e 0x0f>;
+				phandle = <0x12c>;
+			};
+
+			npi_ddrmc_xmpu0@0xf67a0000 {
+				compatible = "xlnx,versal-ddrmc-xmpu";
+				reg-extended = <0x52 0x00 0xf67b0000 0x00 0x10000 0x01 0x0b
+0x00 0x00 0x00 0x80000000 0x00>;
+				protected-mr = <0x7f>;
+				mr-0 = <0x0b>;
+				protected-base = <0x00>;
+				phandle = <0x12d>;
+			};
+
+			noc_npi_devs@0 {
+				compatible = "xlnx,noc-npi-dev";
+				reg = <0x00 0xf6000000 0x00 0x2000000 0x00>;
+				phandle = <0x12e>;
+			};
+
+			cfu_fdro@0xf12c2000 {
+				compatible = "xlnx,versal-cfu-fdro";
+				reg = <0x00 0xf12c2000 0x00 0x1000 0x00>;
+				phandle = <0x81>;
+			};
+
+			cfu_sfr@0xf12c1000 {
+				compatible = "xlnx,versal-cfu-sfr";
+				reg = <0x00 0xf12c1000 0x00 0x1000 0x00>;
+				cfu = <0x80>;
+				phandle = <0x12f>;
+			};
+
+			cframe0_reg@0xf12d0000 {
+				compatible = "xlnx.cframe_reg";
+				reg = <0x00 0xf12d0000 0x00 0x1000 0x00
+0x00 0xf12d1000 0x00 0x1000 0x00>;
+				interrupts = <0xb3>;
+				cfu-fdro = <0x81>;
+				blktype0-frames = <0x853f>;
+				blktype1-frames = <0xdc8>;
+				blktype2-frames = <0x3200>;
+				blktype3-frames = <0x0b>;
+				blktype4-frames = <0x05>;
+				blktype5-frames = <0x01>;
+				blktype6-frames = <0x01>;
+				phandle = <0x82>;
+			};
+
+			cframe1_reg@0xf12d2000 {
+				compatible = "xlnx.cframe_reg";
+				reg = <0x00 0xf12d2000 0x00 0x1000 0x00
+0x00 0xf12d3000 0x00 0x1000 0x00>;
+				interrupts = <0xb3>;
+				cfu-fdro = <0x81>;
+				blktype0-frames = <0x9662>;
+				blktype1-frames = <0xf01>;
+				blktype2-frames = <0x3c01>;
+				blktype3-frames = <0x0d>;
+				blktype4-frames = <0x07>;
+				blktype5-frames = <0x03>;
+				blktype6-frames = <0x01>;
+				phandle = <0x83>;
+			};
+
+			cframe2_reg@0xf12d4000 {
+				compatible = "xlnx.cframe_reg";
+				reg = <0x00 0xf12d4000 0x00 0x1000 0x00
+0x00 0xf12d5000 0x00 0x1000 0x00>;
+				interrupts = <0xb3>;
+				cfu-fdro = <0x81>;
+				blktype0-frames = <0x9662>;
+				blktype1-frames = <0xf01>;
+				blktype2-frames = <0x3c01>;
+				blktype3-frames = <0x0d>;
+				blktype4-frames = <0x07>;
+				blktype5-frames = <0x03>;
+				blktype6-frames = <0x01>;
+				phandle = <0x84>;
+			};
+
+			cframe3_reg@0xf12d6000 {
+				compatible = "xlnx.cframe_reg";
+				reg = <0x00 0xf12d6000 0x00 0x1000 0x00
+0x00 0xf12d7000 0x00 0x1000 0x00>;
+				interrupts = <0xb3>;
+				cfu-fdro = <0x81>;
+				blktype0-frames = <0x9662>;
+				blktype1-frames = <0xf01>;
+				blktype2-frames = <0x3c01>;
+				blktype3-frames = <0x0d>;
+				blktype4-frames = <0x07>;
+				blktype5-frames = <0x03>;
+				blktype6-frames = <0x01>;
+				phandle = <0x85>;
+			};
+
+			cframe4_reg@0xf12d8000 {
+				compatible = "xlnx.cframe_reg";
+				reg = <0x00 0xf12d8000 0x00 0x1000 0x00
+0x00 0xf12d9000 0x00 0x1000 0x00>;
+				interrupts = <0xb3>;
+				cfu-fdro = <0x81>;
+				phandle = <0x86>;
+			};
+
+			cframe5_reg@0xf12da000 {
+				compatible = "xlnx.cframe_reg";
+				reg = <0x00 0xf12da000 0x00 0x1000 0x00
+0x00 0xf12db000 0x00 0x1000 0x00>;
+				interrupts = <0xb3>;
+				cfu-fdro = <0x81>;
+				phandle = <0x87>;
+			};
+
+			cframe6_reg@0xf12dc000 {
+				compatible = "xlnx.cframe_reg";
+				reg = <0x00 0xf12dc000 0x00 0x1000 0x00
+0x00 0xf12dd000 0x00 0x1000 0x00>;
+				interrupts = <0xb3>;
+				cfu-fdro = <0x81>;
+				phandle = <0x88>;
+			};
+
+			cframe7_reg@0xf12de000 {
+				compatible = "xlnx.cframe_reg";
+				reg = <0x00 0xf12de000 0x00 0x1000 0x00
+0x00 0xf12df000 0x00 0x1000 0x00>;
+				interrupts = <0xb3>;
+				cfu-fdro = <0x81>;
+				phandle = <0x89>;
+			};
+
+			cframe8_reg@0xf12e0000 {
+				compatible = "xlnx.cframe_reg";
+				reg = <0x00 0xf12e0000 0x00 0x1000 0x00
+0x00 0xf12e1000 0x00 0x1000 0x00>;
+				interrupts = <0xb3>;
+				cfu-fdro = <0x81>;
+				phandle = <0x8a>;
+			};
+
+			cframe9_reg@0xf12e2000 {
+				compatible = "xlnx.cframe_reg";
+				reg = <0x00 0xf12e2000 0x00 0x1000 0x00
+0x00 0xf12e3000 0x00 0x1000 0x00>;
+				interrupts = <0xb3>;
+				cfu-fdro = <0x81>;
+				phandle = <0x8b>;
+			};
+
+			cframe10_reg@0xf12e4000 {
+				compatible = "xlnx.cframe_reg";
+				reg = <0x00 0xf12e4000 0x00 0x1000 0x00
+0x00 0xf12e5000 0x00 0x1000 0x00>;
+				interrupts = <0xb3>;
+				cfu-fdro = <0x81>;
+				phandle = <0x8c>;
+			};
+
+			cframe11_reg@0xf12e6000 {
+				compatible = "xlnx.cframe_reg";
+				reg = <0x00 0xf12e6000 0x00 0x1000 0x00
+0x00 0xf12e7000 0x00 0x1000 0x00>;
+				interrupts = <0xb3>;
+				cfu-fdro = <0x81>;
+				phandle = <0x8d>;
+			};
+
+			cframe12_reg@0xf12e8000 {
+				compatible = "xlnx.cframe_reg";
+				reg = <0x00 0xf12e8000 0x00 0x1000 0x00 0x00
+0xf12e9000 0x00 0x1000 0x00>;
+				interrupts = <0xb3>;
+				cfu-fdro = <0x81>;
+				phandle = <0x8e>;
+			};
+
+			cframe13_reg@0xf12ea000 {
+				compatible = "xlnx.cframe_reg";
+				reg = <0x00 0xf12ea000 0x00 0x1000 0x00 0x00
+0xf12eb000 0x00 0x1000 0x00>;
+				interrupts = <0xb3>;
+				cfu-fdro = <0x81>;
+				phandle = <0x8f>;
+			};
+
+			cframe14_reg@0xf12ec000 {
+				compatible = "xlnx.cframe_reg";
+				reg = <0x00 0xf12ec000 0x00 0x1000 0x00 0x00
+0xf12ed000 0x00 0x1000 0x00>;
+				interrupts = <0xb3>;
+				cfu-fdro = <0x81>;
+				phandle = <0x90>;
+			};
+
+			cframe_bcast_reg@0xf12ee000 {
+				compatible = "xlnx.cframe-bcast-reg";
+				reg = <0x00 0xf12ee000 0x00 0x1000 0x00
+0x00 0xf12ef000 0x00 0x1000 0x00>;
+				cframe0 = <0x82>;
+				cframe1 = <0x83>;
+				cframe2 = <0x84>;
+				cframe3 = <0x85>;
+				cframe4 = <0x86>;
+				cframe5 = <0x87>;
+				cframe6 = <0x88>;
+				cframe7 = <0x89>;
+				cframe8 = <0x8a>;
+				cframe9 = <0x8b>;
+				cframe10 = <0x8c>;
+				cframe11 = <0x8d>;
+				cframe12 = <0x8e>;
+				cframe13 = <0x8f>;
+				cframe14 = <0x90>;
+				phandle = <0x130>;
+			};
+
+			gtm_npi_slave_0@0xf6ca0000 {
+				compatible = "xlnx,xlnx,gtyp_npi_slave";
+				reg = <0x00 0xf6ca0000 0x00 0x20000 0x00>;
+			};
+
+			gtm_npi_slave_1@0xf6d10000 {
+				compatible = "xlnx,xlnx,gtyp_npi_slave";
+				reg = <0x00 0xf6d10000 0x00 0x20000 0x00>;
+			};
+
+			hnicx_npi_0@0xf6af0000 {
+				compatible = "xlnx,hnicx_npi";
+				reg = <0x00 0xf6af0000 0x00 0x20000 0x01>;
+				doc-limitations = "Just a stub";
+				phandle = <0x131>;
+			};
+
+			hnicx_pllpor_0@0xf6b30000 {
+				compatible = "xlnx,noc-npi-dev";
+				reg = <0x00 0xf6b30000 0x00 0x10000 0x01>;
+				custom = <0x01>;
+				pcsr-status = <0x8011>;
+				phandle = <0x132>;
+			};
+
+			dummy_cfu_mem@0xf12b0000 {
+				compatible = "qemu:memory-region";
+				phandle = <0x56>;
+
+				cfu@0x0 {
+					doc-status = "partial";
+					doc-comments = "Stub";
+					doc-limitations = "No way to extract CFRAME data.";
+					compatible = "xlnx,versal-cfu";
+					reg = <0x00 0x00 0x00 0x10000 0x00 0x00 0x10000 0x00 0x1000
+0x00 0x00 0xcd0000 0x00 0x40000 0x00>;
+					chardev = "pmc-cfu";
+					dma = <0x55>;
+					phandle = <0x80>;
+				};
+			};
+		};
+
+		amba_pmc_bat@0 {
+			#address-cells = <0x02>;
+			#size-cells = <0x02>;
+			#priority-cells = <0x01>;
+			compatible = "simple-bus";
+			ranges;
+			doc-name = "PMC BAT";
+			doc-status = "partial";
+			phandle = <0x53>;
+
+			rtc@0xf12a0000 {
+				doc-status = "complete";
+				doc-comments = "Versal PMC RTC";
+				compatible = "xlnx,zynqmp-rtc";
+				interrupts = <0xbca 0xc8 0xc9>;
+				reg = <0x00 0xf12a0000 0x00 0x10000 0x00>;
+				xlnx,version = "2.0.0";
+				phandle = <0x133>;
+			};
+		};
+
+		amba_psm@0 {
+			#address-cells = <0x02>;
+			#size-cells = <0x02>;
+			#priority-cells = <0x01>;
+			compatible = "simple-bus";
+			ranges;
+			phandle = <0x11>;
+
+			psm_ram_instr@0xebc00000 {
+				device_type = "memory";
+				compatible = "qemu:memory-region";
+				qemu,ram = <0x01>;
+				reg = <0x00 0xebc00000 0x00 0x20000 0x01>;
+				phandle = <0x134>;
+			};
+
+			psm_ram_data@0xebc20000 {
+				device_type = "memory";
+				compatible = "qemu:memory-region";
+				qemu,ram = <0x01>;
+				reg = <0x00 0xebc20000 0x00 0x8000 0x01>;
+				phandle = <0x135>;
+			};
+
+			psm_gic_proxy@0 {
+				doc-status = "complete";
+				#interrupt-cells = <0x03>;
+				interrupt-controller;
+				compatible = "xlnx,zynqmp-gicp";
+				reg = <0x00 0xebc92000 0x00 0x100 0x00>;
+				interrupt-parent = <0x07>;
+				interrupts = <0x16>;
+				max-ints = <0x100>;
+				phandle = <0x05>;
+			};
+
+			psm_global_reg@0xebc90000 {
+				compatible = "xlnx,psmx_global_reg";
+				reg = <0x00 0xebc90000 0x00 0xf000 0x00>;
+				interrupt-parent = <0x07>;
+				interrupts = <0x1c 0x1e 0x1a 0x1b 0x1f 0x18 0x19>;
+				#gpio-cells = <0x01>;
+				gpios = <0x17 0x23 0x17 0x24 0x17 0x25 0x17 0x26 0x17 0x27
+0x17 0x28 0x17 0x29 0x17 0x2a 0x17 0x2b 0x17 0x2c 0x17 0x2d 0x17 0x2e 0x17 0x2f 0x17 0x30
+0x17 0x31 0x17 0x32 0x17 0x33 0x17 0x34 0x17 0x35 0x17 0x36 0x17 0x37 0x17 0x38 0x17 0x39
+0x17 0x3a 0x17 0x3b 0x17 0x3c 0x17 0x3d 0x17 0x3e 0x17 0x3f 0x17 0x40 0x17 0x41 0x17 0x42
+0x17 0x43 0x17 0x44 0x17 0x45 0x17 0x46 0x17 0x47 0x17 0x48 0x17 0x49 0x17 0x4a 0x17 0x4b
+0x17 0x4c 0x17 0x4d 0x17 0x4e 0x17 0x4f 0x17 0x50 0x17 0x51 0x17 0x52 0x17 0x53 0x17 0x54
+0x17 0x55 0x17 0x56 0x17 0x57 0x17 0x58 0x17 0x59 0x17 0x5a 0x17 0x5b 0x17 0x5c 0x17 0x5d
+0x17 0x5e 0x17 0x5f 0x17 0x60 0x17 0x61 0x17 0x62 0x17 0x63 0x17 0x64 0x17 0x65 0x91 0x00
+0x91 0x01 0x91 0x02 0x91 0x03 0x02 0x00 0x02 0x01 0x03 0x00 0x03 0x01>;
+				gpio-controller;
+				phandle = <0xab>;
+			};
+
+			psm_err_mng@0xebc90000 {
+				compatible = "xlnx.psmx_err_reg";
+				reg = <0x00 0xebc91000 0x00 0x100 0x00>;
+				phandle = <0x136>;
+			};
+
+			psm_reset_domain@0 {
+				compatible = "qemu,reset-domain";
+				mr0 = <0x92>;
+				mr1 = <0x11>;
+				reset-gpios = <0x5e 0x07>;
+			};
+		};
+
+		amba_xram@0 {
+			#address-cells = <0x02>;
+			#size-cells = <0x02>;
+			#priority-cells = <0x01>;
+			compatible = "simple-bus";
+			ranges;
+			phandle = <0x0d>;
+
+			xram_ctrl_0 {
+				compatible = "xlnx,versal-xramc";
+				reg = <0x00 0xeb8e0000 0x00 0x10000 0x00>;
+				interrupts = <0x4f>;
+				alloc-ram = <0x00>;
+			};
+
+			xram_ctrl_1 {
+				compatible = "xlnx,versal-xramc";
+				reg = <0x00 0xeb8f0000 0x00 0x10000 0x00>;
+				interrupts = <0x4f>;
+				alloc-ram = <0x00>;
+			};
+
+			xram_ctrl_2 {
+				compatible = "xlnx,versal-xramc";
+				reg = <0x00 0xeb900000 0x00 0x10000 0x00>;
+				interrupts = <0x4f>;
+				alloc-ram = <0x00>;
+			};
+
+			xram_ctrl_3 {
+				compatible = "xlnx,versal-xramc";
+				reg = <0x00 0xeb910000 0x00 0x10000 0x00>;
+				interrupts = <0x4f>;
+				alloc-ram = <0x00>;
+			};
+		};
+
+		crf@0xec200000 {
+			compatible = "xlnx,versal-psx-crf";
+			reg-extended = <0x09 0x00 0xec200000 0x00 0x100000 0x00>;
+			gpio-controller;
+			#gpio-cells = <0x01>;
+			phandle = <0x31>;
+		};
+	};
+
+	lmb_pmc_ppu0@0 {
+		#address-cells = <0x02>;
+		#size-cells = <0x02>;
+		#priority-cells = <0x01>;
+		compatible = "simple-bus";
+		ranges;
+		doc-name = "LMB PPU0";
+		doc-status = "complete";
+		phandle = <0x7e>;
+
+		main_bus_for_pmc {
+			compatible = "qemu:memory-region";
+			alias = <0x55>;
+			reg = <0x00 0x00 0xffffffff 0xffffffff 0x00>;
+		};
+
+		pmc_rom@0xf0000000 {
+			reg = <0x00 0xf0000000 0x00 0x40000 0x01>;
+			compatible = "qemu:memory-region";
+			container = <0x7e>;
+			qemu,ram = <0x01>;
+			read-only;
+			phandle = <0x137>;
+		};
+
+		ppu0_ram@0xf0060000 {
+			reg = <0x00 0xf0060000 0x00 0x8000 0x01>;
+			compatible = "qemu:memory-region";
+			container = <0x7e>;
+			qemu,ram = <0x01>;
+			phandle = <0x138>;
+		};
+
+		io-module@00 {
+			doc-status = "complete";
+			#address-cells = <0x02>;
+			#size-cells = <0x01>;
+			#priority-cells = <0x00>;
+			compatible = "xlnx,iomodule-1.02.a\0syscon\0simple-bus";
+			container = <0x7e>;
+			priority = <0xffffffff>;
+			xlnx,freq = <0x47868c0>;
+			xlnx,instance = "iomodule_1";
+			xlnx,io-mask = <0xfffe0000>;
+			xlnx,lmb-awidth = <0x20>;
+			xlnx,lmb-dwidth = <0x20>;
+			xlnx,mask = <0xffffff80>;
+			xlnx,use-io-bus = <0x01>;
+			phandle = <0x139>;
+
+			pmc_ppu0_intc@0C {
+				#interrupt-cells = <0x01>;
+				compatible = "xlnx,io-intc-1.02.a\0xlnx,io_intc";
+				interrupt-controller;
+				interrupts-extended = <0x93 0x00>;
+				reg = <0x00 0xf008000c 0x04 0x00 0xf0080030 0x10
+0x00 0xf0080080 0x7c>;
+				xlnx,intc-addr-width = <0x20>;
+				xlnx,intc-base-vectors = <0x00>;
+				xlnx,intc-has-fast = <0x00>;
+				xlnx,intc-intr-size = <0x10>;
+				xlnx,intc-level-edge = <0x00>;
+				xlnx,intc-positive = <0xffff>;
+				xlnx,intc-use-ext-intr = <0x01>;
+				phandle = <0x66>;
+			};
+
+			pmc_ppu0_gpi@20 {
+				#gpio-cells = <0x01>;
+				gpio-controller;
+				compatible = "xlnx,io-gpi-1.02.a\0xlnx,io_gpi";
+				interrupt-parent = <0x66>;
+				interrupts = <0x0b>;
+				reg = <0x00 0xf0080020 0x04>;
+				xlnx,gpi-interrupt = <0x01>;
+				xlnx,gpi-size = <0x20>;
+				xlnx,use-gpi = <0x01>;
+				phandle = <0x13a>;
+			};
+
+			pmc_ppu0_gpi@24 {
+				#gpio-cells = <0x01>;
+				gpio-controller;
+				compatible = "xlnx,io-gpi-1.02.a\0xlnx,io_gpi";
+				interrupt-parent = <0x66>;
+				interrupts = <0x0c>;
+				reg = <0x00 0xf0080024 0x04>;
+				xlnx,gpi-interrupt = <0x01>;
+				xlnx,gpi-size = <0x20>;
+				xlnx,use-gpi = <0x01>;
+				phandle = <0x13b>;
+			};
+
+			pmc_ppu0_gpi@28 {
+				#gpio-cells = <0x01>;
+				gpio-controller;
+				compatible = "xlnx,io-gpi-1.02.a\0xlnx,io_gpi";
+				interrupt-parent = <0x66>;
+				interrupts = <0x0d>;
+				reg = <0x00 0xf0080028 0x04>;
+				xlnx,gpi-interrupt = <0x01>;
+				xlnx,gpi-size = <0x20>;
+				xlnx,use-gpi = <0x01>;
+				phandle = <0x13c>;
+			};
+
+			pmc_ppu0_gpi@2c {
+				#gpio-cells = <0x01>;
+				gpio-controller;
+				compatible = "xlnx,io-gpi-1.02.a\0xlnx,io_gpi";
+				interrupt-parent = <0x66>;
+				interrupts = <0x0e>;
+				reg = <0x00 0xf008002c 0x04>;
+				xlnx,gpi-interrupt = <0x01>;
+				xlnx,gpi-size = <0x20>;
+				xlnx,use-gpi = <0x01>;
+				phandle = <0x13d>;
+			};
+
+			pmc_ppu0_gpo@10 {
+				#gpio-cells = <0x01>;
+				gpio-controller;
+				compatible = "xlnx,io-gpo-1.02.a\0xlnx,io_gpo";
+				reg = <0x00 0xf0080010 0x04>;
+				xlnx,gpo-init = <0x00>;
+				xlnx,gpo-size = <0x09>;
+				xlnx,use-gpo = <0x01>;
+				phandle = <0x94>;
+			};
+
+			pmc_ppu0_gpo@14 {
+				#gpio-cells = <0x01>;
+				gpio-controller;
+				compatible = "xlnx,io-gpo-1.02.a\0xlnx,io_gpo";
+				reg = <0x00 0xf0080014 0x04>;
+				xlnx,gpo-init = <0x00>;
+				xlnx,gpo-size = <0x20>;
+				xlnx,use-gpo = <0x01>;
+				phandle = <0x13e>;
+			};
+
+			pmc_ppu0_gpo@18 {
+				#gpio-cells = <0x01>;
+				gpio-controller;
+				compatible = "xlnx,io-gpo-1.02.a\0xlnx,io_gpo";
+				reg = <0x00 0xf0080018 0x04>;
+				xlnx,gpo-init = <0x00>;
+				xlnx,gpo-size = <0x20>;
+				xlnx,use-gpo = <0x01>;
+				phandle = <0x13f>;
+			};
+
+			pmc_ppu0_gpo@1c {
+				#gpio-cells = <0x01>;
+				gpio-controller;
+				compatible = "xlnx,io-gpo-1.02.a\0xlnx,io_gpo";
+				reg = <0x00 0xf008001c 0x04>;
+				xlnx,gpo-init = <0x00>;
+				xlnx,gpo-size = <0x20>;
+				xlnx,use-gpo = <0x01>;
+				phandle = <0x140>;
+			};
+
+			pmc_ppu0_pit@40 {
+				compatible = "xlnx,io-pit-1.02.a\0xlnx,io_pit";
+				interrupt-parent = <0x66>;
+				interrupts = <0x03>;
+				reg = <0x00 0xf0080040 0x0c>;
+				xlnx,pit-interrupt = <0x01>;
+				xlnx,pit-prescaler = <0x09>;
+				xlnx,pit-readable = <0x01>;
+				xlnx,pit-size = <0x20>;
+				xlnx,use-pit = <0x01>;
+				frequency = <0x1b6b0b00>;
+				gpios = <0x94 0x01 0x95 0x00>;
+				gpio-names = "ps_config\0ps_hit_in";
+				gpio-controller;
+				#gpio-cells = <0x01>;
+				phandle = <0x141>;
+			};
+
+			pmc_ppu0_pit@50 {
+				compatible = "xlnx,io-pit-1.02.a\0xlnx,io_pit";
+				interrupt-parent = <0x66>;
+				interrupts = <0x04>;
+				reg = <0x00 0xf0080050 0x0c>;
+				xlnx,pit-interrupt = <0x01>;
+				xlnx,pit-prescaler = <0x09>;
+				xlnx,pit-readable = <0x01>;
+				xlnx,pit-size = <0x20>;
+				xlnx,use-pit = <0x01>;
+				frequency = <0x1b6b0b00>;
+				gpio-controller;
+				#gpio-cells = <0x01>;
+				phandle = <0x95>;
+			};
+
+			pmc_ppu0_pit@60 {
+				compatible = "xlnx,io-pit-1.02.a\0xlnx,io_pit";
+				interrupt-parent = <0x66>;
+				interrupts = <0x05>;
+				reg = <0x00 0xf0080060 0x0c>;
+				xlnx,pit-interrupt = <0x01>;
+				xlnx,pit-prescaler = <0x09>;
+				xlnx,pit-readable = <0x01>;
+				xlnx,pit-size = <0x20>;
+				xlnx,use-pit = <0x01>;
+				frequency = <0x1b6b0b00>;
+				gpios = <0x94 0x06 0x96 0x00>;
+				gpio-names = "ps_config\0ps_hit_in";
+				gpio-controller;
+				#gpio-cells = <0x01>;
+				phandle = <0x142>;
+			};
+
+			pmc_ppu0_pit@70 {
+				compatible = "xlnx,io-pit-1.02.a\0xlnx,io_pit";
+				interrupt-parent = <0x66>;
+				interrupts = <0x06>;
+				reg = <0x00 0xf0080070 0x0c>;
+				xlnx,pit-interrupt = <0x01>;
+				xlnx,pit-prescaler = <0x09>;
+				xlnx,pit-readable = <0x01>;
+				xlnx,pit-size = <0x20>;
+				xlnx,use-pit = <0x01>;
+				frequency = <0x1b6b0b00>;
+				gpio-controller;
+				#gpio-cells = <0x01>;
+				phandle = <0x96>;
+			};
+		};
+	};
+
+	lmb_pmc_ppu1@0 {
+		#address-cells = <0x02>;
+		#size-cells = <0x02>;
+		#priority-cells = <0x01>;
+		compatible = "simple-bus";
+		ranges;
+		doc-name = "LMB PPU1";
+		doc-status = "complete";
+		phandle = <0x97>;
+
+		main_bus_for_pmc {
+			compatible = "qemu:memory-region";
+			alias = <0x55>;
+			reg = <0x00 0x00 0xffffffff 0xffffffff 0x00>;
+		};
+
+		io-module@00 {
+			doc-status = "complete";
+			#address-cells = <0x02>;
+			#size-cells = <0x01>;
+			#priority-cells = <0x00>;
+			compatible = "xlnx,iomodule-1.02.a\0syscon\0simple-bus";
+			container = <0x97>;
+			priority = <0xffffffff>;
+			xlnx,freq = <0x47868c0>;
+			xlnx,instance = "iomodule_1";
+			xlnx,io-mask = <0xfffe0000>;
+			xlnx,lmb-awidth = <0x20>;
+			xlnx,lmb-dwidth = <0x20>;
+			xlnx,mask = <0xffffff80>;
+			xlnx,use-io-bus = <0x01>;
+			phandle = <0x143>;
+
+			pmc_ppu1_intc@0C {
+				#interrupt-cells = <0x01>;
+				compatible = "xlnx,io-intc-1.02.a\0xlnx,io_intc";
+				interrupt-controller;
+				interrupts-extended = <0x98 0x00>;
+				reg = <0x00 0xf030000c 0x04 0x00 0xf0300030 0x10
+0x00 0xf0300080 0x7c>;
+				xlnx,intc-addr-width = <0x20>;
+				xlnx,intc-base-vectors = <0x00>;
+				xlnx,intc-has-fast = <0x00>;
+				xlnx,intc-intr-size = <0x10>;
+				xlnx,intc-level-edge = <0x00>;
+				xlnx,intc-positive = <0xffff>;
+				xlnx,intc-use-ext-intr = <0x01>;
+				phandle = <0x06>;
+			};
+
+			pmc_ppu1_gpi@20 {
+				#gpio-cells = <0x01>;
+				gpio-controller;
+				compatible = "xlnx,io-gpi-1.02.a\0xlnx,io_gpi";
+				interrupt-parent = <0x06>;
+				interrupts = <0x0b>;
+				reg = <0x00 0xf0300020 0x04>;
+				xlnx,gpi-interrupt = <0x01>;
+				xlnx,gpi-size = <0x20>;
+				xlnx,use-gpi = <0x01>;
+				phandle = <0x144>;
+			};
+
+			pmc_ppu1_gpi@24 {
+				#gpio-cells = <0x01>;
+				gpio-controller;
+				compatible = "xlnx,io-gpi-1.02.a\0xlnx,io_gpi";
+				interrupt-parent = <0x06>;
+				interrupts = <0x0c>;
+				reg = <0x00 0xf0300024 0x04>;
+				xlnx,gpi-interrupt = <0x01>;
+				xlnx,gpi-size = <0x20>;
+				xlnx,use-gpi = <0x01>;
+				phandle = <0x145>;
+			};
+
+			pmc_ppu1_gpi@28 {
+				#gpio-cells = <0x01>;
+				gpio-controller;
+				compatible = "xlnx,io-gpi-1.02.a\0xlnx,io_gpi";
+				interrupt-parent = <0x06>;
+				interrupts = <0x0d>;
+				reg = <0x00 0xf0300028 0x04>;
+				xlnx,gpi-interrupt = <0x01>;
+				xlnx,gpi-size = <0x20>;
+				xlnx,use-gpi = <0x01>;
+				phandle = <0x146>;
+			};
+
+			pmc_ppu1_gpi@2c {
+				#gpio-cells = <0x01>;
+				gpio-controller;
+				compatible = "xlnx,io-gpi-1.02.a\0xlnx,io_gpi";
+				interrupt-parent = <0x06>;
+				interrupts = <0x0e>;
+				reg = <0x00 0xf030002c 0x04>;
+				xlnx,gpi-interrupt = <0x01>;
+				xlnx,gpi-size = <0x20>;
+				xlnx,use-gpi = <0x01>;
+				phandle = <0x147>;
+			};
+
+			pmc_ppu1_gpo@10 {
+				#gpio-cells = <0x01>;
+				gpio-controller;
+				compatible = "xlnx,io-gpo-1.02.a\0xlnx,io_gpo";
+				reg = <0x00 0xf0300010 0x04>;
+				xlnx,gpo-init = <0x00>;
+				xlnx,gpo-size = <0x09>;
+				xlnx,use-gpo = <0x01>;
+				phandle = <0x99>;
+			};
+
+			pmc_ppu1_gpo@14 {
+				#gpio-cells = <0x01>;
+				gpio-controller;
+				compatible = "xlnx,io-gpo-1.02.a\0xlnx,io_gpo";
+				reg = <0x00 0xf0300014 0x04>;
+				xlnx,gpo-init = <0x00>;
+				xlnx,gpo-size = <0x20>;
+				xlnx,use-gpo = <0x01>;
+				phandle = <0x148>;
+			};
+
+			pmc_ppu1_gpo@18 {
+				#gpio-cells = <0x01>;
+				gpio-controller;
+				compatible = "xlnx,io-gpo-1.02.a\0xlnx,io_gpo";
+				reg = <0x00 0xf0300018 0x04>;
+				xlnx,gpo-init = <0x00>;
+				xlnx,gpo-size = <0x20>;
+				xlnx,use-gpo = <0x01>;
+				phandle = <0x149>;
+			};
+
+			pmc_ppu1_gpo@1c {
+				#gpio-cells = <0x01>;
+				gpio-controller;
+				compatible = "xlnx,io-gpo-1.02.a\0xlnx,io_gpo";
+				reg = <0x00 0xf030001c 0x04>;
+				xlnx,gpo-init = <0x00>;
+				xlnx,gpo-size = <0x20>;
+				xlnx,use-gpo = <0x01>;
+				phandle = <0x14a>;
+			};
+
+			pmc_ppu1_pit@40 {
+				compatible = "xlnx,io-pit-1.02.a\0xlnx,io_pit";
+				interrupt-parent = <0x06>;
+				interrupts = <0x03>;
+				reg = <0x00 0xf0300040 0x0c>;
+				xlnx,pit-interrupt = <0x01>;
+				xlnx,pit-prescaler = <0x09>;
+				xlnx,pit-readable = <0x01>;
+				xlnx,pit-size = <0x20>;
+				xlnx,use-pit = <0x01>;
+				frequency = <0x5f5e100>;
+				gpios = <0x99 0x01 0x9a 0x00>;
+				gpio-names = "ps_config\0ps_hit_in";
+				gpio-controller;
+				#gpio-cells = <0x01>;
+				phandle = <0x14b>;
+			};
+
+			pmc_ppu1_pit@50 {
+				compatible = "xlnx,io-pit-1.02.a\0xlnx,io_pit";
+				interrupt-parent = <0x06>;
+				interrupts = <0x04>;
+				reg = <0x00 0xf0300050 0x0c>;
+				xlnx,pit-interrupt = <0x01>;
+				xlnx,pit-prescaler = <0x09>;
+				xlnx,pit-readable = <0x01>;
+				xlnx,pit-size = <0x20>;
+				xlnx,use-pit = <0x01>;
+				frequency = <0x5f5e100>;
+				gpio-controller;
+				#gpio-cells = <0x01>;
+				phandle = <0x9a>;
+			};
+
+			pmc_ppu1_pit@60 {
+				compatible = "xlnx,io-pit-1.02.a\0xlnx,io_pit";
+				interrupt-parent = <0x06>;
+				interrupts = <0x05>;
+				reg = <0x00 0xf0300060 0x0c>;
+				xlnx,pit-interrupt = <0x01>;
+				xlnx,pit-prescaler = <0x09>;
+				xlnx,pit-readable = <0x01>;
+				xlnx,pit-size = <0x20>;
+				xlnx,use-pit = <0x01>;
+				frequency = <0x5f5e100>;
+				gpios = <0x99 0x06 0x9b 0x00>;
+				gpio-names = "ps_config\0ps_hit_in";
+				gpio-controller;
+				#gpio-cells = <0x01>;
+				windows-frequency = <0x13d620>;
+				phandle = <0x14c>;
+			};
+
+			pmc_ppu1_pit@70 {
+				compatible = "xlnx,io-pit-1.02.a\0xlnx,io_pit";
+				interrupt-parent = <0x06>;
+				interrupts = <0x06>;
+				reg = <0x00 0xf0300070 0x0c>;
+				xlnx,pit-interrupt = <0x01>;
+				xlnx,pit-prescaler = <0x09>;
+				xlnx,pit-readable = <0x01>;
+				xlnx,pit-size = <0x20>;
+				xlnx,use-pit = <0x01>;
+				frequency = <0x5f5e100>;
+				gpio-controller;
+				#gpio-cells = <0x01>;
+				phandle = <0x9b>;
+			};
+		};
+	};
+
+	lmb_psm@0 {
+		#address-cells = <0x02>;
+		#size-cells = <0x02>;
+		#priority-cells = <0x01>;
+		compatible = "simple-bus";
+		ranges;
+		doc-name = "LMB PPU0";
+		doc-status = "in-progress";
+		phandle = <0x92>;
+
+		downstream_amba {
+			compatible = "qemu:memory-region";
+			alias = <0x0b>;
+			reg = <0x00 0x00 0xffffffff 0xffffffff 0xffffffff>;
+		};
+
+		main_bus_for_pmc {
+			compatible = "qemu:memory-region";
+			alias = <0x11>;
+			reg = <0x00 0x00 0xffffffff 0xffffffff 0x00>;
+		};
+
+		io-module@00 {
+			doc-status = "complete";
+			#address-cells = <0x02>;
+			#size-cells = <0x01>;
+			#priority-cells = <0x00>;
+			compatible = "simple-bus";
+			priority = <0xffffffff>;
+			container = <0x92>;
+			phandle = <0x14d>;
+
+			psm0_intc@0C {
+				#interrupt-cells = <0x01>;
+				compatible = "xlnx,io-intc-1.02.a\0xlnx,io_intc";
+				interrupt-controller;
+				interrupts-extended = <0x93 0x00>;
+				reg = <0x00 0xebc8000c 0x04 0x00 0xebc80030 0x10
+0x00 0xebc80080 0x7c>;
+				xlnx,intc-addr-width = <0x20>;
+				xlnx,intc-base-vectors = <0x00>;
+				xlnx,intc-has-fast = <0x00>;
+				xlnx,intc-intr-size = <0x10>;
+				xlnx,intc-level-edge = <0x00>;
+				xlnx,intc-positive = <0xffff>;
+				xlnx,intc-use-ext-intr = <0x01>;
+				phandle = <0x07>;
+			};
+
+			psm0_gpo@10 {
+				#gpio-cells = <0x01>;
+				gpio-controller;
+				compatible = "xlnx,io-gpo-1.02.a\0xlnx,io_gpo";
+				reg = <0x00 0xebc80010 0x04>;
+				xlnx,gpo-init = <0x00>;
+				xlnx,gpo-size = <0x03>;
+				xlnx,use-gpo = <0x01>;
+				phandle = <0x9c>;
+			};
+
+			psm0_pit@40 {
+				compatible = "xlnx,io-pit-1.02.a\0xlnx,io_pit";
+				interrupt-parent = <0x07>;
+				interrupts = <0x03>;
+				reg = <0x00 0xebc80040 0x0c>;
+				xlnx,pit-interrupt = <0x01>;
+				xlnx,pit-prescaler = <0x09>;
+				xlnx,pit-readable = <0x01>;
+				xlnx,pit-size = <0x20>;
+				xlnx,use-pit = <0x01>;
+				frequency = <0x1b6b0b00>;
+				gpios = <0x9c 0x01 0x9d 0x00>;
+				gpio-names = "ps_config\0ps_hit_in";
+				gpio-controller;
+				#gpio-cells = <0x01>;
+				phandle = <0x14e>;
+			};
+
+			psm0_pit@50 {
+				compatible = "xlnx,io-pit-1.02.a\0xlnx,io_pit";
+				interrupt-parent = <0x07>;
+				interrupts = <0x04>;
+				reg = <0x00 0xebc80050 0x0c>;
+				xlnx,pit-interrupt = <0x01>;
+				xlnx,pit-prescaler = <0x09>;
+				xlnx,pit-readable = <0x01>;
+				xlnx,pit-size = <0x20>;
+				xlnx,use-pit = <0x01>;
+				frequency = <0x1b6b0b00>;
+				gpio-controller;
+				#gpio-cells = <0x01>;
+				phandle = <0x9d>;
+			};
+
+			psm0_pit@60 {
+				compatible = "xlnx,io-pit-1.02.a\0xlnx,io_pit";
+				interrupt-parent = <0x07>;
+				interrupts = <0x05>;
+				reg = <0x00 0xebc80060 0x0c>;
+				xlnx,pit-interrupt = <0x01>;
+				xlnx,pit-prescaler = <0x09>;
+				xlnx,pit-readable = <0x01>;
+				xlnx,pit-size = <0x20>;
+				xlnx,use-pit = <0x01>;
+				frequency = <0x1b6b0b00>;
+				gpios = <0x9c 0x06 0x9e 0x00>;
+				gpio-names = "ps_config\0ps_hit_in";
+				gpio-controller;
+				#gpio-cells = <0x01>;
+				phandle = <0x14f>;
+			};
+
+			psm0_pit@70 {
+				compatible = "xlnx,io-pit-1.02.a\0xlnx,io_pit";
+				interrupt-parent = <0x07>;
+				interrupts = <0x06>;
+				reg = <0x00 0xebc80070 0x0c>;
+				xlnx,pit-interrupt = <0x01>;
+				xlnx,pit-prescaler = <0x09>;
+				xlnx,pit-readable = <0x01>;
+				xlnx,pit-size = <0x20>;
+				xlnx,use-pit = <0x01>;
+				frequency = <0x1b6b0b00>;
+				gpio-controller;
+				#gpio-cells = <0x01>;
+				phandle = <0x9e>;
+			};
+		};
+
+		psm_local_reg@0xebc88000 {
+			gpio-controller;
+			#gpio-cells = <0x01>;
+			compatible = "xlnx,psmx_local_reg";
+			reg = <0x00 0xebc88000 0x00 0x8000 0x00>;
+			phandle = <0x17>;
+		};
+	};
+
+	lmb_ddrmc@0 {
+		#address-cells = <0x02>;
+		#size-cells = <0x02>;
+		#priority-cells = <0x01>;
+		compatible = "simple-bus";
+		ranges;
+		doc-name = "LMB DDRMC0";
+		doc-status = "partial";
+		phandle = <0x9f>;
+
+		ddrmc0_ram_data@0x1c000 {
+			reg = <0x00 0x1c000 0x00 0x4000 0x01>;
+			compatible = "qemu:memory-region";
+			qemu,ram = <0x01>;
+			phandle = <0x150>;
+		};
+
+		ddrmc0_ram_instr@0x20000 {
+			reg = <0x00 0x20000 0x00 0x20000 0x01>;
+			compatible = "qemu:memory-region";
+			qemu,ram = <0x01>;
+			phandle = <0x151>;
+		};
+
+		ddrmc0_ram_exchange@0x08000 {
+			reg = <0x00 0x8000 0x00 0x8000 0x01>;
+			compatible = "qemu:memory-region";
+			qemu,ram = <0x01>;
+			phandle = <0x152>;
+		};
+
+		io-module@00 {
+			doc-status = "complete";
+			#address-cells = <0x02>;
+			#size-cells = <0x01>;
+			#priority-cells = <0x00>;
+			compatible = "simple-bus";
+			container = <0x9f>;
+			priority = <0xffffffff>;
+			phandle = <0x153>;
+
+			ddrmc0_intc@0C {
+				#interrupt-cells = <0x01>;
+				compatible = "xlnx,io-intc-1.02.a\0xlnx,io_intc";
+				interrupt-controller;
+				interrupts-extended = <0xa0 0x00>;
+				reg = <0x00 0x1b00c 0x04 0x00 0x1b030 0x10 0x00 0x1b080 0x7c>;
+				xlnx,intc-addr-width = <0x20>;
+				xlnx,intc-base-vectors = <0x00>;
+				xlnx,intc-has-fast = <0x00>;
+				xlnx,intc-intr-size = <0x10>;
+				xlnx,intc-level-edge = <0x00>;
+				xlnx,intc-positive = <0xffff>;
+				xlnx,intc-use-ext-intr = <0x01>;
+				phandle = <0xa1>;
+			};
+
+			ddrmc0_gpo@10 {
+				#gpio-cells = <0x01>;
+				gpio-controller;
+				compatible = "xlnx,io-gpo-1.02.a\0xlnx,io_gpo";
+				reg = <0x00 0x1b010 0x04>;
+				xlnx,gpo-init = <0x00>;
+				xlnx,gpo-size = <0x03>;
+				xlnx,use-gpo = <0x01>;
+				phandle = <0xa2>;
+			};
+
+			ddrmc0_pit@40 {
+				compatible = "xlnx,io-pit-1.02.a\0xlnx,io_pit";
+				interrupt-parent = <0xa1>;
+				interrupts = <0x03>;
+				reg = <0x00 0x1b040 0x0c>;
+				xlnx,pit-interrupt = <0x01>;
+				xlnx,pit-prescaler = <0x09>;
+				xlnx,pit-readable = <0x01>;
+				xlnx,pit-size = <0x20>;
+				xlnx,use-pit = <0x01>;
+				frequency = <0x1b6b0b00>;
+				gpios = <0xa2 0x01 0xa3 0x00>;
+				gpio-names = "ps_config\0ps_hit_in";
+				gpio-controller;
+				#gpio-cells = <0x01>;
+				phandle = <0x154>;
+			};
+
+			ddrmc0_pit@50 {
+				compatible = "xlnx,io-pit-1.02.a\0xlnx,io_pit";
+				interrupt-parent = <0xa1>;
+				interrupts = <0x04>;
+				reg = <0x00 0x1b050 0x0c>;
+				xlnx,pit-interrupt = <0x01>;
+				xlnx,pit-prescaler = <0x09>;
+				xlnx,pit-readable = <0x01>;
+				xlnx,pit-size = <0x20>;
+				xlnx,use-pit = <0x01>;
+				frequency = <0x1b6b0b00>;
+				gpio-controller;
+				#gpio-cells = <0x01>;
+				phandle = <0xa3>;
+			};
+
+			ddrmc0_pit@60 {
+				compatible = "xlnx,io-pit-1.02.a\0xlnx,io_pit";
+				interrupt-parent = <0xa1>;
+				interrupts = <0x05>;
+				reg = <0x00 0x1b060 0x0c>;
+				xlnx,pit-interrupt = <0x01>;
+				xlnx,pit-prescaler = <0x09>;
+				xlnx,pit-readable = <0x01>;
+				xlnx,pit-size = <0x20>;
+				xlnx,use-pit = <0x01>;
+				frequency = <0x1b6b0b00>;
+				gpios = <0xa2 0x06 0xa4 0x00>;
+				gpio-names = "ps_config\0ps_hit_in";
+				gpio-controller;
+				#gpio-cells = <0x01>;
+				phandle = <0x155>;
+			};
+
+			ddrmc0_pit@70 {
+				compatible = "xlnx,io-pit-1.02.a\0xlnx,io_pit";
+				interrupt-parent = <0xa1>;
+				interrupts = <0x06>;
+				reg = <0x00 0x1b070 0x0c>;
+				xlnx,pit-interrupt = <0x01>;
+				xlnx,pit-prescaler = <0x09>;
+				xlnx,pit-readable = <0x01>;
+				xlnx,pit-size = <0x20>;
+				xlnx,use-pit = <0x01>;
+				frequency = <0x1b6b0b00>;
+				gpio-controller;
+				#gpio-cells = <0x01>;
+				phandle = <0xa4>;
+			};
+		};
+
+		ddrmc_uart0@0 {
+			compatible = "xlnx,io_uart";
+			reg = <0x00 0x1b000 0x0c 0x1b04c 0x04>;
+			xlnx,use-uart-rx = <0x01>;
+			xlnx,use-uart-tx = <0x01>;
+			chardev = "ddrmc-uart0\0serial1";
+			phandle = <0x156>;
+		};
+
+		alias_npi_ddrmc_main {
+			compatible = "qemu:memory-region";
+			alias = <0xa5>;
+			reg = <0x00 0x00 0x00 0x8000 0x00>;
+		};
+	};
+
+	lmb_ddrmc@1 {
+		#address-cells = <0x02>;
+		#size-cells = <0x02>;
+		#priority-cells = <0x01>;
+		compatible = "simple-bus";
+		ranges;
+		phandle = <0x157>;
+
+		ddrmc1_ram_data@0x1c000 {
+			reg = <0x00 0x1c000 0x00 0x4000 0x01>;
+			compatible = "qemu:memory-region";
+			qemu,ram = <0x01>;
+			phandle = <0x158>;
+		};
+
+		ddrmc1_ram_instr@0x20000 {
+			reg = <0x00 0x20000 0x00 0x20000 0x01>;
+			compatible = "qemu:memory-region";
+			qemu,ram = <0x01>;
+			phandle = <0x159>;
+		};
+
+		ddrmc1_ram_exchange@0x08000 {
+			reg = <0x00 0x8000 0x00 0x8000 0x01>;
+			compatible = "qemu:memory-region";
+			qemu,ram = <0x01>;
+			phandle = <0x15a>;
+		};
+	};
+
+	amba_rpu@0 {
+		#address-cells = <0x02>;
+		#size-cells = <0x02>;
+		#priority-cells = <0x01>;
+		compatible = "simple-bus";
+		ranges;
+		phandle = <0xa6>;
+
+		downstream_amba {
+			compatible = "qemu:memory-region";
+			alias = <0x0b>;
+			reg = <0x00 0x00 0xffffffff 0xffffffff 0x00>;
+		};
+
+		timer_a {
+			compatible = "arm,armv8-timer";
+			interrupt-parent = <0x02>;
+			interrupts = <0x01 0x0e 0x301 0x01 0x0b 0x301 0x01 0x0a 0x301>;
+			clock-frequency = <0x5f5e100>;
+		};
+
+		timer_b {
+			compatible = "arm,armv8-timer";
+			interrupt-parent = <0x03>;
+			interrupts = <0x01 0x0e 0x301 0x01 0x0b 0x301 0x01 0x0a 0x301>;
+			clock-frequency = <0x5f5e100>;
+		};
+	};
+
+	amba_r5@0 {
+		#address-cells = <0x02>;
+		#size-cells = <0x02>;
+		#priority-cells = <0x01>;
+		compatible = "simple-bus";
+		ranges;
+		phandle = <0xac>;
+
+		downstream_amba {
+			compatible = "qemu:memory-region";
+			alias = <0xa6>;
+			reg = <0x00 0x00 0xffffffff 0xffffffff 0x00>;
+		};
+
+		downstream_tcm {
+			compatible = "qemu:memory-region";
+			alias = <0xa7>;
+			reg = <0x00 0x00 0x00 0x400000 0x01>;
+		};
+
+		downstream_gic0 {
+			compatible = "qemu:memory-region";
+			alias = <0xa8>;
+			reg = <0x00 0xe2000000 0x00 0x140000 0x01>;
+		};
+	};
+
+	amba_r5@1 {
+		#address-cells = <0x02>;
+		#size-cells = <0x02>;
+		#priority-cells = <0x01>;
+		compatible = "simple-bus";
+		ranges;
+		phandle = <0xaf>;
+
+		downstream_amba {
+			compatible = "qemu:memory-region";
+			alias = <0xa6>;
+			reg = <0x00 0x00 0xffffffff 0xffffffff 0x00>;
+		};
+
+		downstream_tcm {
+			compatible = "qemu:memory-region";
+			alias = <0xa9>;
+			reg = <0x00 0x00 0x00 0x400000 0x01>;
+		};
+
+		downstream_gic0 {
+			compatible = "qemu:memory-region";
+			alias = <0xa8>;
+			reg = <0x00 0xe2000000 0x00 0x140000 0x01>;
+		};
+	};
+
+	dummy1@0 {
+		doc-ignore = <0x01>;
+		interrupt-controller;
+		#interrupt-cells = <0x01>;
+		gpio-controller;
+		#gpio-cells = <0x01>;
+		phandle = <0x72>;
+	};
+
+	tbu0_slave@0 {
+		#address-cells = <0x02>;
+		#size-cells = <0x02>;
+		#priority-cells = <0x01>;
+		compatible = "simple-bus";
+		ranges;
+		phandle = <0x13>;
+	};
+
+	tbu1_slave@0 {
+		#address-cells = <0x02>;
+		#size-cells = <0x02>;
+		#priority-cells = <0x01>;
+		compatible = "simple-bus";
+		ranges;
+		phandle = <0x42>;
+	};
+
+	tbu2_slave@0 {
+		#address-cells = <0x02>;
+		#size-cells = <0x02>;
+		#priority-cells = <0x01>;
+		compatible = "simple-bus";
+		ranges;
+		phandle = <0x43>;
+	};
+
+	tbu3_slave@0 {
+		#address-cells = <0x02>;
+		#size-cells = <0x02>;
+		#priority-cells = <0x01>;
+		compatible = "simple-bus";
+		ranges;
+		phandle = <0x44>;
+	};
+
+	tbu4_slave@0 {
+		#address-cells = <0x02>;
+		#size-cells = <0x02>;
+		#priority-cells = <0x01>;
+		compatible = "simple-bus";
+		ranges;
+		phandle = <0x45>;
+	};
+
+	tbu5_slave@0 {
+		#address-cells = <0x02>;
+		#size-cells = <0x02>;
+		#priority-cells = <0x01>;
+		compatible = "simple-bus";
+		ranges;
+		phandle = <0x46>;
+	};
+
+	tbu6_slave@0 {
+		#address-cells = <0x02>;
+		#size-cells = <0x02>;
+		#priority-cells = <0x01>;
+		compatible = "simple-bus";
+		ranges;
+		phandle = <0x47>;
+	};
+
+	memory@00000000 {
+		compatible = "qemu:memory-region";
+		device_type = "memory";
+		container = <0x0b>;
+		phandle = <0xb9>;
+	};
+
+	memory@8_0000_0000 {
+		compatible = "qemu:memory-region";
+		device_type = "memory";
+		container = <0x0b>;
+		phandle = <0xba>;
+	};
+
+	memory@0x50000000000ULL {
+		compatible = "qemu:memory-region";
+		device_type = "memory";
+		container = <0x0b>;
+		phandle = <0x15b>;
+	};
+
+	ocm_mem@0xbbf00000 {
+		compatible = "qemu:memory-region";
+		phandle = <0x0c>;
+	};
+
+	ocm_mem_bank_0@ {
+		compatible = "qemu:memory-region";
+		container = <0x0c>;
+		qemu,ram = <0x01>;
+		reg = <0x00 0x00 0x00 0x20000 0x00>;
+		phandle = <0x15c>;
+	};
+
+	ocm_mem_bank_1@ {
+		compatible = "qemu:memory-region";
+		container = <0x0c>;
+		qemu,ram = <0x01>;
+		reg = <0x00 0x20000 0x00 0x20000 0x00>;
+		phandle = <0x15d>;
+	};
+
+	ocm_mem_bank_2@ {
+		compatible = "qemu:memory-region";
+		container = <0x0c>;
+		qemu,ram = <0x01>;
+		reg = <0x00 0x40000 0x00 0x20000 0x00>;
+		phandle = <0x15e>;
+	};
+
+	ocm_mem_bank_3@ {
+		compatible = "qemu:memory-region";
+		container = <0x0c>;
+		qemu,ram = <0x01>;
+		reg = <0x00 0x60000 0x00 0x20000 0x00>;
+		phandle = <0x15f>;
+	};
+
+	xram_mem@0xea800000 {
+		compatible = "qemu:memory-region";
+		phandle = <0x0e>;
+	};
+
+	xram_mem_bank_0@0x0 {
+		compatible = "qemu:memory-region";
+		container = <0x0e>;
+		qemu,ram = <0x01>;
+		reg = <0x00 0x00 0x00 0x200000 0x00>;
+		phandle = <0x160>;
+	};
+
+	xram_mem_bank_1@0x200000 {
+		compatible = "qemu:memory-region";
+		container = <0x0e>;
+		qemu,ram = <0x01>;
+		reg = <0x00 0x200000 0x00 0x200000 0x00>;
+		phandle = <0x161>;
+	};
+
+	xram_mem_bank_2@0x400000 {
+		compatible = "qemu:memory-region";
+		container = <0x0e>;
+		qemu,ram = <0x01>;
+		reg = <0x00 0x400000 0x00 0x200000 0x00>;
+		phandle = <0x162>;
+	};
+
+	xram_mem_bank_3@0x600000 {
+		compatible = "qemu:memory-region";
+		container = <0x0e>;
+		qemu,ram = <0x01>;
+		reg = <0x00 0x600000 0x00 0x200000 0x00>;
+		phandle = <0x163>;
+	};
+
+	ipi_msgbuf@0 {
+		compatible = "qemu:memory-region";
+		device_type = "memory";
+		container = <0x08>;
+		qemu,ram = <0x01>;
+		reg = <0x00 0xeb3f0000 0x00 0x1000 0x00>;
+		phandle = <0x164>;
+	};
+
+	pmc_ram@0xf2000000 {
+		compatible = "qemu:memory-region";
+		phandle = <0x54>;
+	};
+
+	pmc_ram_bank_0@0x0 {
+		compatible = "qemu:memory-region";
+		container = <0x54>;
+		qemu,ram = <0x01>;
+		reg = <0x00 0x00 0x00 0x20000 0x00>;
+		phandle = <0x165>;
+	};
+
+	pmc_ppu1_ram@0xf0200000 {
+		compatible = "qemu:memory-region";
+		container = <0x0b>;
+		qemu,ram = <0x01>;
+		reg = <0x00 0xf0200000 0x00 0x80000 0x00>;
+		phandle = <0x166>;
+	};
+
+	pmc_ppu1_ram@0xf0280000 {
+		compatible = "qemu:memory-region";
+		container = <0x0b>;
+		qemu,ram = <0x01>;
+		reg = <0x00 0xf0280000 0x00 0x20000 0x00>;
+		phandle = <0x167>;
+	};
+
+	ppu0_mdm_uart@0xf0110000 {
+		doc-status = "complete";
+		compatible = "xlnx,xps-uartlite";
+		reg-extended = <0x7e 0x00 0xf0110000 0x00 0x10 0x01>;
+		chardev = "serial0";
+	};
+
+	ppu1_mdm_uart@0xf0310000 {
+		doc-status = "complete";
+		compatible = "xlnx,xps-uartlite";
+		reg-extended = <0x97 0x00 0xf0310000 0x00 0x10 0x01>;
+		chardev = "serial1";
+	};
+
+	lqspi_mr@0 {
+		#address-cells = <0x02>;
+		#size-cells = <0x02>;
+		#priority-cells = <0x01>;
+		compatible = "simple-bus";
+		ranges;
+		phandle = <0x60>;
+	};
+
+	lospi_mr@0 {
+		#address-cells = <0x02>;
+		#size-cells = <0x02>;
+		#priority-cells = <0x01>;
+		compatible = "simple-bus";
+		ranges;
+		phandle = <0x62>;
+	};
+
+	cpus {
+		#address-cells = <0x01>;
+		#size-cells = <0x00>;
+
+		apu_cpu@0 {
+			compatible = "cortex-a78-arm-cpu";
+			device_type = "cpu";
+			arm,ccsidr0 = <0x701fe00a>;
+			arm,ccsidr1 = <0x201fe012>;
+			reg = <0x00>;
+			core-count = <0x04>;
+			arm,reset-hivecs = <0x01>;
+			arm,rvbar = <0xffff0000>;
+			arm,reset-cbar = <0xe2060000>;
+			mr = <0xaa>;
+			memory = <0xaa>;
+			qemu,halt = <0x01>;
+			gdb-id = "Cortex-A78 0";
+			#interrupt-cells = <0x01>;
+			reset-gpios = <0x31 0x00>;
+			gpios = <0xab 0x43>;
+			gpio-names = "wfi";
+			power-gpios = <0x17 0x00>;
+			mp-affinity = <0x00>;
+			generic-timer-frequency = <0x5f5e100>;
+			phandle = <0x32>;
+		};
+
+		apu_cpu@1 {
+			compatible = "cortex-a78-arm-cpu";
+			device_type = "cpu";
+			arm,ccsidr0 = <0x701fe00a>;
+			arm,ccsidr1 = <0x201fe012>;
+			reg = <0x01>;
+			core-count = <0x04>;
+			arm,reset-hivecs = <0x01>;
+			arm,rvbar = <0xffff0000>;
+			arm,reset-cbar = <0xe2060000>;
+			mr = <0xaa>;
+			memory = <0xaa>;
+			qemu,halt = <0x01>;
+			gdb-id = "Cortex-A78 1";
+			#interrupt-cells = <0x01>;
+			direct-lnx-start-powered-off = <0x01>;
+			start-powered-off = <0x00>;
+			reset-gpios = <0x31 0x01>;
+			gpios = <0xab 0x44>;
+			gpio-names = "wfi";
+			power-gpios = <0x17 0x01>;
+			mp-affinity = <0x100>;
+			generic-timer-frequency = <0x5f5e100>;
+			phandle = <0x33>;
+		};
+
+		apu_cpu@2 {
+			compatible = "cortex-a78-arm-cpu";
+			device_type = "cpu";
+			arm,ccsidr0 = <0x701fe00a>;
+			arm,ccsidr1 = <0x201fe012>;
+			reg = <0x02>;
+			core-count = <0x04>;
+			arm,reset-hivecs = <0x01>;
+			arm,rvbar = <0xffff0000>;
+			arm,reset-cbar = <0xe2060000>;
+			mr = <0xaa>;
+			memory = <0xaa>;
+			qemu,halt = <0x01>;
+			gdb-id = "Cortex-A78 2";
+			#interrupt-cells = <0x01>;
+			direct-lnx-start-powered-off = <0x01>;
+			start-powered-off = <0x00>;
+			reset-gpios = <0x31 0x02>;
+			gpios = <0xab 0x45>;
+			gpio-names = "wfi";
+			power-gpios = <0x17 0x02>;
+			mp-affinity = <0x200>;
+			generic-timer-frequency = <0x5f5e100>;
+			phandle = <0x34>;
+		};
+
+		apu_cpu@3 {
+			compatible = "cortex-a78-arm-cpu";
+			device_type = "cpu";
+			arm,ccsidr0 = <0x701fe00a>;
+			arm,ccsidr1 = <0x201fe012>;
+			reg = <0x03>;
+			core-count = <0x04>;
+			arm,reset-hivecs = <0x01>;
+			arm,rvbar = <0xffff0000>;
+			arm,reset-cbar = <0xe2060000>;
+			mr = <0xaa>;
+			memory = <0xaa>;
+			qemu,halt = <0x01>;
+			gdb-id = "Cortex-A78 3";
+			#interrupt-cells = <0x01>;
+			direct-lnx-start-powered-off = <0x01>;
+			start-powered-off = <0x00>;
+			reset-gpios = <0x31 0x03>;
+			gpios = <0xab 0x46>;
+			gpio-names = "wfi";
+			power-gpios = <0x17 0x03>;
+			mp-affinity = <0x300>;
+			generic-timer-frequency = <0x5f5e100>;
+			phandle = <0x35>;
+		};
+
+		apu_cpu@4 {
+			compatible = "cortex-a78-arm-cpu";
+			device_type = "cpu";
+			arm,ccsidr0 = <0x701fe00a>;
+			arm,ccsidr1 = <0x201fe012>;
+			reg = <0x04>;
+			core-count = <0x04>;
+			arm,reset-hivecs = <0x01>;
+			arm,rvbar = <0xffff0000>;
+			arm,reset-cbar = <0xe2060000>;
+			mr = <0xaa>;
+			memory = <0xaa>;
+			qemu,halt = <0x01>;
+			gdb-id = "Cortex-A78 4";
+			#interrupt-cells = <0x01>;
+			direct-lnx-start-powered-off = <0x01>;
+			start-powered-off = <0x00>;
+			reset-gpios = <0x31 0x04>;
+			gpios = <0xab 0x47>;
+			gpio-names = "wfi";
+			power-gpios = <0x17 0x04>;
+			mp-affinity = <0x10000>;
+			generic-timer-frequency = <0x5f5e100>;
+			phandle = <0x36>;
+		};
+
+		apu_cpu@5 {
+			compatible = "cortex-a78-arm-cpu";
+			device_type = "cpu";
+			arm,ccsidr0 = <0x701fe00a>;
+			arm,ccsidr1 = <0x201fe012>;
+			reg = <0x05>;
+			core-count = <0x04>;
+			arm,reset-hivecs = <0x01>;
+			arm,rvbar = <0xffff0000>;
+			arm,reset-cbar = <0xe2060000>;
+			mr = <0xaa>;
+			memory = <0xaa>;
+			qemu,halt = <0x01>;
+			gdb-id = "Cortex-A78 5";
+			#interrupt-cells = <0x01>;
+			direct-lnx-start-powered-off = <0x01>;
+			start-powered-off = <0x00>;
+			reset-gpios = <0x31 0x05>;
+			gpios = <0xab 0x48>;
+			gpio-names = "wfi";
+			power-gpios = <0x17 0x05>;
+			mp-affinity = <0x10100>;
+			generic-timer-frequency = <0x5f5e100>;
+			phandle = <0x37>;
+		};
+
+		apu_cpu@6 {
+			compatible = "cortex-a78-arm-cpu";
+			device_type = "cpu";
+			arm,ccsidr0 = <0x701fe00a>;
+			arm,ccsidr1 = <0x201fe012>;
+			reg = <0x06>;
+			core-count = <0x04>;
+			arm,reset-hivecs = <0x01>;
+			arm,rvbar = <0xffff0000>;
+			arm,reset-cbar = <0xe2060000>;
+			mr = <0xaa>;
+			memory = <0xaa>;
+			qemu,halt = <0x01>;
+			gdb-id = "Cortex-A78 6";
+			#interrupt-cells = <0x01>;
+			direct-lnx-start-powered-off = <0x01>;
+			start-powered-off = <0x00>;
+			reset-gpios = <0x31 0x06>;
+			gpios = <0xab 0x49>;
+			gpio-names = "wfi";
+			power-gpios = <0x17 0x06>;
+			mp-affinity = <0x10200>;
+			generic-timer-frequency = <0x5f5e100>;
+			phandle = <0x38>;
+		};
+
+		apu_cpu@7 {
+			compatible = "cortex-a78-arm-cpu";
+			device_type = "cpu";
+			arm,ccsidr0 = <0x701fe00a>;
+			arm,ccsidr1 = <0x201fe012>;
+			reg = <0x07>;
+			core-count = <0x04>;
+			arm,reset-hivecs = <0x01>;
+			arm,rvbar = <0xffff0000>;
+			arm,reset-cbar = <0xe2060000>;
+			mr = <0xaa>;
+			memory = <0xaa>;
+			qemu,halt = <0x01>;
+			gdb-id = "Cortex-A78 7";
+			#interrupt-cells = <0x01>;
+			direct-lnx-start-powered-off = <0x01>;
+			start-powered-off = <0x00>;
+			reset-gpios = <0x31 0x07>;
+			gpios = <0xab 0x4a>;
+			gpio-names = "wfi";
+			power-gpios = <0x17 0x07>;
+			mp-affinity = <0x10300>;
+			generic-timer-frequency = <0x5f5e100>;
+			phandle = <0x39>;
+		};
+
+		apu_cpu@8 {
+			compatible = "cortex-a78-arm-cpu";
+			device_type = "cpu";
+			arm,ccsidr0 = <0x701fe00a>;
+			arm,ccsidr1 = <0x201fe012>;
+			reg = <0x08>;
+			core-count = <0x04>;
+			arm,reset-hivecs = <0x01>;
+			arm,rvbar = <0xffff0000>;
+			arm,reset-cbar = <0xe2060000>;
+			mr = <0xaa>;
+			memory = <0xaa>;
+			qemu,halt = <0x01>;
+			gdb-id = "Cortex-A78 8";
+			#interrupt-cells = <0x01>;
+			direct-lnx-start-powered-off = <0x01>;
+			start-powered-off = <0x00>;
+			reset-gpios = <0x31 0x08>;
+			gpios = <0xab 0x4b>;
+			gpio-names = "wfi";
+			power-gpios = <0x17 0x08>;
+			mp-affinity = <0x20000>;
+			generic-timer-frequency = <0x5f5e100>;
+			phandle = <0x3a>;
+		};
+
+		apu_cpu@9 {
+			compatible = "cortex-a78-arm-cpu";
+			device_type = "cpu";
+			arm,ccsidr0 = <0x701fe00a>;
+			arm,ccsidr1 = <0x201fe012>;
+			reg = <0x09>;
+			core-count = <0x04>;
+			arm,reset-hivecs = <0x01>;
+			arm,rvbar = <0xffff0000>;
+			arm,reset-cbar = <0xe2060000>;
+			mr = <0xaa>;
+			memory = <0xaa>;
+			qemu,halt = <0x01>;
+			gdb-id = "Cortex-A78 9";
+			#interrupt-cells = <0x01>;
+			direct-lnx-start-powered-off = <0x01>;
+			start-powered-off = <0x00>;
+			reset-gpios = <0x31 0x09>;
+			gpios = <0xab 0x4c>;
+			gpio-names = "wfi";
+			power-gpios = <0x17 0x09>;
+			mp-affinity = <0x20100>;
+			generic-timer-frequency = <0x5f5e100>;
+			phandle = <0x3b>;
+		};
+
+		apu_cpu@10 {
+			compatible = "cortex-a78-arm-cpu";
+			device_type = "cpu";
+			arm,ccsidr0 = <0x701fe00a>;
+			arm,ccsidr1 = <0x201fe012>;
+			reg = <0x0a>;
+			core-count = <0x04>;
+			arm,reset-hivecs = <0x01>;
+			arm,rvbar = <0xffff0000>;
+			arm,reset-cbar = <0xe2060000>;
+			mr = <0xaa>;
+			memory = <0xaa>;
+			qemu,halt = <0x01>;
+			gdb-id = "Cortex-A78 10";
+			#interrupt-cells = <0x01>;
+			direct-lnx-start-powered-off = <0x01>;
+			start-powered-off = <0x00>;
+			reset-gpios = <0x31 0x0a>;
+			gpios = <0xab 0x4d>;
+			gpio-names = "wfi";
+			power-gpios = <0x17 0x0a>;
+			mp-affinity = <0x20200>;
+			generic-timer-frequency = <0x5f5e100>;
+			phandle = <0x3c>;
+		};
+
+		apu_cpu@11 {
+			compatible = "cortex-a78-arm-cpu";
+			device_type = "cpu";
+			arm,ccsidr0 = <0x701fe00a>;
+			arm,ccsidr1 = <0x201fe012>;
+			reg = <0x0b>;
+			core-count = <0x04>;
+			arm,reset-hivecs = <0x01>;
+			arm,rvbar = <0xffff0000>;
+			arm,reset-cbar = <0xe2060000>;
+			mr = <0xaa>;
+			memory = <0xaa>;
+			qemu,halt = <0x01>;
+			gdb-id = "Cortex-A78 11";
+			#interrupt-cells = <0x01>;
+			direct-lnx-start-powered-off = <0x01>;
+			start-powered-off = <0x00>;
+			reset-gpios = <0x31 0x0b>;
+			gpios = <0xab 0x4e>;
+			gpio-names = "wfi";
+			power-gpios = <0x17 0x0b>;
+			mp-affinity = <0x20300>;
+			generic-timer-frequency = <0x5f5e100>;
+			phandle = <0x3d>;
+		};
+
+		apu_cpu@12 {
+			compatible = "cortex-a78-arm-cpu";
+			device_type = "cpu";
+			arm,ccsidr0 = <0x701fe00a>;
+			arm,ccsidr1 = <0x201fe012>;
+			reg = <0x0c>;
+			core-count = <0x04>;
+			arm,reset-hivecs = <0x01>;
+			arm,rvbar = <0xffff0000>;
+			arm,reset-cbar = <0xe2060000>;
+			mr = <0xaa>;
+			memory = <0xaa>;
+			qemu,halt = <0x01>;
+			gdb-id = "Cortex-A78 12";
+			#interrupt-cells = <0x01>;
+			direct-lnx-start-powered-off = <0x01>;
+			start-powered-off = <0x00>;
+			reset-gpios = <0x31 0x0c>;
+			gpios = <0xab 0x4f>;
+			gpio-names = "wfi";
+			power-gpios = <0x17 0x0c>;
+			mp-affinity = <0x30000>;
+			generic-timer-frequency = <0x5f5e100>;
+			phandle = <0x3e>;
+		};
+
+		apu_cpu@13 {
+			compatible = "cortex-a78-arm-cpu";
+			device_type = "cpu";
+			arm,ccsidr0 = <0x701fe00a>;
+			arm,ccsidr1 = <0x201fe012>;
+			reg = <0x0d>;
+			core-count = <0x04>;
+			arm,reset-hivecs = <0x01>;
+			arm,rvbar = <0xffff0000>;
+			arm,reset-cbar = <0xe2060000>;
+			mr = <0xaa>;
+			memory = <0xaa>;
+			qemu,halt = <0x01>;
+			gdb-id = "Cortex-A78 13";
+			#interrupt-cells = <0x01>;
+			direct-lnx-start-powered-off = <0x01>;
+			start-powered-off = <0x00>;
+			reset-gpios = <0x31 0x0d>;
+			gpios = <0xab 0x50>;
+			gpio-names = "wfi";
+			power-gpios = <0x17 0x0d>;
+			mp-affinity = <0x30100>;
+			generic-timer-frequency = <0x5f5e100>;
+			phandle = <0x3f>;
+		};
+
+		apu_cpu@14 {
+			compatible = "cortex-a78-arm-cpu";
+			device_type = "cpu";
+			arm,ccsidr0 = <0x701fe00a>;
+			arm,ccsidr1 = <0x201fe012>;
+			reg = <0x0e>;
+			core-count = <0x04>;
+			arm,reset-hivecs = <0x01>;
+			arm,rvbar = <0xffff0000>;
+			arm,reset-cbar = <0xe2060000>;
+			mr = <0xaa>;
+			memory = <0xaa>;
+			qemu,halt = <0x01>;
+			gdb-id = "Cortex-A78 14";
+			#interrupt-cells = <0x01>;
+			direct-lnx-start-powered-off = <0x01>;
+			start-powered-off = <0x00>;
+			reset-gpios = <0x31 0x0e>;
+			gpios = <0xab 0x51>;
+			gpio-names = "wfi";
+			power-gpios = <0x17 0x0e>;
+			mp-affinity = <0x30200>;
+			generic-timer-frequency = <0x5f5e100>;
+			phandle = <0x40>;
+		};
+
+		apu_cpu@15 {
+			compatible = "cortex-a78-arm-cpu";
+			device_type = "cpu";
+			arm,ccsidr0 = <0x701fe00a>;
+			arm,ccsidr1 = <0x201fe012>;
+			reg = <0x0f>;
+			core-count = <0x04>;
+			arm,reset-hivecs = <0x01>;
+			arm,rvbar = <0xffff0000>;
+			arm,reset-cbar = <0xe2060000>;
+			mr = <0xaa>;
+			memory = <0xaa>;
+			qemu,halt = <0x01>;
+			gdb-id = "Cortex-A78 15";
+			#interrupt-cells = <0x01>;
+			direct-lnx-start-powered-off = <0x01>;
+			start-powered-off = <0x00>;
+			reset-gpios = <0x31 0x0f>;
+			gpios = <0xab 0x52>;
+			gpio-names = "wfi";
+			power-gpios = <0x17 0x0f>;
+			mp-affinity = <0x30300>;
+			generic-timer-frequency = <0x5f5e100>;
+			phandle = <0x41>;
+		};
+
+		rpu_a@0 {
+			#address-cells = <0x01>;
+			#size-cells = <0x00>;
+			phandle = <0x168>;
+
+			rpu_cpu_a@0 {
+				compatible = "cortex-r52-arm-cpu";
+				device_type = "cpu";
+				arm,tcmtr = <0x10001>;
+				arm,ctr = <0x8003c003>;
+				arm,clidr = <0x9200003>;
+				arm,ccsidr0 = <0xf01fe019>;
+				arm,ccsidr1 = <0xf01fe019>;
+				arm,mp-affinity = <0x00>;
+				arm,id_pfr0 = <0x131>;
+				arm,reset-hivecs = <0x01>;
+				#interrupt-cells = <0x01>;
+				memory = <0xac>;
+				qemu,halt = <0x01>;
+				memattr_ns = <0xad>;
+				core-count = <0x02>;
+				gdb-id = "Cortex-R52 #a0";
+				gpios = <0x16 0x23 0xae 0x00 0x91 0x04>;
+				gpio-names = "reset\0halt\0wfi";
+				reset-cbar = <0xe2000000>;
+				phandle = <0x29>;
+			};
+
+			rpu_cpu_a@1 {
+				compatible = "cortex-r52-arm-cpu";
+				device_type = "cpu";
+				arm,tcmtr = <0x10001>;
+				arm,ctr = <0x8003c003>;
+				arm,clidr = <0x9200003>;
+				arm,ccsidr0 = <0xf01fe019>;
+				arm,ccsidr1 = <0xf01fe019>;
+				arm,mp-affinity = <0x01>;
+				arm,id_pfr0 = <0x131>;
+				arm,reset-hivecs = <0x01>;
+				#interrupt-cells = <0x01>;
+				memory = <0xaf>;
+				qemu,halt = <0x01>;
+				memattr_ns = <0xb0>;
+				core-count = <0x02>;
+				gdb-id = "Cortex-R52 #a1";
+				gpios = <0x16 0x24 0xb1 0x00 0x91 0x05>;
+				gpio-names = "reset\0halt\0wfi";
+				reset-cbar = <0xe2000000>;
+				phandle = <0x2b>;
+			};
+		};
+
+		rpu_b@0 {
+			#address-cells = <0x01>;
+			#size-cells = <0x00>;
+			phandle = <0x169>;
+
+			rpu_cpu_b@0 {
+				compatible = "cortex-r52-arm-cpu";
+				device_type = "cpu";
+				arm,tcmtr = <0x10001>;
+				arm,ctr = <0x8003c003>;
+				arm,clidr = <0x9200003>;
+				arm,ccsidr0 = <0xf01fe019>;
+				arm,ccsidr1 = <0xf01fe019>;
+				arm,mp-affinity = <0x100>;
+				arm,id_pfr0 = <0x131>;
+				arm,reset-hivecs = <0x01>;
+				#interrupt-cells = <0x01>;
+				memory = <0xb2>;
+				qemu,halt = <0x01>;
+				memattr_ns = <0xb3>;
+				core-count = <0x02>;
+				gdb-id = "Cortex-R52 #b0";
+				gpios = <0x16 0x25 0xb4 0x00 0x91 0x06>;
+				gpio-names = "reset\0halt\0wfi";
+				reset-cbar = <0xe2000000>;
+				phandle = <0x2d>;
+			};
+
+			rpu_cpu_b@1 {
+				compatible = "cortex-r52-arm-cpu";
+				device_type = "cpu";
+				arm,tcmtr = <0x10001>;
+				arm,ctr = <0x8003c003>;
+				arm,clidr = <0x9200003>;
+				arm,ccsidr0 = <0xf01fe019>;
+				arm,ccsidr1 = <0xf01fe019>;
+				arm,mp-affinity = <0x101>;
+				arm,id_pfr0 = <0x131>;
+				arm,reset-hivecs = <0x01>;
+				#interrupt-cells = <0x01>;
+				memory = <0xb5>;
+				qemu,halt = <0x01>;
+				memattr_ns = <0xb6>;
+				core-count = <0x02>;
+				gdb-id = "Cortex-R52 #b1";
+				gpios = <0x16 0x26 0xb7 0x00 0x91 0x07>;
+				gpio-names = "reset\0halt\0wfi";
+				reset-cbar = <0xe2000000>;
+				phandle = <0x2f>;
+			};
+		};
+	};
+
+	amba_apu@0 {
+		#address-cells = <0x02>;
+		#size-cells = <0x02>;
+		#priority-cells = <0x01>;
+		compatible = "simple-bus";
+		ranges;
+		phandle = <0xaa>;
+
+		downstream_amba {
+			compatible = "qemu:memory-region";
+			alias = <0x0b>;
+			reg = <0x00 0x00 0xffffffff 0xffffffff 0xffffffff>;
+		};
+
+		timer {
+			compatible = "arm,armv8-timer";
+			interrupt-parent = <0x01>;
+			interrupts = <0x1000001 0x0d 0xffffff01 0x1000001 0x0e
+0xffffff01 0x1000001 0x0b 0xffffff01 0x1000001 0x0a 0xffffff01>;
+			clock-frequency = <0x5f5e100>;
+			phandle = <0x16a>;
+		};
+	};
+
+	amba_apu_gic@0 {
+		#address-cells = <0x02>;
+		#size-cells = <0x02>;
+		#priority-cells = <0x01>;
+		compatible = "simple-bus";
+		ranges;
+		container = <0x09>;
+		priority = <0xffffffff>;
+		phandle = <0x16b>;
+
+		interrupt-controller@0xe2000000 {
+			#address-cells = <0x00>;
+			#size-cells = <0x00>;
+			#interrupt-cells = <0x03>;
+			compatible = "arm-gicv3";
+			reg = <0x00 0xe2000000 0x00 0x10000 0x00 0x00 0xe2060000
+0x00 0x400000 0x00>;
+			interrupt-controller;
+			interrupts-extended = <0x32 0x00 0x33 0x00 0x34 0x00 0x35 0x00 0x36 0x00
+0x37 0x00 0x38 0x00 0x39 0x00 0x3a 0x00 0x3b 0x00 0x3c 0x00 0x3d 0x00 0x3e 0x00 0x3f 0x00 0x40 0x00
+0x41 0x00 0x32 0x01 0x33 0x01 0x34 0x01 0x35 0x01 0x36 0x01 0x37 0x01 0x38 0x01 0x39 0x01 0x3a
+0x01 0x3b 0x01 0x3c 0x01 0x3d 0x01 0x3e 0x01 0x3f 0x01 0x40 0x01 0x41 0x01 0x32 0x02 0x33
+0x02 0x34 0x02 0x35 0x02 0x36 0x02 0x37 0x02 0x38 0x02 0x39 0x02 0x3a 0x02 0x3b 0x02 0x3c
+0x02 0x3d 0x02 0x3e 0x02 0x3f 0x02 0x40 0x02 0x41 0x02 0x32 0x03 0x33 0x03 0x34 0x03 0x35
+0x03 0x36 0x03 0x37 0x03 0x38 0x03 0x39 0x03 0x3a 0x03 0x3b 0x03 0x3c 0x03 0x3d 0x03 0x3e
+0x03 0x3f 0x03 0x40 0x03 0x41 0x03 0x01 0x01 0x09 0x104 0x01 0x01 0x09 0x204 0x01 0x01
+0x09 0x404 0x01 0x01 0x09 0x804 0x01 0x01 0x09 0x1004 0x01 0x01 0x09 0x2004 0x01 0x01 0x09
+0x4004 0x01 0x01 0x09 0x8004 0x01 0x01 0x09 0x10004 0x01 0x01 0x09 0x20004 0x01 0x01 0x09
+0x40004 0x01 0x01 0x09 0x80004 0x01 0x01 0x09 0x100004 0x01 0x01 0x09 0x200004 0x01 0x01
+0x09 0x400004>;
+			num-cpu = <0x10>;
+			num-irq = <0x220>;
+			has-security-extensions = <0x01>;
+			redist-region-count = <0x10>;
+			has-lpi = <0x01>;
+			sysmem = <0x0b>;
+			phandle = <0x01>;
+		};
+
+		git_its@0xe2040000 {
+			compatible = "arm-gicv3-its";
+			reg = <0x00 0xe2040000 0x00 0x20000 0x00>;
+			parent-gicv3 = <0x01>;
+		};
+	};
+
+	lpd_reset_domain@0 {
+		compatible = "qemu,reset-domain";
+		mr0 = <0x08>;
+		reset-gpios = <0x5e 0x07 0x5e 0x0a>;
+	};
+
+	fpd_reset_domain@0 {
+		compatible = "qemu,reset-domain";
+		mr0 = <0x09>;
+		reset-gpios = <0x5e 0x07 0x5e 0x0a 0x16 0x1c 0x16 0x1d>;
+	};
+
+	amba_alias@0 {
+		compatible = "qemu:memory-region";
+		container = <0xb8>;
+		alias = <0x0b>;
+		reg = <0x00 0x00 0xffffffff 0xffffffff 0x01>;
+		phandle = <0x16c>;
+	};
+
+	qemu_sysmem@0 {
+		#address-cells = <0x02>;
+		#size-cells = <0x02>;
+		#priority-cells = <0x01>;
+		compatible = "qemu:system-memory";
+		phandle = <0xb8>;
+	};
+
+	dummy_ppu0@0 {
+		#interrupt-cells = <0x01>;
+		phandle = <0x93>;
+	};
+
+	dummy_ppu1@0 {
+		#interrupt-cells = <0x01>;
+		phandle = <0x98>;
+	};
+
+	dummy_ddrmc0@0 {
+		#interrupt-cells = <0x01>;
+		phandle = <0xa0>;
+	};
+
+	dummy_ddrmc1@0 {
+		#interrupt-cells = <0x01>;
+		phandle = <0x16d>;
+	};
+
+	ddr@0x00000000 {
+		compatible = "qemu:memory-region";
+		container = <0xb9>;
+		qemu,ram = <0x01>;
+		reg = <0x00 0x00 0x00 0x80000000 0x00>;
+		phandle = <0x7f>;
+	};
+
+	ddr_2@0x800000000ULL {
+		compatible = "qemu:memory-region-spec";
+		container = <0xba>;
+		qemu,ram = <0x01>;
+		reg = <0x08 0x00 0x08 0x00 0x00>;
+		phandle = <0x16e>;
+	};
+
+	mdio {
+		#address-cells = <0x01>;
+		#size-cells = <0x00>;
+		#priority-cells = <0x00>;
+		compatible = "mdio";
+		phandle = <0x18>;
+
+		phy@1 {
+			compatible = "dp83867";
+			device_type = "ethernet-phy";
+			reg = <0x01>;
+			phandle = <0x16f>;
+		};
+	};
+
+	cpu_dummy {
+		phandle = <0x170>;
+	};
+
+	tbu7_slave@0 {
+		#address-cells = <0x02>;
+		#size-cells = <0x02>;
+		#priority-cells = <0x01>;
+		compatible = "simple-bus";
+		ranges;
+		phandle = <0x48>;
+	};
+
+	tbu8_slave@0 {
+		#address-cells = <0x02>;
+		#size-cells = <0x02>;
+		#priority-cells = <0x01>;
+		compatible = "simple-bus";
+		ranges;
+		phandle = <0x49>;
+	};
+
+	tbu9_slave@0 {
+		#address-cells = <0x02>;
+		#size-cells = <0x02>;
+		#priority-cells = <0x01>;
+		compatible = "simple-bus";
+		ranges;
+		phandle = <0x4a>;
+	};
+
+	tbu10_slave@0 {
+		#address-cells = <0x02>;
+		#size-cells = <0x02>;
+		#priority-cells = <0x01>;
+		compatible = "simple-bus";
+		ranges;
+		phandle = <0x4b>;
+	};
+
+	tbu11_slave@0 {
+		#address-cells = <0x02>;
+		#size-cells = <0x02>;
+		#priority-cells = <0x01>;
+		compatible = "simple-bus";
+		ranges;
+		phandle = <0x4c>;
+	};
+
+	tbu12_slave@0 {
+		#address-cells = <0x02>;
+		#size-cells = <0x02>;
+		#priority-cells = <0x01>;
+		compatible = "simple-bus";
+		ranges;
+		phandle = <0x4d>;
+	};
+
+	mr_rpu_gic_a@0 {
+		#address-cells = <0x02>;
+		#size-cells = <0x02>;
+		#priority-cells = <0x01>;
+		compatible = "simple-bus";
+		phandle = <0xa8>;
+
+		rpu_gic_a@0x0 {
+			#address-cells = <0x00>;
+			#size-cells = <0x00>;
+			#interrupt-cells = <0x03>;
+			compatible = "arm-gicv3";
+			reg = <0x00 0x00 0x00 0x10000 0x00 0x00 0x100000 0x00 0x40000 0x00>;
+			interrupt-controller;
+			interrupts-extended = <0x29 0x00 0x2b 0x00 0x29 0x01 0x2b 0x01 0x29 0x02
+0x2b 0x02 0x29 0x03 0x2b 0x03 0x02 0x01 0x09 0x104 0x02 0x01 0x09 0x204>;
+			first-cpu-idx = <0x10>;
+			num-cpu = <0x02>;
+			num-irq = <0x120>;
+			redist-region-count = <0x02>;
+			gpio-controller;
+			#gpio-cells = <0x01>;
+			phandle = <0x02>;
+		};
+	};
+
+	mr_rpu_gic_b@0 {
+		#address-cells = <0x02>;
+		#size-cells = <0x02>;
+		#priority-cells = <0x01>;
+		compatible = "simple-bus";
+		phandle = <0xbd>;
+
+		rpu_gic_b@0x0 {
+			#address-cells = <0x00>;
+			#size-cells = <0x00>;
+			#interrupt-cells = <0x03>;
+			compatible = "arm-gicv3";
+			reg = <0x00 0x00 0x00 0x10000 0x00 0x00 0x100000 0x00 0x40000 0x00>;
+			interrupt-controller;
+			interrupts-extended = <0x2d 0x00 0x2f 0x00 0x2d 0x01 0x2f 0x01 0x2d 0x02
+0x2f 0x02 0x2d 0x03 0x2f 0x03 0x03 0x01 0x09 0x104 0x03 0x01 0x09 0x204>;
+			first-cpu-idx = <0x12>;
+			num-cpu = <0x02>;
+			num-irq = <0x120>;
+			redist-region-count = <0x02>;
+			gpio-controller;
+			#gpio-cells = <0x01>;
+			phandle = <0x03>;
+		};
+	};
+
+	tcm_core@0 {
+		#address-cells = <0x02>;
+		#size-cells = <0x02>;
+		#priority-cells = <0x01>;
+		compatible = "qemu:memory-region";
+		phandle = <0xa7>;
+
+		atcm_rpu_core0@0x00000 {
+			compatible = "qemu:memory-region";
+			container = <0xa7>;
+			qemu,ram = <0x01>;
+			reg = <0x00 0x00 0x00 0x10000 0x00>;
+			phandle = <0x171>;
+		};
+
+		btcm_rpu_core0@0x00000 {
+			compatible = "qemu:memory-region";
+			container = <0xa7>;
+			qemu,ram = <0x01>;
+			reg = <0x00 0x10000 0x00 0x10000 0x00>;
+			phandle = <0x172>;
+		};
+
+		ctcm_rpu_core0@0x00000 {
+			compatible = "qemu:memory-region";
+			container = <0xa7>;
+			qemu,ram = <0x01>;
+			reg = <0x00 0x20000 0x00 0x10000 0x00>;
+			phandle = <0x173>;
+		};
+	};
+
+	tcm_core@1 {
+		#address-cells = <0x02>;
+		#size-cells = <0x02>;
+		#priority-cells = <0x01>;
+		compatible = "qemu:memory-region";
+		phandle = <0xa9>;
+
+		atcm_rpu_core1@0x00000 {
+			compatible = "qemu:memory-region";
+			container = <0xa9>;
+			qemu,ram = <0x01>;
+			reg = <0x00 0x00 0x00 0x10000 0x00>;
+			phandle = <0x174>;
+		};
+
+		btcm_rpu_core1@0x00000 {
+			compatible = "qemu:memory-region";
+			container = <0xa9>;
+			qemu,ram = <0x01>;
+			reg = <0x00 0x10000 0x00 0x10000 0x00>;
+			phandle = <0x175>;
+		};
+
+		ctcm_rpu_core1@0x00000 {
+			compatible = "qemu:memory-region";
+			container = <0xa9>;
+			qemu,ram = <0x01>;
+			reg = <0x00 0x20000 0x00 0x10000 0x00>;
+			phandle = <0x176>;
+		};
+	};
+
+	tcm_core@2 {
+		#address-cells = <0x02>;
+		#size-cells = <0x02>;
+		#priority-cells = <0x01>;
+		compatible = "qemu:memory-region";
+		phandle = <0xbb>;
+
+		atcm_rpu_core2@0x00000 {
+			compatible = "qemu:memory-region";
+			container = <0xbb>;
+			qemu,ram = <0x01>;
+			reg = <0x00 0x00 0x00 0x10000 0x00>;
+			phandle = <0x177>;
+		};
+
+		btcm_rpu_core2@0x00000 {
+			compatible = "qemu:memory-region";
+			container = <0xbb>;
+			qemu,ram = <0x01>;
+			reg = <0x00 0x10000 0x00 0x10000 0x00>;
+			phandle = <0x178>;
+		};
+
+		ctcm_rpu_core2@0x00000 {
+			compatible = "qemu:memory-region";
+			container = <0xbb>;
+			qemu,ram = <0x01>;
+			reg = <0x00 0x20000 0x00 0x10000 0x00>;
+			phandle = <0x179>;
+		};
+	};
+
+	tcm_core@3 {
+		#address-cells = <0x02>;
+		#size-cells = <0x02>;
+		#priority-cells = <0x01>;
+		compatible = "qemu:memory-region";
+		phandle = <0xbc>;
+
+		atcm_rpu_core3@0x00000 {
+			compatible = "qemu:memory-region";
+			container = <0xbc>;
+			qemu,ram = <0x01>;
+			reg = <0x00 0x00 0x00 0x10000 0x00>;
+			phandle = <0x17a>;
+		};
+
+		btcm_rpu_core3@0x00000 {
+			compatible = "qemu:memory-region";
+			container = <0xbc>;
+			qemu,ram = <0x01>;
+			reg = <0x00 0x10000 0x00 0x10000 0x00>;
+			phandle = <0x17b>;
+		};
+
+		ctcm_rpu_core3@0x00000 {
+			compatible = "qemu:memory-region";
+			container = <0xbc>;
+			qemu,ram = <0x01>;
+			reg = <0x00 0x20000 0x00 0x10000 0x00>;
+			phandle = <0x17c>;
+		};
+	};
+
+	tcm_cluster_a@0 {
+		#address-cells = <0x02>;
+		#size-cells = <0x02>;
+		#priority-cells = <0x01>;
+		compatible = "qemu:memory-region";
+		phandle = <0x0f>;
+
+		tcm_core_0 {
+			compatible = "qemu:memory-region";
+			alias = <0xa7>;
+			reg = <0x00 0x00 0x00 0x40000 0x00>;
+		};
+
+		tcm_core_1 {
+			compatible = "qemu:memory-region";
+			alias = <0xa9>;
+			reg = <0x00 0x40000 0x00 0x40000 0x00>;
+		};
+	};
+
+	tcm_cluster_b@0 {
+		#address-cells = <0x02>;
+		#size-cells = <0x02>;
+		#priority-cells = <0x01>;
+		compatible = "qemu:memory-region";
+		phandle = <0x10>;
+
+		tcm_core_0 {
+			compatible = "qemu:memory-region";
+			alias = <0xbb>;
+			reg = <0x00 0x00 0x00 0x40000 0x00>;
+		};
+
+		tcm_core_1 {
+			compatible = "qemu:memory-region";
+			alias = <0xbc>;
+			reg = <0x00 0x40000 0x00 0x40000 0x00>;
+		};
+	};
+
+	amba_r5@2 {
+		#address-cells = <0x02>;
+		#size-cells = <0x02>;
+		#priority-cells = <0x01>;
+		compatible = "simple-bus";
+		ranges;
+		phandle = <0xb2>;
+
+		downstream_tcm {
+			compatible = "qemu:memory-region";
+			alias = <0xbb>;
+			reg = <0x00 0x00 0x00 0x400000 0x01>;
+		};
+
+		downstream_gic1 {
+			compatible = "qemu:memory-region";
+			alias = <0xbd>;
+			reg = <0x00 0xe2000000 0x00 0x140000 0x01>;
+		};
+
+		downstream_amba {
+			compatible = "qemu:memory-region";
+			alias = <0xa6>;
+			reg = <0x00 0x00 0xffffffff 0xffffffff 0x00>;
+		};
+	};
+
+	amba_r5@3 {
+		#address-cells = <0x02>;
+		#size-cells = <0x02>;
+		#priority-cells = <0x01>;
+		compatible = "simple-bus";
+		ranges;
+		phandle = <0xb5>;
+
+		downstream_tcm {
+			compatible = "qemu:memory-region";
+			alias = <0xbc>;
+			reg = <0x00 0x00 0x00 0x400000 0x01>;
+		};
+
+		downstream_gic1 {
+			compatible = "qemu:memory-region";
+			alias = <0xbd>;
+			reg = <0x00 0xe2000000 0x00 0x140000 0x01>;
+		};
+
+		downstream_amba {
+			compatible = "qemu:memory-region";
+			alias = <0xa6>;
+			reg = <0x00 0x00 0xffffffff 0xffffffff 0x00>;
+		};
+	};
+
+	rpu2_s_ma {
+		doc-ignore = <0x01>;
+		compatible = "qemu:memory-transaction-attr";
+		secure = <0x01>;
+		requester-id = <0x208>;
+		phandle = <0xb3>;
+	};
+
+	rpu3_s_ma {
+		doc-ignore = <0x01>;
+		compatible = "qemu:memory-transaction-attr";
+		secure = <0x01>;
+		requester-id = <0x20c>;
+		phandle = <0xb6>;
+	};
+
+	usb1_ma {
+		doc-ignore = <0x01>;
+		compatible = "qemu:memory-transaction-attr";
+		secure = <0x00>;
+		requester-id = <0x232>;
+		phandle = <0x30>;
+	};
+
+	__symbols__ {
+		pmc_ppu0_memattr = "/pmc_ppu0_ma";
+		pmc_ppu1_memattr = "/pmc_ppu1_ma";
+		psm_memattr = "/psm_ma";
+		ddrmc_ub0_memattr = "/ddrmc_ub0_ma";
+		ddrmc_ub1_memattr = "/ddrmc_ub1_ma";
+		pmc_dma0_memattr = "/pmc_dma0_ma";
+		pmc_dma1_memattr = "/pmc_dma1_ma";
+		pmc_qspi_dma_memattr_smid = "/pmc_qspi_dma_ma_smid";
+		pmc_qspi_dma_w_memattr_smid = "/pmc_qspi_dma_w_ma_smid";
+		apu0_s_memattr = "/apu0_s_ma";
+		apu0_ns_memattr = "/apu0_ns_ma";
+		apu1_s_memattr = "/apu1_s_ma";
+		apu1_ns_memattr = "/apu1_ns_ma";
+		rpu0_s_memattr = "/rpu0_s_ma";
+		rpu1_s_memattr = "/rpu1_s_ma";
+		gem0_memattr_smid = "/gem0_ma_smid";
+		gem0_w_memattr_smid = "/gem0_w_ma_smid";
+		gem1_memattr_smid = "/gem1_ma_smid";
+		gem1_w_memattr_smid = "/gem1_w_ma_smid";
+		ospi_dma_memattr_smid = "/ospi_dma_ma_smid";
+		ospi_dma_w_memattr_smid = "/ospi_dma_w_ma_smid";
+		sd0_memattr_smid = "/sd0_ma_smid";
+		sd0_w_memattr_smid = "/sd0_w_ma_smid";
+		sd1_memattr_smid = "/sd1_ma_smid";
+		sd1_w_memattr_smid = "/sd1_w_ma_smid";
+		usb0_memattr = "/usb0_ma";
+		amba_root = "/amba_root@0";
+		amba = "/amba_root@0/amba@0";
+		xmpu_ocm = "/amba_root@0/amba@0/xmpu_ocm@0";
+		xmpu_ocm2 = "/amba_root@0/amba@0/xmpu_ocm2@0";
+		loader_write_0xF1110880 = "/amba_root@0/amba@0/loader_write_cpu0_0x1@0xF1110880";
+		loader_write_0xFD1A0050 = "/amba_root@0/amba@0/loader_write_cpu0_0x5@0xFD1A0050";
+		loader_write_0xF111010C = "/amba_root@0/amba@0/loader_write_cpu0_0xFF@0xF111010C";
+		s_axi_tcm_a = "/amba_root@0/amba@0/s_axi_tcm_a@0";
+		s_axi_tcm_b = "/amba_root@0/amba@0/s_axi_tcm_b@0";
+		loader_write_0xF12B0100 = "/amba_root@0/amba@0/loader_write_cpu0_0x80C@0xF12B0100";
+		amba_lpd = "/amba_root@0/amba_lpd@0";
+		xppu_lpd = "/amba_root@0/amba_lpd@0/xppu_lpd@0xeb990000";
+		gem0 = "/amba_root@0/amba_lpd@0/ethernet@0xf19e0000";
+		gem1 = "/amba_root@0/amba_lpd@0/ethernet@0xf19f0000";
+		serial0 = "/amba_root@0/amba_lpd@0/serial@0xf1920000";
+		serial1 = "/amba_root@0/amba_lpd@0/serial@0xf1930000";
+		canfdbus0 = "/amba_root@0/amba_lpd@0/canfdbus@0";
+		can0 = "/amba_root@0/amba_lpd@0/can@0xf1980000";
+		can1 = "/amba_root@0/amba_lpd@0/can@0xf1990000";
+		crl = "/amba_root@0/amba_lpd@0/crl@0xeb5e0000";
+		lpd_iou_slcr = "/amba_root@0/amba_lpd@0/slcr@0xf19a0000";
+		ipi = "/amba_root@0/amba_lpd@0/ipi@0xeb300000";
+		spi0 = "/amba_root@0/amba_lpd@0/spi@0xf1960000";
+		spi0_flash0 = "/amba_root@0/amba_lpd@0/spi@0xf1960000/spi0_flash0@0";
+		spi1 = "/amba_root@0/amba_lpd@0/spi@0xf1970000";
+		spi1_flash0 = "/amba_root@0/amba_lpd@0/spi@0xf1970000/spi1_flash0@0";
+		dwc3_0 = "/amba_root@0/amba_lpd@0/usb2@USB2_0_XHCI";
+		ttc0 = "/amba_root@0/amba_lpd@0/timer@0xf1dc0000";
+		ttc1 = "/amba_root@0/amba_lpd@0/timer@0xf1dd0000";
+		ttc2 = "/amba_root@0/amba_lpd@0/timer@0xf1de0000";
+		ttc3 = "/amba_root@0/amba_lpd@0/timer@0xf1df0000";
+		adma0_mattr = "/amba_root@0/amba_lpd@0/adma0mattr";
+		adma0 = "/amba_root@0/amba_lpd@0/dma-controller@0xebd00000";
+		adma1_mattr = "/amba_root@0/amba_lpd@0/adma1mattr";
+		adma1 = "/amba_root@0/amba_lpd@0/dma-controller@0xebd10000";
+		adma2_mattr = "/amba_root@0/amba_lpd@0/adma2mattr";
+		adma2 = "/amba_root@0/amba_lpd@0/dma-controller@0xebd20000";
+		adma3_mattr = "/amba_root@0/amba_lpd@0/adma3mattr";
+		adma3 = "/amba_root@0/amba_lpd@0/dma-controller@0xebd30000";
+		adma4_mattr = "/amba_root@0/amba_lpd@0/adma4mattr";
+		adma4 = "/amba_root@0/amba_lpd@0/dma-controller@0xebd40000";
+		adma5_mattr = "/amba_root@0/amba_lpd@0/adma5mattr";
+		adma5 = "/amba_root@0/amba_lpd@0/dma-controller@0xebd50000";
+		adma6_mattr = "/amba_root@0/amba_lpd@0/adma6mattr";
+		adma6 = "/amba_root@0/amba_lpd@0/dma-controller@0xebd60000";
+		adma7_mattr = "/amba_root@0/amba_lpd@0/adma7mattr";
+		adma7 = "/amba_root@0/amba_lpd@0/dma-controller@0xebd70000";
+		ps_i2c0 = "/amba_root@0/amba_lpd@0/lpd_i2c_wrapper/ps_i2c0@0xf1940000";
+		i2c0_bridge = "/amba_root@0/amba_lpd@0/lpd_i2c_wrapper/ps_i2c0@0xf1940000/
+i2c0_bridge@0";
+		ps_i2c1 = "/amba_root@0/amba_lpd@0/lpd_i2c_wrapper/ps_i2c0@0xf1950000";
+		eeprom0 = "/amba_root@0/amba_lpd@0/lpd_i2c_wrapper/ps_i2c0@0xf1950000/eeprom@54";
+		eeprom1 = "/amba_root@0/amba_lpd@0/lpd_i2c_wrapper/ps_i2c0@0xf1950000/eeprom@51";
+		i2c1_bridge = "/amba_root@0/amba_lpd@0/lpd_i2c_wrapper/ps_i2c0@0xf1950000/
+i2c1_bridge@0";
+		ocm_ctrl0 = "/amba_root@0/amba_lpd@0/ocm_ctrl@OCM";
+		lpd_slcr_secure = "/amba_root@0/amba_lpd@0/lpd_slcr_secure@0xeb510000";
+		lpd_iou_slcr_secure = "/amba_root@0/amba_lpd@0/lpd_iou_slcr_secure@0xf19c0000";
+		lpd_gpio = "/amba_root@0/amba_lpd@0/lpd_gpio@0xf19d0000";
+		intlpd = "/amba_root@0/amba_lpd@0/intlpd@0xea600000";
+		rpu_ctrl = "/amba_root@0/amba_lpd@0/rpu_ctrl@0";
+		rpu_ctrl_a = "/amba_root@0/amba_lpd@0/rpu_cluster@0xeb580000";
+		rpu_ctrl_a0 = "/amba_root@0/amba_lpd@0/rpu_ctrl_a0@0xeb588000";
+		rpu_ctrl_a1 = "/amba_root@0/amba_lpd@0/rpu_ctrl_a1@0xeb58c000";
+		rpu_ctrl_b = "/amba_root@0/amba_lpd@0/rpu_cluster@0xeb590000";
+		rpu_ctrl_b0 = "/amba_root@0/amba_lpd@0/rpu_ctrl_b0@0xeb598000";
+		rpu_ctrl_b1 = "/amba_root@0/amba_lpd@0/rpu_ctrl_b1@0xeb59c000";
+		rpu_pcil = "/amba_root@0/amba_lpd@0/rpu_pcil@0xEB420000";
+		dwc3_1 = "/amba_root@0/amba_lpd@0/usb2@USB2_0_XHCI1";
+		amba_fpd = "/amba_root@0/amba_fpd@0";
+		wwdt0 = "/amba_root@0/amba_fpd@0/watchdog@0xecc10000";
+		intfpd = "/amba_root@0/amba_fpd@0/intfpd@0xec400000";
+		apu_cluster0 = "/amba_root@0/amba_fpd@0/apu_cluster@MM_FPD_FPD_APU_CLUSTER0";
+		apu_cluster1 = "/amba_root@0/amba_fpd@0/apu_cluster@MM_FPD_FPD_APU_CLUSTER1";
+		apu_cluster2 = "/amba_root@0/amba_fpd@0/apu_cluster@MM_FPD_FPD_APU_CLUSTER2";
+		apu_cluster3 = "/amba_root@0/amba_fpd@0/apu_cluster@MM_FPD_FPD_APU_CLUSTER3";
+		smmu = "/amba_root@0/amba_fpd@0/smmuv3@MM_FPD_SMMU";
+		pcie = "/amba_root@0/amba_fpd@0/dummy_pcie@0x6_0000_0000";
+		pki_rng = "/amba_root@0/amba_fpd@0/pki_rng@0x20400040000ULL";
+		apu_pcil = "/amba_root@0/amba_fpd@0/apu_pcil@0xecb10000";
+		cpm5_crx = "/amba_root@0/amba_fpd@0/cpm5_crx@0xdc0000";
+		amba_pmc_internal = "/amba_root@0/amba_pmc_internal@0";
+		xmpu_pmc = "/amba_root@0/amba_pmc_internal@0/xmpu_pmc@0";
+		xppu_pmc_npi = "/amba_root@0/amba_pmc_internal@0/xppu_pmc_npi@0xf1300000";
+		xppu_pmc = "/amba_root@0/amba_pmc_internal@0/xppu_pmc@0xf1310000";
+		amba_pmc = "/amba_root@0/amba_pmc@0";
+		xmpu_pmc_cfu = "/amba_root@0/amba_pmc@0/xmpu_pmc_cfu@0xf1340000";
+		pmx_err_mng = "/amba_root@0/amba_pmc@0/pmx_err_mng@0xf1110000";
+		amba_pmc_iou = "/amba_root@0/amba_pmc_iou@0";
+		pmc_iou_slcr = "/amba_root@0/amba_pmc_iou@0/pmc_iou_slcr@0xf1060000";
+		pmc_iou_slcr_secure = "/amba_root@0/amba_pmc_iou@0/pmc_iou_slcr_secure@0xf1070000";
+		pmc_qspi_dma_0 = "/amba_root@0/amba_pmc_iou@0/pmc_qspi_dma@QSPI_DMA";
+		pmc_qspi_0 = "/amba_root@0/amba_pmc_iou@0/pmc_qspi@0xf1030000";
+		qspi_flash_lcs_lb = "/amba_root@0/amba_pmc_iou@0/pmc_qspi@0xf1030000/
+qspi_flash_lcs_lb@0";
+		qspi_flash_ucs_ub = "/amba_root@0/amba_pmc_iou@0/pmc_qspi@0xf1030000/
+qspi_flash_ucs_ub@0";
+		ospi_dma_dst = "/amba_root@0/amba_pmc_iou@0/ospi_dst_dma@0";
+		ospi_dma_src = "/amba_root@0/amba_pmc_iou@0/ospi_src_dma@0";
+		ospi = "/amba_root@0/amba_pmc_iou@0/spi@0xf1010000";
+		gpio_mr_mux = "/amba_root@0/amba_pmc_iou@0/gpio_mr_mux@0xc0000000";
+		pmc_gpio = "/amba_root@0/amba_pmc_iou@0/pmc_gpio@0xf1020000";
+		sdhci0 = "/amba_root@0/amba_pmc_iou@0/mmc@0xf1040000";
+		sdhci1 = "/amba_root@0/amba_pmc_iou@0/mmc@0xf1050000";
+		pmc_tap = "/amba_root@0/amba_pmc_iou@0/pmc_tap@0xf11a0000";
+		pmx_wwdt = "/amba_root@0/amba_pmc_iou@0/wwdt@0xf03f0000";
+		amba_pmc_sec = "/amba_root@0/amba_pmc_sec@0";
+		pmc_dma0_src = "/amba_root@0/amba_pmc_sec@0/pmc_dma0_src@0";
+		pmc_dma0_dst = "/amba_root@0/amba_pmc_sec@0/pmc_dma0_dst@0";
+		pmc_dma1_src = "/amba_root@0/amba_pmc_sec@0/pmc_dma1_src@0";
+		pmc_dma1_dst = "/amba_root@0/amba_pmc_sec@0/pmc_dma1_dst@0";
+		pmc_stream_switch = "/amba_root@0/amba_pmc_sec@0/pmc_stream_switch@0";
+		pmc_sha3 = "/amba_root@0/amba_pmc_sec@0/pmc_sha@0xf1210000";
+		pmc_aes = "/amba_root@0/amba_pmc_sec@0/pmc_aes@0xf11e0000";
+		xlnx_aes = "/amba_root@0/amba_pmc_sec@0/pmc_aes@0xf11e0000/xlnx_aes@0";
+		pmc_rsa = "/amba_root@0/amba_pmc_sec@0/pmc_rsa@0xf1200000";
+		xlnx_pmc_efuse_cache = "/amba_root@0/amba_pmc_sec@0/
+xlnx_pmc_efuse_cache@0xf1250000";
+		pmc_puf_ctrl = "/amba_root@0/amba_pmc_sec@0/pmc_puf_ctrl@0";
+		pmc_efuse = "/amba_root@0/amba_pmc_sec@0/pmc_efuse@0xf1240000";
+		xlnx_efuse = "/amba_root@0/amba_pmc_sec@0/pmc_efuse@0xf1240000/xlnx_efuse@0";
+		pmc_bbram_ctrl = "/amba_root@0/amba_pmc_sec@0/pmc_bbram@0xf11f0000";
+		pmc_sbi = "/amba_root@0/amba_pmc_sec@0/pmc_sbi@0xf1220000";
+		pmc_sha3_1 = "/amba_root@0/amba_pmc_sec@0/pmc_sha1@0xF1800000";
+		amba_pmc_ppu = "/amba_root@0/amba_pmc_ppu@0";
+		pmc_gic_proxy = "/amba_root@0/amba_pmc_ppu@0/pmc_gic_proxy@0";
+		amba_pmc_sys = "/amba_root@0/amba_pmc_sys@0";
+		pmc_clk_rst = "/amba_root@0/amba_pmc_sys@0/pmc_clk_rst@0xf1260000";
+		pmc_int = "/amba_root@0/amba_pmc_sys@0/pmc_int@0xf1400000";
+		pmc_global = "/amba_root@0/amba_pmc_sys@0/pmc_global@0xf1110000";
+		pmc_err_mng = "/amba_root@0/amba_pmc_sys@0/pmc_err_mng@0xF1130000";
+		pmc_stream_zero = "/amba_root@0/amba_pmc_sys@0/pmc_stream_zero@";
+		pmc_sysmon = "/amba_root@0/amba_pmc_sys@0/pmc_sysmon@0xf1270000";
+		pmc_ams_sat0 = "/amba_root@0/amba_pmc_sys@0/pmc_ams_sat@0";
+		pmc_ams_sat1 = "/amba_root@0/amba_pmc_sys@0/pmc_ams_sat@1";
+		pmc_global_tamper = "/amba_root@0/amba_pmc_sys@0/versal_pmc_tamper@";
+		lpd_sysmon_sat = "/amba_root@0/amba_pmc_sys@0/lpd_ams_sat@0";
+		fpd_sysmon_sat0 = "/amba_root@0/amba_pmc_sys@0/fpd_ams_sat@0";
+		fpd_sysmon_sat1 = "/amba_root@0/amba_pmc_sys@0/fpd_ams_sat@1";
+		fpd_sysmon_sat2 = "/amba_root@0/amba_pmc_sys@0/fpd_ams_sat@2";
+		fpd_sysmon_sat3 = "/amba_root@0/amba_pmc_sys@0/fpd_ams_sat@3";
+		amba_pmc_pl = "/amba_root@0/amba_pmc_pl@0";
+		noc_npi_nir = "/amba_root@0/amba_pmc_pl@0/noc_npi_nir@0xf6000000";
+		npi_ddrmc_ub0 = "/amba_root@0/amba_pmc_pl@0/npi_ddrmc_ub0@0xf67c0000";
+		npi_ddrmc_main0 = "/amba_root@0/amba_pmc_pl@0/npi_ddrmc_main0@0xf6790000";
+		npi_ddrmc_noc0 = "/amba_root@0/amba_pmc_pl@0/npi_ddrmc_noc0@0xf67a0000";
+		npi_ddrmc_ub1 = "/amba_root@0/amba_pmc_pl@0/npi_ddrmc_ub1@0xf68b0000";
+		npi_ddrmc_main1 = "/amba_root@0/amba_pmc_pl@0/npi_ddrmc_main1@0xf6880000";
+		npi_ddrmc_noc1 = "/amba_root@0/amba_pmc_pl@0/npi_ddrmc_noc1@0xf6890000";
+		npi_ddrmc_ub2 = "/amba_root@0/amba_pmc_pl@0/npi_ddrmc_ub2@0xf6dc0000";
+		npi_ddrmc_main2 = "/amba_root@0/amba_pmc_pl@0/npi_ddrmc_main2@0xf6d90000";
+		npi_ddrmc_noc2 = "/amba_root@0/amba_pmc_pl@0/npi_ddrmc_noc2@0xf6da0000";
+		npi_ddrmc_ub3 = "/amba_root@0/amba_pmc_pl@0/npi_ddrmc_ub3@0xf6eb0000";
+		npi_ddrmc_main3 = "/amba_root@0/amba_pmc_pl@0/npi_ddrmc_main3@0xf6e80000";
+		npi_ddrmc_noc3 = "/amba_root@0/amba_pmc_pl@0/npi_ddrmc_noc3@0xf6e90000";
+		npi_ddrmc_ub4 = "/amba_root@0/amba_pmc_pl@0/npi_ddrmc_ub4@0xf6f70000";
+		npi_ddrmc_main4 = "/amba_root@0/amba_pmc_pl@0/npi_ddrmc_main4@0xf6f40000";
+		npi_ddrmc_noc4 = "/amba_root@0/amba_pmc_pl@0/npi_ddrmc_noc4@0xf6f50000";
+		npi_ddrmc_ub5 = "/amba_root@0/amba_pmc_pl@0/npi_ddrmc_ub5@0xf7060000";
+		npi_ddrmc_main5 = "/amba_root@0/amba_pmc_pl@0/npi_ddrmc_main5@0xf7030000";
+		npi_ddrmc_noc5 = "/amba_root@0/amba_pmc_pl@0/npi_ddrmc_noc5@0xf7040000";
+		npi_ddrmc_ub6 = "/amba_root@0/amba_pmc_pl@0/npi_ddrmc_ub6@0xf7320000";
+		npi_ddrmc_main6 = "/amba_root@0/amba_pmc_pl@0/npi_ddrmc_main6@0xf72f0000";
+		npi_ddrmc_noc6 = "/amba_root@0/amba_pmc_pl@0/npi_ddrmc_noc6@0xf7300000";
+		npi_ddrmc_ub7 = "/amba_root@0/amba_pmc_pl@0/npi_ddrmc_ub7@0xf7400000";
+		npi_ddrmc_main7 = "/amba_root@0/amba_pmc_pl@0/npi_ddrmc_main7@0xf73d0000";
+		npi_ddrmc_noc7 = "/amba_root@0/amba_pmc_pl@0/npi_ddrmc_noc7@0xf73e0000";
+		npi_ddrmc_xmpu0 = "/amba_root@0/amba_pmc_pl@0/npi_ddrmc_xmpu0@0xf67a0000";
+		noc_npi_devs = "/amba_root@0/amba_pmc_pl@0/noc_npi_devs@0";
+		cfu_fdro = "/amba_root@0/amba_pmc_pl@0/cfu_fdro@0xf12c2000";
+		cfu_sfr = "/amba_root@0/amba_pmc_pl@0/cfu_sfr@0xf12c1000";
+		cframe0_reg = "/amba_root@0/amba_pmc_pl@0/cframe0_reg@0xf12d0000";
+		cframe1_reg = "/amba_root@0/amba_pmc_pl@0/cframe1_reg@0xf12d2000";
+		cframe2_reg = "/amba_root@0/amba_pmc_pl@0/cframe2_reg@0xf12d4000";
+		cframe3_reg = "/amba_root@0/amba_pmc_pl@0/cframe3_reg@0xf12d6000";
+		cframe4_reg = "/amba_root@0/amba_pmc_pl@0/cframe4_reg@0xf12d8000";
+		cframe5_reg = "/amba_root@0/amba_pmc_pl@0/cframe5_reg@0xf12da000";
+		cframe6_reg = "/amba_root@0/amba_pmc_pl@0/cframe6_reg@0xf12dc000";
+		cframe7_reg = "/amba_root@0/amba_pmc_pl@0/cframe7_reg@0xf12de000";
+		cframe8_reg = "/amba_root@0/amba_pmc_pl@0/cframe8_reg@0xf12e0000";
+		cframe9_reg = "/amba_root@0/amba_pmc_pl@0/cframe9_reg@0xf12e2000";
+		cframe10_reg = "/amba_root@0/amba_pmc_pl@0/cframe10_reg@0xf12e4000";
+		cframe11_reg = "/amba_root@0/amba_pmc_pl@0/cframe11_reg@0xf12e6000";
+		cframe12_reg = "/amba_root@0/amba_pmc_pl@0/cframe12_reg@0xf12e8000";
+		cframe13_reg = "/amba_root@0/amba_pmc_pl@0/cframe13_reg@0xf12ea000";
+		cframe14_reg = "/amba_root@0/amba_pmc_pl@0/cframe14_reg@0xf12ec000";
+		cframe_bcast_reg = "/amba_root@0/amba_pmc_pl@0/cframe_bcast_reg@0xf12ee000";
+		hnicx_npi_0 = "/amba_root@0/amba_pmc_pl@0/hnicx_npi_0@0xf6af0000";
+		hnicx_pllpor_0 = "/amba_root@0/amba_pmc_pl@0/hnicx_pllpor_0@0xf6b30000";
+		dummy_cfu_mem = "/amba_root@0/amba_pmc_pl@0/dummy_cfu_mem@0xf12b0000";
+		cfu = "/amba_root@0/amba_pmc_pl@0/dummy_cfu_mem@0xf12b0000/cfu@0x0";
+		amba_pmc_bat = "/amba_root@0/amba_pmc_bat@0";
+		rtc = "/amba_root@0/amba_pmc_bat@0/rtc@0xf12a0000";
+		amba_psm = "/amba_root@0/amba_psm@0";
+		psm_ram_instr = "/amba_root@0/amba_psm@0/psm_ram_instr@0xebc00000";
+		psm_ram_data = "/amba_root@0/amba_psm@0/psm_ram_data@0xebc20000";
+		psm_gic_proxy = "/amba_root@0/amba_psm@0/psm_gic_proxy@0";
+		psm_global = "/amba_root@0/amba_psm@0/psm_global_reg@0xebc90000";
+		psm_err_mng = "/amba_root@0/amba_psm@0/psm_err_mng@0xebc90000";
+		amba_xram = "/amba_root@0/amba_xram@0";
+		crf = "/amba_root@0/crf@0xec200000";
+		lmb_pmc_ppu0 = "/lmb_pmc_ppu0@0";
+		pmc_rom = "/lmb_pmc_ppu0@0/pmc_rom@0xf0000000";
+		pmc_ppu0_ram = "/lmb_pmc_ppu0@0/ppu0_ram@0xf0060000";
+		pmc_ppu0_io_module = "/lmb_pmc_ppu0@0/io-module@00";
+		pmc_ppu0_io_intc = "/lmb_pmc_ppu0@0/io-module@00/pmc_ppu0_intc@0C";
+		pmc_ppu0_io_gpi1 = "/lmb_pmc_ppu0@0/io-module@00/pmc_ppu0_gpi@20";
+		pmc_ppu0_io_gpi2 = "/lmb_pmc_ppu0@0/io-module@00/pmc_ppu0_gpi@24";
+		pmc_ppu0_io_gpi3 = "/lmb_pmc_ppu0@0/io-module@00/pmc_ppu0_gpi@28";
+		pmc_ppu0_io_gpi4 = "/lmb_pmc_ppu0@0/io-module@00/pmc_ppu0_gpi@2c";
+		pmc_ppu0_io_gpo1 = "/lmb_pmc_ppu0@0/io-module@00/pmc_ppu0_gpo@10";
+		pmc_ppu0_io_gpo2 = "/lmb_pmc_ppu0@0/io-module@00/pmc_ppu0_gpo@14";
+		pmc_ppu0_io_gpo3 = "/lmb_pmc_ppu0@0/io-module@00/pmc_ppu0_gpo@18";
+		pmc_ppu0_io_gpo4 = "/lmb_pmc_ppu0@0/io-module@00/pmc_ppu0_gpo@1c";
+		pmc_ppu0_io_pit1 = "/lmb_pmc_ppu0@0/io-module@00/pmc_ppu0_pit@40";
+		pmc_ppu0_io_pit2 = "/lmb_pmc_ppu0@0/io-module@00/pmc_ppu0_pit@50";
+		pmc_ppu0_io_pit3 = "/lmb_pmc_ppu0@0/io-module@00/pmc_ppu0_pit@60";
+		pmc_ppu0_io_pit4 = "/lmb_pmc_ppu0@0/io-module@00/pmc_ppu0_pit@70";
+		lmb_pmc_ppu1 = "/lmb_pmc_ppu1@0";
+		pmc_ppu1_io_module = "/lmb_pmc_ppu1@0/io-module@00";
+		pmc_ppu1_io_intc = "/lmb_pmc_ppu1@0/io-module@00/pmc_ppu1_intc@0C";
+		pmc_ppu1_io_gpi1 = "/lmb_pmc_ppu1@0/io-module@00/pmc_ppu1_gpi@20";
+		pmc_ppu1_io_gpi2 = "/lmb_pmc_ppu1@0/io-module@00/pmc_ppu1_gpi@24";
+		pmc_ppu1_io_gpi3 = "/lmb_pmc_ppu1@0/io-module@00/pmc_ppu1_gpi@28";
+		pmc_ppu1_io_gpi4 = "/lmb_pmc_ppu1@0/io-module@00/pmc_ppu1_gpi@2c";
+		pmc_ppu1_io_gpo1 = "/lmb_pmc_ppu1@0/io-module@00/pmc_ppu1_gpo@10";
+		pmc_ppu1_io_gpo2 = "/lmb_pmc_ppu1@0/io-module@00/pmc_ppu1_gpo@14";
+		pmc_ppu1_io_gpo3 = "/lmb_pmc_ppu1@0/io-module@00/pmc_ppu1_gpo@18";
+		pmc_ppu1_io_gpo4 = "/lmb_pmc_ppu1@0/io-module@00/pmc_ppu1_gpo@1c";
+		pmc_ppu1_io_pit1 = "/lmb_pmc_ppu1@0/io-module@00/pmc_ppu1_pit@40";
+		pmc_ppu1_io_pit2 = "/lmb_pmc_ppu1@0/io-module@00/pmc_ppu1_pit@50";
+		pmc_ppu1_io_pit3 = "/lmb_pmc_ppu1@0/io-module@00/pmc_ppu1_pit@60";
+		pmc_ppu1_io_pit4 = "/lmb_pmc_ppu1@0/io-module@00/pmc_ppu1_pit@70";
+		lmb_psm = "/lmb_psm@0";
+		psm_0_io_module = "/lmb_psm@0/io-module@00";
+		psm0_io_intc = "/lmb_psm@0/io-module@00/psm0_intc@0C";
+		psm0_io_gpo1 = "/lmb_psm@0/io-module@00/psm0_gpo@10";
+		psm0_io_pit1 = "/lmb_psm@0/io-module@00/psm0_pit@40";
+		psm0_io_pit2 = "/lmb_psm@0/io-module@00/psm0_pit@50";
+		psm0_io_pit3 = "/lmb_psm@0/io-module@00/psm0_pit@60";
+		psm0_io_pit4 = "/lmb_psm@0/io-module@00/psm0_pit@70";
+		psm_local = "/lmb_psm@0/psm_local_reg@0xebc88000";
+		lmb_ddrmc0 = "/lmb_ddrmc@0";
+		ddrmc0_ram_data = "/lmb_ddrmc@0/ddrmc0_ram_data@0x1c000";
+		ddrmc0_ram_instr = "/lmb_ddrmc@0/ddrmc0_ram_instr@0x20000";
+		ddrmc0_ram_exchange = "/lmb_ddrmc@0/ddrmc0_ram_exchange@0x08000";
+		ddrmc_0_io_module = "/lmb_ddrmc@0/io-module@00";
+		ddrmc0_io_intc = "/lmb_ddrmc@0/io-module@00/ddrmc0_intc@0C";
+		ddrmc0_io_gpo1 = "/lmb_ddrmc@0/io-module@00/ddrmc0_gpo@10";
+		ddrmc0_io_pit1 = "/lmb_ddrmc@0/io-module@00/ddrmc0_pit@40";
+		ddrmc0_io_pit2 = "/lmb_ddrmc@0/io-module@00/ddrmc0_pit@50";
+		ddrmc0_io_pit3 = "/lmb_ddrmc@0/io-module@00/ddrmc0_pit@60";
+		ddrmc0_io_pit4 = "/lmb_ddrmc@0/io-module@00/ddrmc0_pit@70";
+		ddrmc_uart0 = "/lmb_ddrmc@0/ddrmc_uart0@0";
+		lmb_ddrmc1 = "/lmb_ddrmc@1";
+		ddrmc1_ram_data = "/lmb_ddrmc@1/ddrmc1_ram_data@0x1c000";
+		ddrmc1_ram_instr = "/lmb_ddrmc@1/ddrmc1_ram_instr@0x20000";
+		ddrmc1_ram_exchange = "/lmb_ddrmc@1/ddrmc1_ram_exchange@0x08000";
+		amba_rpu = "/amba_rpu@0";
+		amba_r5_0 = "/amba_r5@0";
+		amba_r5_1 = "/amba_r5@1";
+		dummy1 = "/dummy1@0";
+		smmu_tbu0 = "/tbu0_slave@0";
+		smmu_tbu1 = "/tbu1_slave@0";
+		smmu_tbu2 = "/tbu2_slave@0";
+		smmu_tbu3 = "/tbu3_slave@0";
+		smmu_tbu4 = "/tbu4_slave@0";
+		smmu_tbu5 = "/tbu5_slave@0";
+		smmu_tbu6 = "/tbu6_slave@0";
+		ddr_mem = "/memory@00000000";
+		ddr_2_mem = "/memory@8_0000_0000";
+		ddr_3_mem = "/memory@0x50000000000ULL";
+		ocm_mem = "/ocm_mem@0xbbf00000";
+		ocm_mem_bank_0 = "/ocm_mem_bank_0@";
+		ocm_mem_bank_1 = "/ocm_mem_bank_1@";
+		ocm_mem_bank_2 = "/ocm_mem_bank_2@";
+		ocm_mem_bank_3 = "/ocm_mem_bank_3@";
+		xram_mem = "/xram_mem@0xea800000";
+		xram_mem_bank_0 = "/xram_mem_bank_0@0x0";
+		xram_mem_bank_1 = "/xram_mem_bank_1@0x200000";
+		xram_mem_bank_2 = "/xram_mem_bank_2@0x400000";
+		xram_mem_bank_3 = "/xram_mem_bank_3@0x600000";
+		ipi_msgbuf = "/ipi_msgbuf@0";
+		pmc_ram = "/pmc_ram@0xf2000000";
+		pmc_ram_bank_0 = "/pmc_ram_bank_0@0x0";
+		pmc_ppu1_insn_ram = "/pmc_ppu1_ram@0xf0200000";
+		pmc_ppu1_data_ram = "/pmc_ppu1_ram@0xf0280000";
+		lqspi_mr = "/lqspi_mr@0";
+		lospi_mr = "/lospi_mr@0";
+		cpu0 = "/cpus/apu_cpu@0";
+		cpu1 = "/cpus/apu_cpu@1";
+		cpu2 = "/cpus/apu_cpu@2";
+		cpu3 = "/cpus/apu_cpu@3";
+		cpu4 = "/cpus/apu_cpu@4";
+		cpu5 = "/cpus/apu_cpu@5";
+		cpu6 = "/cpus/apu_cpu@6";
+		cpu7 = "/cpus/apu_cpu@7";
+		cpu8 = "/cpus/apu_cpu@8";
+		cpu9 = "/cpus/apu_cpu@9";
+		cpu10 = "/cpus/apu_cpu@10";
+		cpu11 = "/cpus/apu_cpu@11";
+		cpu12 = "/cpus/apu_cpu@12";
+		cpu13 = "/cpus/apu_cpu@13";
+		cpu14 = "/cpus/apu_cpu@14";
+		cpu15 = "/cpus/apu_cpu@15";
+		rpu_a = "/cpus/rpu_a@0";
+		rpu_cpu0 = "/cpus/rpu_a@0/rpu_cpu_a@0";
+		rpu_cpu1 = "/cpus/rpu_a@0/rpu_cpu_a@1";
+		rpu_b = "/cpus/rpu_b@0";
+		rpu_cpu2 = "/cpus/rpu_b@0/rpu_cpu_b@0";
+		rpu_cpu3 = "/cpus/rpu_b@0/rpu_cpu_b@1";
+		amba_apu = "/amba_apu@0";
+		timer = "/amba_apu@0/timer";
+		amba_apu_gic = "/amba_apu_gic@0";
+		gic = "/amba_apu_gic@0/interrupt-controller@0xe2000000";
+		amba_alias = "/amba_alias@0";
+		qemu_sysmem = "/qemu_sysmem@0";
+		psm0 = "/dummy_ppu0@0";
+		pmc_ppu0 = "/dummy_ppu0@0";
+		pmc_ppu1 = "/dummy_ppu1@0";
+		ddrmc_ub0 = "/dummy_ddrmc0@0";
+		ddrmc_ub1 = "/dummy_ddrmc1@0";
+		ddr = "/ddr@0x00000000";
+		ddr_2 = "/ddr_2@0x800000000ULL";
+		mdio0 = "/mdio";
+		phy0 = "/mdio/phy@1";
+		cpunone = "/cpu_dummy";
+		smmu_tbu7 = "/tbu7_slave@0";
+		smmu_tbu8 = "/tbu8_slave@0";
+		smmu_tbu9 = "/tbu9_slave@0";
+		smmu_tbu10 = "/tbu10_slave@0";
+		smmu_tbu11 = "/tbu11_slave@0";
+		smmu_tbu12 = "/tbu12_slave@0";
+		mr_rpu_gic_a = "/mr_rpu_gic_a@0";
+		rpu_gic_a = "/mr_rpu_gic_a@0/rpu_gic_a@0x0";
+		mr_rpu_gic_b = "/mr_rpu_gic_b@0";
+		rpu_gic_b = "/mr_rpu_gic_b@0/rpu_gic_b@0x0";
+		tcm_core0 = "/tcm_core@0";
+		atcm_rpu_core0 = "/tcm_core@0/atcm_rpu_core0@0x00000";
+		btcm_rpu_core0 = "/tcm_core@0/btcm_rpu_core0@0x00000";
+		ctcm_rpu_core0 = "/tcm_core@0/ctcm_rpu_core0@0x00000";
+		tcm_core1 = "/tcm_core@1";
+		atcm_rpu_core1 = "/tcm_core@1/atcm_rpu_core1@0x00000";
+		btcm_rpu_core1 = "/tcm_core@1/btcm_rpu_core1@0x00000";
+		ctcm_rpu_core1 = "/tcm_core@1/ctcm_rpu_core1@0x00000";
+		tcm_core2 = "/tcm_core@2";
+		atcm_rpu_core2 = "/tcm_core@2/atcm_rpu_core2@0x00000";
+		btcm_rpu_core2 = "/tcm_core@2/btcm_rpu_core2@0x00000";
+		ctcm_rpu_core2 = "/tcm_core@2/ctcm_rpu_core2@0x00000";
+		tcm_core3 = "/tcm_core@3";
+		atcm_rpu_core3 = "/tcm_core@3/atcm_rpu_core3@0x00000";
+		btcm_rpu_core3 = "/tcm_core@3/btcm_rpu_core3@0x00000";
+		ctcm_rpu_core3 = "/tcm_core@3/ctcm_rpu_core3@0x00000";
+		tcm_cluster_a = "/tcm_cluster_a@0";
+		tcm_cluster_b = "/tcm_cluster_b@0";
+		amba_r5_2 = "/amba_r5@2";
+		amba_r5_3 = "/amba_r5@3";
+		rpu2_s_memattr = "/rpu2_s_ma";
+		rpu3_s_memattr = "/rpu3_s_ma";
+		usb1_memattr = "/usb1_ma";
+	};
+};
diff --git a/boards/amd/versalnet_apu/versalnet_apu.dts b/boards/amd/versalnet_apu/versalnet_apu.dts
new file mode 100644
index 0000000000000..5ee2b9710f60c
--- /dev/null
+++ b/boards/amd/versalnet_apu/versalnet_apu.dts
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2025, Advanced Micro Devices, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+#include <arm64/xilinx/versalnet_a78.dtsi>
+
+/ {
+	chosen {
+		zephyr,sram = &sram0;
+		zephyr,console = &uart0;
+		zephyr,shell-uart = &uart0;
+	};
+};
+
+&cpu0 {
+	 clock-frequency = <100000000>;
+};
+
+&soc {
+	sram0: memory@0 {
+		compatible = "mmio-sram";
+		reg = <0x0 0x0 0x0 DT_SIZE_M(2048)>;
+	};
+};
+
+&uart1 {
+	status = "okay";
+	current-speed = <115200>;
+	clock-frequency = <100000000>;
+};
+
+&uart0 {
+	status = "okay";
+	current-speed = <115200>;
+	clock-frequency = <100000000>;
+};
diff --git a/boards/amd/versalnet_apu/versalnet_apu.yaml b/boards/amd/versalnet_apu/versalnet_apu.yaml
new file mode 100644
index 0000000000000..2a3825fdd5721
--- /dev/null
+++ b/boards/amd/versalnet_apu/versalnet_apu.yaml
@@ -0,0 +1,11 @@
+identifier: versalnet_apu
+name: AMD Development board for Versal NET APU
+arch: arm
+toolchain:
+  - zephyr
+testing:
+  ignore_tags:
+    - net
+    - bluetooth
+    - fpu
+vendor: amd
diff --git a/boards/amd/versalnet_apu/versalnet_apu_defconfig b/boards/amd/versalnet_apu/versalnet_apu_defconfig
new file mode 100644
index 0000000000000..7cfeda9524115
--- /dev/null
+++ b/boards/amd/versalnet_apu/versalnet_apu_defconfig
@@ -0,0 +1,27 @@
+# The Zephyr build from this defconfig is expected to boot from
+# Xilinx Arm Trusted Firmware (ATF).
+# Boot Flow is: Boot PDI -> TF-A -> Zephyr
+
+CONFIG_ARM64_VA_BITS_40=y
+CONFIG_ARM64_PA_BITS_40=y
+CONFIG_TIMER_READS_ITS_FREQUENCY_AT_RUNTIME=y
+
+# Enable UART driver
+CONFIG_SERIAL=y
+
+# Enable console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+
+# Enable serial port
+CONFIG_UART_PL011=y
+
+# This should be commented in order to test at EL1 S (EL1 Secure)
+CONFIG_ARMV8_A_NS=y
+
+# FPU support is disabled due to QEMU limitations. When CONFIG_FPU_SHARING
+# is enabled, it uses the swpal instruction which QEMU does not emulate.
+# If testing is targeted on real hardware and FPU operations are needed,
+# comment the lines below.
+CONFIG_FPU=n
+CONFIG_FPU_SHARING=n
diff --git a/cmake/gcc-m-cpu.cmake b/cmake/gcc-m-cpu.cmake
index 75b13fa423844..d95180b78d73b 100644
--- a/cmake/gcc-m-cpu.cmake
+++ b/cmake/gcc-m-cpu.cmake
@@ -103,6 +103,8 @@ elseif("${ARCH}" STREQUAL "arm64")
     set(GCC_M_TUNE cortex-a76.cortex-a55)
   elseif(CONFIG_CPU_CORTEX_A72)
     set(GCC_M_CPU cortex-a72)
+  elseif(CONFIG_CPU_CORTEX_A78)
+    set(GCC_M_CPU cortex-a78)
   elseif(CONFIG_CPU_CORTEX_R82)
     set(GCC_M_CPU cortex-r82)
   endif()
diff --git a/dts/arm64/xilinx/versalnet_a78.dtsi b/dts/arm64/xilinx/versalnet_a78.dtsi
new file mode 100644
index 0000000000000..35d913df84112
--- /dev/null
+++ b/dts/arm64/xilinx/versalnet_a78.dtsi
@@ -0,0 +1,79 @@
+/*
+ * Copyright (c) 2025, Advanced Micro Devices, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <mem.h>
+#include <arm64/armv8-a.dtsi>
+#include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
+#include <amd/versalnet_apu.dtsi>
+
+/ {
+	model = "Versal NET APU";
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a78";
+			reg = <0>;
+			enable-method = "psci";
+		};
+
+		cpu100: cpu@100 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a78";
+			enable-method = "psci";
+			reg = <0x100>;
+		};
+
+		cpu200: cpu@200 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a78";
+			enable-method = "psci";
+			reg = <0x200>;
+		};
+
+		cpu300: cpu@300 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a78";
+			enable-method = "psci";
+			reg = <0x300>;
+		};
+	};
+
+	psci {
+		compatible = "arm,psci-1.1";
+		method = "smc";
+	};
+
+	arch_timer: timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+			     <GIC_PPI 14 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+			     <GIC_PPI 11 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+			     <GIC_PPI 10 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+		interrupt-parent = <&gic>;
+	};
+};
+
+&soc {
+	interrupt-parent = <&gic>;
+
+	gic: interrupt-controller@e2000000 {
+		compatible = "arm,gic-v3", "arm,gic";
+		reg = <0x0 0xe2000000 0x0 0x10000>,
+		      <0x0 0xe2060000 0x0 0x200000>;
+		interrupt-controller;
+		#interrupt-cells = <4>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+	};
+};
diff --git a/dts/bindings/cpu/arm,cortex-a78.yaml b/dts/bindings/cpu/arm,cortex-a78.yaml
new file mode 100644
index 0000000000000..1c7f167c9b698
--- /dev/null
+++ b/dts/bindings/cpu/arm,cortex-a78.yaml
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: Apache-2.0
+
+description: ARM Cortex-A78 CPU
+
+compatible: "arm,cortex-a78"
+
+include: cpu.yaml
diff --git a/dts/vendor/amd/versalnet_apu.dtsi b/dts/vendor/amd/versalnet_apu.dtsi
new file mode 100644
index 0000000000000..14af3aae67bb8
--- /dev/null
+++ b/dts/vendor/amd/versalnet_apu.dtsi
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2025, Advanced Micro Devices, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	soc: soc {
+		#address-cells = <2>;
+		#size-cells = <2>;
+
+		/*
+		 * OCM (On-Chip Memory) is used by TF-A (Trusted Firmware-A) by default.
+		 * Enable this node only if TF-A is not using this memory region or if
+		 * explicit coordination is established between TF-A and Zephyr.
+		 */
+		ocm: memory@bbf00000 {
+			compatible = "zephyr,memory-region";
+			reg = <0x0 0xbbf00000 0x0 DT_SIZE_M(1)>;
+			status = "disabled";
+			zephyr,memory-region = "OCM";
+		};
+
+		uart0: uart@f1920000 {
+			compatible = "arm,sbsa-uart";
+			reg = <0x0 0xf1920000 0x0 0x4c>;
+			status = "disabled";
+			interrupt-names = "irq_0";
+			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+		};
+
+		uart1: uart@f1930000 {
+			compatible = "arm,sbsa-uart";
+			reg = <0x0 0xf1930000 0x0 0x1000>;
+			status = "disabled";
+			interrupt-names = "irq_1";
+			interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+		};
+	};
+};
diff --git a/soc/xlnx/versalnet/CMakeLists.txt b/soc/xlnx/versalnet/CMakeLists.txt
index a6ccdf4f20302..489b2d1129d09 100644
--- a/soc/xlnx/versalnet/CMakeLists.txt
+++ b/soc/xlnx/versalnet/CMakeLists.txt
@@ -4,12 +4,14 @@
 # SPDX-License-Identifier: Apache-2.0
 #
 
-zephyr_sources(
-  soc.c
-)
 zephyr_sources_ifdef(
   CONFIG_ARM_MPU
   arm_mpu_regions.c
+  soc.c
+)
+zephyr_sources_ifdef(
+  CONFIG_ARM_MMU
+  arm_mmu_regions.c
 )
 
 zephyr_include_directories(.)
@@ -17,3 +19,7 @@ zephyr_include_directories(.)
 if(CONFIG_SOC_AMD_VERSALNET_RPU)
   set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_a_r/scripts/linker.ld CACHE INTERNAL "")
 endif()
+
+if(CONFIG_SOC_AMD_VERSALNET_APU)
+  set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm64/scripts/linker.ld CACHE INTERNAL "")
+endif()
diff --git a/soc/xlnx/versalnet/Kconfig b/soc/xlnx/versalnet/Kconfig
index 89e185d62664a..952cd8651abd0 100644
--- a/soc/xlnx/versalnet/Kconfig
+++ b/soc/xlnx/versalnet/Kconfig
@@ -13,3 +13,9 @@ config SOC_AMD_VERSALNET_RPU
 	select GIC_SINGLE_SECURITY_STATE
 	select CPU_HAS_ARM_MPU
 	select ARM_MPU
+
+config SOC_AMD_VERSALNET_APU
+	select ARM64
+	select ARM_ARCH_TIMER
+	select CPU_CORTEX_A78
+	select CPU_HAS_MMU
diff --git a/soc/xlnx/versalnet/Kconfig.defconfig b/soc/xlnx/versalnet/Kconfig.defconfig
index 7997b8feb6962..03ae4c6888bbf 100644
--- a/soc/xlnx/versalnet/Kconfig.defconfig
+++ b/soc/xlnx/versalnet/Kconfig.defconfig
@@ -22,4 +22,19 @@ config SYS_CLOCK_HW_CYCLES_PER_SEC
 
 endif # SOC_AMD_VERSALNET_RPU
 
+if SOC_AMD_VERSALNET_APU
+
+CONFIG_CACHE_MANAGEMENT=y
+CONFIG_ARM_ARCH_TIMER=y
+CONFIG_CACHE_MANAGEMENT=y
+
+config NUM_IRQS
+	# must be >= the highest interrupt number used
+	# - include the UART interrupts
+	default 256
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency)
+
+endif # SOC_AMD_VERSALNET_APU
 endif # SOC_AMD_VERSALNET
diff --git a/soc/xlnx/versalnet/Kconfig.soc b/soc/xlnx/versalnet/Kconfig.soc
index 181a2100d9bf3..f2eb665b03378 100644
--- a/soc/xlnx/versalnet/Kconfig.soc
+++ b/soc/xlnx/versalnet/Kconfig.soc
@@ -11,10 +11,17 @@ config SOC_AMD_VERSALNET_RPU
 	bool
 	select SOC_AMD_VERSALNET
 	help
-	  AMD Versal NET SoC
+	  AMD Versal NET SoC RPU
+
+config SOC_AMD_VERSALNET_APU
+	bool
+	select SOC_AMD_VERSALNET
+	help
+	  AMD Versal NET SoC APU
 
 config SOC_FAMILY
 	default "amd_versalnet" if SOC_AMD_VERSALNET
 
 config SOC
 	default "amd_versalnet_rpu" if SOC_AMD_VERSALNET_RPU
+	default "amd_versalnet_apu" if SOC_AMD_VERSALNET_APU
diff --git a/soc/xlnx/versalnet/arm_mmu_regions.c b/soc/xlnx/versalnet/arm_mmu_regions.c
new file mode 100644
index 0000000000000..11a5f09f55b53
--- /dev/null
+++ b/soc/xlnx/versalnet/arm_mmu_regions.c
@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2025 Advanced Micro Devices, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/arch/arm64/arm_mmu.h>
+#include <zephyr/devicetree.h>
+#include <zephyr/sys/util.h>
+
+static const struct arm_mmu_region mmu_regions[] = {
+	MMU_REGION_FLAT_ENTRY("GIC",
+			      DT_REG_ADDR_BY_IDX(DT_INST(0, arm_gic), 0),
+			      DT_REG_SIZE_BY_IDX(DT_INST(0, arm_gic), 0),
+			      MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_DEFAULT_SECURE_STATE),
+
+	MMU_REGION_FLAT_ENTRY("GIC",
+			      DT_REG_ADDR_BY_IDX(DT_INST(0, arm_gic), 1),
+			      DT_REG_SIZE_BY_IDX(DT_INST(0, arm_gic), 1),
+			      MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_DEFAULT_SECURE_STATE),
+};
+
+const struct arm_mmu_config mmu_config = {
+	.num_regions = ARRAY_SIZE(mmu_regions),
+	.mmu_regions = mmu_regions,
+};
diff --git a/soc/xlnx/versalnet/soc.yml b/soc/xlnx/versalnet/soc.yml
index 8de1e6c40f4fa..9f206c8424f41 100644
--- a/soc/xlnx/versalnet/soc.yml
+++ b/soc/xlnx/versalnet/soc.yml
@@ -2,3 +2,4 @@ family:
 - name: amd_versalnet
   socs:
   - name: amd_versalnet_rpu
+  - name: amd_versalnet_apu
diff --git a/subsys/mgmt/mcumgr/grp/os_mgmt/include/os_mgmt_processor.h b/subsys/mgmt/mcumgr/grp/os_mgmt/include/os_mgmt_processor.h
index de1bdf7e34d27..b0ab26968a1f6 100644
--- a/subsys/mgmt/mcumgr/grp/os_mgmt/include/os_mgmt_processor.h
+++ b/subsys/mgmt/mcumgr/grp/os_mgmt/include/os_mgmt_processor.h
@@ -121,6 +121,8 @@ extern "C" {
 #define PROCESSOR_NAME "cortex-a76"
 #elif defined(CONFIG_CPU_CORTEX_A76)
 #define PROCESSOR_NAME "cortex-a76"
+#elif defined(CONFIG_CPU_CORTEX_A78)
+#define PROCESSOR_NAME "cortex-a78"
 #elif defined(CONFIG_CPU_CORTEX_R82)
 #define PROCESSOR_NAME "armv8.4-a+nolse"
 #endif