From 332c65b0cf96fa760d61f11f0b47a9bb39477729 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Tom=C3=A1=C5=A1=20Ju=C5=99ena?= Date: Wed, 9 Jul 2025 08:54:16 +0200 Subject: [PATCH 1/2] include: zephyr: dt-bindings: Fix USB_SEL mask MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Selecting the clock source for USB is only a bit value in the CCIPR2 register. See RM0490 Rev 5 chapter 6.4.21 page 159. Signed-off-by: Tomáš Juřena --- include/zephyr/dt-bindings/clock/stm32c0_clock.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/zephyr/dt-bindings/clock/stm32c0_clock.h b/include/zephyr/dt-bindings/clock/stm32c0_clock.h index 2489c48f1e93..0a5e8348be96 100644 --- a/include/zephyr/dt-bindings/clock/stm32c0_clock.h +++ b/include/zephyr/dt-bindings/clock/stm32c0_clock.h @@ -46,7 +46,7 @@ #define I2C2_I2S1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 14, CCIPR_REG) #define ADC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 30, CCIPR_REG) /** CCIPR2 devices */ -#define USB_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 12, CCIPR2_REG) +#define USB_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 12, CCIPR2_REG) /** CSR1 devices */ #define RTC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, CSR1_REG) From 2bf77448e3fd6407ea8ca7c9953958a3d0aa90ba Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Tom=C3=A1=C5=A1=20Ju=C5=99ena?= Date: Thu, 10 Jul 2025 16:35:07 +0200 Subject: [PATCH 2/2] include: zephyr: dt-bindings: Fix MCOx_yyy masks MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Macros MCO1_SEL, MCO1_PRE, MCO2_SEL, MCO2_PRE uses 4 bits wide masks as defined in the RM0490 Rev 5 section 6.4.3, page 136 Signed-off-by: Tomáš Juřena --- include/zephyr/dt-bindings/clock/stm32c0_clock.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/include/zephyr/dt-bindings/clock/stm32c0_clock.h b/include/zephyr/dt-bindings/clock/stm32c0_clock.h index 0a5e8348be96..db156eff349a 100644 --- a/include/zephyr/dt-bindings/clock/stm32c0_clock.h +++ b/include/zephyr/dt-bindings/clock/stm32c0_clock.h @@ -51,10 +51,10 @@ #define RTC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, CSR1_REG) /** CFGR1 devices */ -#define MCO1_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 24, CFGR1_REG) -#define MCO1_PRE(val) STM32_DT_CLOCK_SELECT((val), 0x7, 28, CFGR1_REG) -#define MCO2_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 16, CFGR1_REG) -#define MCO2_PRE(val) STM32_DT_CLOCK_SELECT((val), 0x7, 20, CFGR1_REG) +#define MCO1_SEL(val) STM32_DT_CLOCK_SELECT((val), 0xf, 24, CFGR1_REG) +#define MCO1_PRE(val) STM32_DT_CLOCK_SELECT((val), 0xf, 28, CFGR1_REG) +#define MCO2_SEL(val) STM32_DT_CLOCK_SELECT((val), 0xf, 16, CFGR1_REG) +#define MCO2_PRE(val) STM32_DT_CLOCK_SELECT((val), 0xf, 20, CFGR1_REG) /* MCO prescaler : division factor */ #define MCO_PRE_DIV_1 0