From 42dd7a903761b3af2a19e3a4831d01bf4b29560a Mon Sep 17 00:00:00 2001 From: James Smith Date: Tue, 8 Jul 2025 09:32:48 -0700 Subject: [PATCH 1/4] soc: silabs: Add support for MG22 SoCs Adds SoC definitions and DTS files for SiLabs EFR32MG22 SoCs Signed-off-by: James Smith --- dts/arm/silabs/xg22/efr32mg22.dtsi | 14 ++++ .../silabs/xg22/efr32mg22c224f512gn32.dtsi | 25 +++++++ .../silabs/xg22/efr32mg22c224f512im32.dtsi | 25 +++++++ .../silabs/xg22/efr32mg22c224f512im40.dtsi | 25 +++++++ .../silabs/xg22/efr32mg22e224f512im32.dtsi | 25 +++++++ .../silabs/xg22/efr32mg22e224f512im40.dtsi | 25 +++++++ .../clock_control/clock_control_silabs.h | 2 +- soc/silabs/silabs_s2/efr32bg22/Kconfig.soc | 21 ------ .../silabs_s2/{efr32bg22 => xg22}/Kconfig | 20 +++++- .../{efr32bg22 => xg22}/Kconfig.defconfig | 6 +- soc/silabs/silabs_s2/xg22/Kconfig.soc | 66 +++++++++++++++++++ soc/silabs/soc.yml | 7 ++ west.yml | 2 +- 13 files changed, 237 insertions(+), 26 deletions(-) create mode 100644 dts/arm/silabs/xg22/efr32mg22.dtsi create mode 100644 dts/arm/silabs/xg22/efr32mg22c224f512gn32.dtsi create mode 100644 dts/arm/silabs/xg22/efr32mg22c224f512im32.dtsi create mode 100644 dts/arm/silabs/xg22/efr32mg22c224f512im40.dtsi create mode 100644 dts/arm/silabs/xg22/efr32mg22e224f512im32.dtsi create mode 100644 dts/arm/silabs/xg22/efr32mg22e224f512im40.dtsi delete mode 100644 soc/silabs/silabs_s2/efr32bg22/Kconfig.soc rename soc/silabs/silabs_s2/{efr32bg22 => xg22}/Kconfig (52%) rename soc/silabs/silabs_s2/{efr32bg22 => xg22}/Kconfig.defconfig (72%) create mode 100644 soc/silabs/silabs_s2/xg22/Kconfig.soc diff --git a/dts/arm/silabs/xg22/efr32mg22.dtsi b/dts/arm/silabs/xg22/efr32mg22.dtsi new file mode 100644 index 0000000000000..9dc9bcba5069f --- /dev/null +++ b/dts/arm/silabs/xg22/efr32mg22.dtsi @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&radio { + bt_hci_silabs: bt_hci_silabs { + compatible = "silabs,bt-hci-efr32"; + status = "disabled"; + }; +}; diff --git a/dts/arm/silabs/xg22/efr32mg22c224f512gn32.dtsi b/dts/arm/silabs/xg22/efr32mg22c224f512gn32.dtsi new file mode 100644 index 0000000000000..fb53c0be96980 --- /dev/null +++ b/dts/arm/silabs/xg22/efr32mg22c224f512gn32.dtsi @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2021 Sateesh Kotapati + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + soc { + compatible = "silabs,efr32mg22c224f512gn32", "silabs,efr32mg22", "silabs,xg22", + "silabs,efr32", "simple-bus"; + model = "Silicon Labs EFR32MG22C224F512GN32 SoC"; + }; +}; + +&flash0 { + reg = <0x0 DT_SIZE_K(512)>; +}; + +&sram0 { + reg = <0x20000000 DT_SIZE_K(32)>; +}; diff --git a/dts/arm/silabs/xg22/efr32mg22c224f512im32.dtsi b/dts/arm/silabs/xg22/efr32mg22c224f512im32.dtsi new file mode 100644 index 0000000000000..f5880f0088433 --- /dev/null +++ b/dts/arm/silabs/xg22/efr32mg22c224f512im32.dtsi @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2021 Sateesh Kotapati + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + soc { + compatible = "silabs,efr32mg22c224f512im32", "silabs,efr32mg22", "silabs,xg22", + "silabs,efr32", "simple-bus"; + model = "Silicon Labs EFR32MG22C224F512IM32 SoC"; + }; +}; + +&flash0 { + reg = <0x0 DT_SIZE_K(512)>; +}; + +&sram0 { + reg = <0x20000000 DT_SIZE_K(32)>; +}; diff --git a/dts/arm/silabs/xg22/efr32mg22c224f512im40.dtsi b/dts/arm/silabs/xg22/efr32mg22c224f512im40.dtsi new file mode 100644 index 0000000000000..78537a9b8a12f --- /dev/null +++ b/dts/arm/silabs/xg22/efr32mg22c224f512im40.dtsi @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2021 Sateesh Kotapati + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + soc { + compatible = "silabs,efr32mg22c224f512im40", "silabs,efr32mg22", "silabs,xg22", + "silabs,efr32", "simple-bus"; + model = "Silicon Labs EFR32MG22C224F512IM40 SoC"; + }; +}; + +&flash0 { + reg = <0x0 DT_SIZE_K(512)>; +}; + +&sram0 { + reg = <0x20000000 DT_SIZE_K(32)>; +}; diff --git a/dts/arm/silabs/xg22/efr32mg22e224f512im32.dtsi b/dts/arm/silabs/xg22/efr32mg22e224f512im32.dtsi new file mode 100644 index 0000000000000..8ef633422a125 --- /dev/null +++ b/dts/arm/silabs/xg22/efr32mg22e224f512im32.dtsi @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2021 Sateesh Kotapati + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + soc { + compatible = "silabs,efr32mg22e224f512im32", "silabs,efr32mg22", "silabs,xg22", + "silabs,efr32", "simple-bus"; + model = "Silicon Labs EFR32MG22E224F512IM32 SoC"; + }; +}; + +&flash0 { + reg = <0x0 DT_SIZE_K(512)>; +}; + +&sram0 { + reg = <0x20000000 DT_SIZE_K(32)>; +}; diff --git a/dts/arm/silabs/xg22/efr32mg22e224f512im40.dtsi b/dts/arm/silabs/xg22/efr32mg22e224f512im40.dtsi new file mode 100644 index 0000000000000..d3ec40ceddbad --- /dev/null +++ b/dts/arm/silabs/xg22/efr32mg22e224f512im40.dtsi @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2021 Sateesh Kotapati + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + soc { + compatible = "silabs,efr32mg22e224f512im40", "silabs,efr32mg22", "silabs,xg22", + "silabs,efr32", "simple-bus"; + model = "Silicon Labs EFR32MG22E224F512IM40 SoC"; + }; +}; + +&flash0 { + reg = <0x0 DT_SIZE_K(512)>; +}; + +&sram0 { + reg = <0x20000000 DT_SIZE_K(32)>; +}; diff --git a/include/zephyr/drivers/clock_control/clock_control_silabs.h b/include/zephyr/drivers/clock_control/clock_control_silabs.h index 8c45b376d5b9a..c92cbacdfb533 100644 --- a/include/zephyr/drivers/clock_control/clock_control_silabs.h +++ b/include/zephyr/drivers/clock_control/clock_control_silabs.h @@ -11,7 +11,7 @@ #if defined(CONFIG_SOC_SERIES_EFR32MG21) #include -#elif defined(CONFIG_SOC_SERIES_EFR32BG22) +#elif defined(CONFIG_SOC_SERIES_XG22) #include #elif defined(CONFIG_SOC_SERIES_EFR32ZG23) #include diff --git a/soc/silabs/silabs_s2/efr32bg22/Kconfig.soc b/soc/silabs/silabs_s2/efr32bg22/Kconfig.soc deleted file mode 100644 index 5f3736fa5f505..0000000000000 --- a/soc/silabs/silabs_s2/efr32bg22/Kconfig.soc +++ /dev/null @@ -1,21 +0,0 @@ -# Copyright (c) 2021 Sateesh Kotapati -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_EFR32BG22 - bool - select SOC_FAMILY_SILABS_S2 - help - Silicon Labs EFR32BG22 (Blue Gecko) Series MCU - -config SOC_PART_NUMBER_EFR32BG22C224F512IM40 - bool - select SOC_SERIES_EFR32BG22 - -config SOC_SERIES - default "efr32bg22" if SOC_SERIES_EFR32BG22 - -config SOC - default "efr32bg22c224f512im40" if SOC_PART_NUMBER_EFR32BG22C224F512IM40 - -config SOC_PART_NUMBER - default "EFR32BG22C224F512IM40" if SOC_PART_NUMBER_EFR32BG22C224F512IM40 diff --git a/soc/silabs/silabs_s2/efr32bg22/Kconfig b/soc/silabs/silabs_s2/xg22/Kconfig similarity index 52% rename from soc/silabs/silabs_s2/efr32bg22/Kconfig rename to soc/silabs/silabs_s2/xg22/Kconfig index 5ac51ff898a39..61f38f68d5e88 100644 --- a/soc/silabs/silabs_s2/efr32bg22/Kconfig +++ b/soc/silabs/silabs_s2/xg22/Kconfig @@ -1,4 +1,5 @@ # Copyright (c) 2021 Sateesh Kotapati +# Copyright (c) 2025 James Smith # SPDX-License-Identifier: Apache-2.0 config SOC_SERIES_EFR32BG22 @@ -19,5 +20,20 @@ config SOC_SERIES_EFR32BG22 select SOC_GECKO_SE select HAS_PM -config SOC_GECKO_SDID - default 205 if SOC_SERIES_EFR32BG22 +config SOC_SERIES_EFR32MG22 + select ARM + select ARMV8_M_DSP + select ARM_TRUSTZONE_M + select CPU_CORTEX_M33 + select CPU_HAS_ARM_MPU + select CPU_HAS_ARM_SAU + select CPU_HAS_FPU + select HAS_SILABS_SISDK + select HAS_SWO + select SOC_GECKO_HAS_RADIO + select SOC_GECKO_GPIO + select SOC_GECKO_CMU + select SOC_GECKO_CORE + select SOC_GECKO_DEV_INIT + select SOC_GECKO_SE + select HAS_PM diff --git a/soc/silabs/silabs_s2/efr32bg22/Kconfig.defconfig b/soc/silabs/silabs_s2/xg22/Kconfig.defconfig similarity index 72% rename from soc/silabs/silabs_s2/efr32bg22/Kconfig.defconfig rename to soc/silabs/silabs_s2/xg22/Kconfig.defconfig index 2423ae5dedd1c..2ba5df8e4717d 100644 --- a/soc/silabs/silabs_s2/efr32bg22/Kconfig.defconfig +++ b/soc/silabs/silabs_s2/xg22/Kconfig.defconfig @@ -1,7 +1,8 @@ # Copyright (c) 2021 Sateesh Kotapati +# Copyright (c) 2025 James Smith # SPDX-License-Identifier: Apache-2.0 -if SOC_SERIES_EFR32BG22 +if SOC_SERIES_XG22 config NUM_IRQS # must be >= the highest interrupt number used @@ -13,4 +14,7 @@ config PM config GPIO_GECKO default y +config SOC_GECKO_SDID + default 205 + endif diff --git a/soc/silabs/silabs_s2/xg22/Kconfig.soc b/soc/silabs/silabs_s2/xg22/Kconfig.soc new file mode 100644 index 0000000000000..746967536d236 --- /dev/null +++ b/soc/silabs/silabs_s2/xg22/Kconfig.soc @@ -0,0 +1,66 @@ +# Copyright (c) 2021 Sateesh Kotapati +# Copyright (c) 2025 James Smith +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_XG22 + bool + help + Silicon Labs EFR32 22 Series SoC and modules + +config SOC_SERIES_EFR32BG22 + bool + select SOC_FAMILY_SILABS_S2 + select SOC_SERIES_XG22 + help + Silicon Labs EFR32BG22 (Blue Gecko) Series MCU + +config SOC_SERIES_EFR32MG22 + bool + select SOC_FAMILY_SILABS_S2 + select SOC_SERIES_XG22 + help + Silicon Labs EFR32MG22 (Mighty Gecko) Series MCU + +config SOC_PART_NUMBER_EFR32BG22C224F512IM40 + bool + select SOC_SERIES_EFR32BG22 + +config SOC_PART_NUMBER_EFR32MG22C224F512IM40 + bool + select SOC_SERIES_EFR32MG22 + +config SOC_PART_NUMBER_EFR32MG22C224F512IM32 + bool + select SOC_SERIES_EFR32MG22 + +config SOC_PART_NUMBER_EFR32MG22C224F512GN32 + bool + select SOC_SERIES_EFR32MG22 + +config SOC_PART_NUMBER_EFR32MG22E224F512IM40 + bool + select SOC_SERIES_EFR32MG22 + +config SOC_PART_NUMBER_EFR32MG22E224F512IM32 + bool + select SOC_SERIES_EFR32MG22 + +config SOC_SERIES + default "efr32bg22" if SOC_SERIES_EFR32BG22 + default "efr32mg22" if SOC_SERIES_EFR32MG22 + +config SOC + default "efr32bg22c224f512im40" if SOC_PART_NUMBER_EFR32BG22C224F512IM40 + default "efr32mg22c224f512im40" if SOC_PART_NUMBER_EFR32MG22C224F512IM40 + default "efr32mg22c224f512im32" if SOC_PART_NUMBER_EFR32MG22C224F512IM32 + default "efr32mg22c224f512gn32" if SOC_PART_NUMBER_EFR32MG22C224F512GN32 + default "efr32mg22e224f512im40" if SOC_PART_NUMBER_EFR32MG22E224F512IM40 + default "efr32mg22e224f512im32" if SOC_PART_NUMBER_EFR32MG22E224F512IM32 + +config SOC_PART_NUMBER + default "EFR32BG22C224F512IM40" if SOC_PART_NUMBER_EFR32BG22C224F512IM40 + default "EFR32MG22C224F512IM40" if SOC_PART_NUMBER_EFR32MG22C224F512IM40 + default "EFR32MG22C224F512IM32" if SOC_PART_NUMBER_EFR32MG22C224F512IM32 + default "EFR32MG22C224F512GN32" if SOC_PART_NUMBER_EFR32MG22C224F512GN32 + default "EFR32MG22E224F512IM40" if SOC_PART_NUMBER_EFR32MG22E224F512IM40 + default "EFR32MG22E224F512IM32" if SOC_PART_NUMBER_EFR32MG22E224F512IM32 diff --git a/soc/silabs/soc.yml b/soc/silabs/soc.yml index 4617f804692d2..042a2528fb06a 100644 --- a/soc/silabs/soc.yml +++ b/soc/silabs/soc.yml @@ -47,6 +47,13 @@ family: - name: efr32bg22 socs: - name: efr32bg22c224f512im40 + - name: efr32mg22 + socs: + - name: efr32mg22c224f512im40 + - name: efr32mg22c224f512im32 + - name: efr32mg22c224f512gn32 + - name: efr32mg22e224f512im40 + - name: efr32mg22e224f512im32 - name: efr32mg24 socs: - name: efr32mg24b220f1536im48 diff --git a/west.yml b/west.yml index 92734c254ab4c..25df99dfac49f 100644 --- a/west.yml +++ b/west.yml @@ -235,7 +235,7 @@ manifest: groups: - hal - name: hal_silabs - revision: 190a144a16bed9a938a94543ed5bbc70c0552e0f + revision: pull/116/head path: modules/hal/silabs groups: - hal From bef043bfa2c0475a8e8a5a1c54911f2b4e6b51b9 Mon Sep 17 00:00:00 2001 From: James Smith Date: Tue, 8 Jul 2025 09:34:33 -0700 Subject: [PATCH 2/4] drivers: entropy: add support for EFR32MG22 SoCs Use CRYPTO_ACC_GECKO_TRNG for entropy on all xG22 SoCs. Signed-off-by: James Smith --- drivers/entropy/Kconfig.gecko | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/entropy/Kconfig.gecko b/drivers/entropy/Kconfig.gecko index e4990f32c93e5..6a0d481465472 100644 --- a/drivers/entropy/Kconfig.gecko +++ b/drivers/entropy/Kconfig.gecko @@ -9,7 +9,7 @@ config ENTROPY_GECKO_TRNG default y depends on DT_HAS_SILABS_GECKO_TRNG_ENABLED select ENTROPY_HAS_DRIVER - select CRYPTO_ACC_GECKO_TRNG if SOC_SERIES_EFR32BG22 + select CRYPTO_ACC_GECKO_TRNG if SOC_SERIES_XG22 select CRYPTO_ACC_GECKO_TRNG if SOC_SERIES_EFR32BG27 help This option enables the true random number generator From 9de0d5fa2b589bee0457300c6e81fdf9ba9b88c7 Mon Sep 17 00:00:00 2001 From: James Smith Date: Mon, 7 Jul 2025 14:26:18 -0700 Subject: [PATCH 3/4] soc: silabs: Add support for additional BG22 SoCs Adds all known EFR32BG22 SoCs and associated DTS includes. Signed-off-by: James Smith --- .../silabs/xg22/efr32bg22c222f352gm32.dtsi | 25 +++++++++++ .../silabs/xg22/efr32bg22c222f352gm40.dtsi | 25 +++++++++++ .../silabs/xg22/efr32bg22c222f352gn32.dtsi | 25 +++++++++++ .../silabs/xg22/efr32bg22c224f512gm32.dtsi | 25 +++++++++++ .../silabs/xg22/efr32bg22c224f512gm40.dtsi | 25 +++++++++++ .../silabs/xg22/efr32bg22c224f512gn32.dtsi | 25 +++++++++++ .../silabs/xg22/efr32bg22c224f512im32.dtsi | 25 +++++++++++ soc/silabs/silabs_s2/xg22/Kconfig.soc | 42 +++++++++++++++++++ soc/silabs/soc.yml | 7 ++++ 9 files changed, 224 insertions(+) create mode 100644 dts/arm/silabs/xg22/efr32bg22c222f352gm32.dtsi create mode 100644 dts/arm/silabs/xg22/efr32bg22c222f352gm40.dtsi create mode 100644 dts/arm/silabs/xg22/efr32bg22c222f352gn32.dtsi create mode 100644 dts/arm/silabs/xg22/efr32bg22c224f512gm32.dtsi create mode 100644 dts/arm/silabs/xg22/efr32bg22c224f512gm40.dtsi create mode 100644 dts/arm/silabs/xg22/efr32bg22c224f512gn32.dtsi create mode 100644 dts/arm/silabs/xg22/efr32bg22c224f512im32.dtsi diff --git a/dts/arm/silabs/xg22/efr32bg22c222f352gm32.dtsi b/dts/arm/silabs/xg22/efr32bg22c222f352gm32.dtsi new file mode 100644 index 0000000000000..af81087ced1d4 --- /dev/null +++ b/dts/arm/silabs/xg22/efr32bg22c222f352gm32.dtsi @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2021 Sateesh Kotapati + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + soc { + compatible = "silabs,efr32bg22c222f352gm32", "silabs,efr32bg22", "silabs,xg22", + "silabs,efr32", "simple-bus"; + model = "Silicon Labs EFR32BG22C222F352GM32 SoC"; + }; +}; + +&flash0 { + reg = <0x0 DT_SIZE_K(352)>; +}; + +&sram0 { + reg = <0x20000000 DT_SIZE_K(32)>; +}; diff --git a/dts/arm/silabs/xg22/efr32bg22c222f352gm40.dtsi b/dts/arm/silabs/xg22/efr32bg22c222f352gm40.dtsi new file mode 100644 index 0000000000000..4e201fe7a6509 --- /dev/null +++ b/dts/arm/silabs/xg22/efr32bg22c222f352gm40.dtsi @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2021 Sateesh Kotapati + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + soc { + compatible = "silabs,efr32bg22c222f352gm40", "silabs,efr32bg22", "silabs,xg22", + "silabs,efr32", "simple-bus"; + model = "Silicon Labs EFR32BG22C222F352GM40 SoC"; + }; +}; + +&flash0 { + reg = <0x0 DT_SIZE_K(352)>; +}; + +&sram0 { + reg = <0x20000000 DT_SIZE_K(32)>; +}; diff --git a/dts/arm/silabs/xg22/efr32bg22c222f352gn32.dtsi b/dts/arm/silabs/xg22/efr32bg22c222f352gn32.dtsi new file mode 100644 index 0000000000000..1810cd7384960 --- /dev/null +++ b/dts/arm/silabs/xg22/efr32bg22c222f352gn32.dtsi @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2021 Sateesh Kotapati + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + soc { + compatible = "silabs,efr32bg22c222f352gn32", "silabs,efr32bg22", "silabs,xg22", + "silabs,efr32", "simple-bus"; + model = "Silicon Labs EFR32BG22C222F352GN32 SoC"; + }; +}; + +&flash0 { + reg = <0x0 DT_SIZE_K(352)>; +}; + +&sram0 { + reg = <0x20000000 DT_SIZE_K(32)>; +}; diff --git a/dts/arm/silabs/xg22/efr32bg22c224f512gm32.dtsi b/dts/arm/silabs/xg22/efr32bg22c224f512gm32.dtsi new file mode 100644 index 0000000000000..4fb1f84fd8815 --- /dev/null +++ b/dts/arm/silabs/xg22/efr32bg22c224f512gm32.dtsi @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2021 Sateesh Kotapati + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + soc { + compatible = "silabs,efr32bg22c224f512gm32", "silabs,efr32bg22", "silabs,xg22", + "silabs,efr32", "simple-bus"; + model = "Silicon Labs EFR32BG22C224F512GM32 SoC"; + }; +}; + +&flash0 { + reg = <0x0 DT_SIZE_K(512)>; +}; + +&sram0 { + reg = <0x20000000 DT_SIZE_K(32)>; +}; diff --git a/dts/arm/silabs/xg22/efr32bg22c224f512gm40.dtsi b/dts/arm/silabs/xg22/efr32bg22c224f512gm40.dtsi new file mode 100644 index 0000000000000..ada3830bc0582 --- /dev/null +++ b/dts/arm/silabs/xg22/efr32bg22c224f512gm40.dtsi @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2021 Sateesh Kotapati + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + soc { + compatible = "silabs,efr32bg22c224f512gm40", "silabs,efr32bg22", "silabs,xg22", + "silabs,efr32", "simple-bus"; + model = "Silicon Labs EFR32BG22C224F512GM40 SoC"; + }; +}; + +&flash0 { + reg = <0x0 DT_SIZE_K(512)>; +}; + +&sram0 { + reg = <0x20000000 DT_SIZE_K(32)>; +}; diff --git a/dts/arm/silabs/xg22/efr32bg22c224f512gn32.dtsi b/dts/arm/silabs/xg22/efr32bg22c224f512gn32.dtsi new file mode 100644 index 0000000000000..a891e72da879d --- /dev/null +++ b/dts/arm/silabs/xg22/efr32bg22c224f512gn32.dtsi @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2021 Sateesh Kotapati + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + soc { + compatible = "silabs,efr32bg22c224f512gn32", "silabs,efr32bg22", "silabs,xg22", + "silabs,efr32", "simple-bus"; + model = "Silicon Labs EFR32BG22C224F512GN32 SoC"; + }; +}; + +&flash0 { + reg = <0x0 DT_SIZE_K(512)>; +}; + +&sram0 { + reg = <0x20000000 DT_SIZE_K(32)>; +}; diff --git a/dts/arm/silabs/xg22/efr32bg22c224f512im32.dtsi b/dts/arm/silabs/xg22/efr32bg22c224f512im32.dtsi new file mode 100644 index 0000000000000..24c6264857794 --- /dev/null +++ b/dts/arm/silabs/xg22/efr32bg22c224f512im32.dtsi @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2021 Sateesh Kotapati + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + soc { + compatible = "silabs,efr32bg22c224f512im32", "silabs,efr32bg22", "silabs,xg22", + "silabs,efr32", "simple-bus"; + model = "Silicon Labs EFR32BG22C224F512IM32 SoC"; + }; +}; + +&flash0 { + reg = <0x0 DT_SIZE_K(512)>; +}; + +&sram0 { + reg = <0x20000000 DT_SIZE_K(32)>; +}; diff --git a/soc/silabs/silabs_s2/xg22/Kconfig.soc b/soc/silabs/silabs_s2/xg22/Kconfig.soc index 746967536d236..f33ef2ac2d56c 100644 --- a/soc/silabs/silabs_s2/xg22/Kconfig.soc +++ b/soc/silabs/silabs_s2/xg22/Kconfig.soc @@ -25,6 +25,34 @@ config SOC_PART_NUMBER_EFR32BG22C224F512IM40 bool select SOC_SERIES_EFR32BG22 +config SOC_PART_NUMBER_EFR32BG22C224F512IM32 + bool + select SOC_SERIES_EFR32BG22 + +config SOC_PART_NUMBER_EFR32BG22C224F512GN32 + bool + select SOC_SERIES_EFR32BG22 + +config SOC_PART_NUMBER_EFR32BG22C224F512GM40 + bool + select SOC_SERIES_EFR32BG22 + +config SOC_PART_NUMBER_EFR32BG22C224F512GM32 + bool + select SOC_SERIES_EFR32BG22 + +config SOC_PART_NUMBER_EFR32BG22C222F352GN32 + bool + select SOC_SERIES_EFR32BG22 + +config SOC_PART_NUMBER_EFR32BG22C222F352GM40 + bool + select SOC_SERIES_EFR32BG22 + +config SOC_PART_NUMBER_EFR32BG22C222F352GM32 + bool + select SOC_SERIES_EFR32BG22 + config SOC_PART_NUMBER_EFR32MG22C224F512IM40 bool select SOC_SERIES_EFR32MG22 @@ -51,6 +79,13 @@ config SOC_SERIES config SOC default "efr32bg22c224f512im40" if SOC_PART_NUMBER_EFR32BG22C224F512IM40 + default "efr32bg22c224f512im32" if SOC_PART_NUMBER_EFR32BG22C224F512IM32 + default "efr32bg22c224f512gn32" if SOC_PART_NUMBER_EFR32BG22C224F512GN32 + default "efr32bg22c224f512gm40" if SOC_PART_NUMBER_EFR32BG22C224F512GM40 + default "efr32bg22c224f512gm32" if SOC_PART_NUMBER_EFR32BG22C224F512GM32 + default "efr32bg22c222f352gn32" if SOC_PART_NUMBER_EFR32BG22C222F352GN32 + default "efr32bg22c222f352gm40" if SOC_PART_NUMBER_EFR32BG22C222F352GM40 + default "efr32bg22c222f352gm32" if SOC_PART_NUMBER_EFR32BG22C222F352GM32 default "efr32mg22c224f512im40" if SOC_PART_NUMBER_EFR32MG22C224F512IM40 default "efr32mg22c224f512im32" if SOC_PART_NUMBER_EFR32MG22C224F512IM32 default "efr32mg22c224f512gn32" if SOC_PART_NUMBER_EFR32MG22C224F512GN32 @@ -59,6 +94,13 @@ config SOC config SOC_PART_NUMBER default "EFR32BG22C224F512IM40" if SOC_PART_NUMBER_EFR32BG22C224F512IM40 + default "EFR32BG22C224F512IM32" if SOC_PART_NUMBER_EFR32BG22C224F512IM32 + default "EFR32BG22C224F512GN32" if SOC_PART_NUMBER_EFR32BG22C224F512GN32 + default "EFR32BG22C224F512GM40" if SOC_PART_NUMBER_EFR32BG22C224F512GM40 + default "EFR32BG22C224F512GM32" if SOC_PART_NUMBER_EFR32BG22C224F512GM32 + default "EFR32BG22C222F352GN32" if SOC_PART_NUMBER_EFR32BG22C222F352GN32 + default "EFR32BG22C222F352GM40" if SOC_PART_NUMBER_EFR32BG22C222F352GM40 + default "EFR32BG22C222F352GM32" if SOC_PART_NUMBER_EFR32BG22C222F352GM32 default "EFR32MG22C224F512IM40" if SOC_PART_NUMBER_EFR32MG22C224F512IM40 default "EFR32MG22C224F512IM32" if SOC_PART_NUMBER_EFR32MG22C224F512IM32 default "EFR32MG22C224F512GN32" if SOC_PART_NUMBER_EFR32MG22C224F512GN32 diff --git a/soc/silabs/soc.yml b/soc/silabs/soc.yml index 042a2528fb06a..106a14d45871c 100644 --- a/soc/silabs/soc.yml +++ b/soc/silabs/soc.yml @@ -47,6 +47,13 @@ family: - name: efr32bg22 socs: - name: efr32bg22c224f512im40 + - name: efr32bg22c224f512im32 + - name: efr32bg22c224f512gn32 + - name: efr32bg22c224f512gm40 + - name: efr32bg22c224f512gm32 + - name: efr32bg22c222f352gn32 + - name: efr32bg22c222f352gm40 + - name: efr32bg22c222f352gm32 - name: efr32mg22 socs: - name: efr32mg22c224f512im40 From 7ba4db09aab8e9341d039072fca81accb1b96437 Mon Sep 17 00:00:00 2001 From: James Smith Date: Mon, 7 Jul 2025 15:44:08 -0700 Subject: [PATCH 4/4] boards: silabs: Add support for xg22_ek2710a board Adds support for the xg22_ek2710a (EFR32xG22E Explorer Kit) board. Signed-off-by: James Smith --- .../dev_kits/xg22_ek2710a/Kconfig.defconfig | 31 ++++ .../xg22_ek2710a/Kconfig.xg22_ek2710a | 5 + .../silabs/dev_kits/xg22_ek2710a/board.cmake | 8 + boards/silabs/dev_kits/xg22_ek2710a/board.yml | 6 + .../dev_kits/xg22_ek2710a/doc/index.rst | 133 +++++++++++++ .../xg22_ek2710a/xg22_ek2710a-pinctrl.dtsi | 47 +++++ .../dev_kits/xg22_ek2710a/xg22_ek2710a.dts | 174 ++++++++++++++++++ .../dev_kits/xg22_ek2710a/xg22_ek2710a.yaml | 24 +++ .../xg22_ek2710a/xg22_ek2710a_defconfig | 12 ++ 9 files changed, 440 insertions(+) create mode 100644 boards/silabs/dev_kits/xg22_ek2710a/Kconfig.defconfig create mode 100644 boards/silabs/dev_kits/xg22_ek2710a/Kconfig.xg22_ek2710a create mode 100644 boards/silabs/dev_kits/xg22_ek2710a/board.cmake create mode 100644 boards/silabs/dev_kits/xg22_ek2710a/board.yml create mode 100644 boards/silabs/dev_kits/xg22_ek2710a/doc/index.rst create mode 100644 boards/silabs/dev_kits/xg22_ek2710a/xg22_ek2710a-pinctrl.dtsi create mode 100644 boards/silabs/dev_kits/xg22_ek2710a/xg22_ek2710a.dts create mode 100644 boards/silabs/dev_kits/xg22_ek2710a/xg22_ek2710a.yaml create mode 100644 boards/silabs/dev_kits/xg22_ek2710a/xg22_ek2710a_defconfig diff --git a/boards/silabs/dev_kits/xg22_ek2710a/Kconfig.defconfig b/boards/silabs/dev_kits/xg22_ek2710a/Kconfig.defconfig new file mode 100644 index 0000000000000..8e11f9d8a8778 --- /dev/null +++ b/boards/silabs/dev_kits/xg22_ek2710a/Kconfig.defconfig @@ -0,0 +1,31 @@ +# Copyright The Zephyr Project Contributors +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_XG22_EK2710A + +config LOG_BACKEND_SWO_FREQ_HZ + default 875000 + depends on LOG_BACKEND_SWO + +if SOC_GECKO_USE_RAIL + +config FPU + default y + +endif # SOC_GECKO_USE_RAIL + +if BT + +config FPU + default y + +config COMMON_LIBC_MALLOC_ARENA_SIZE + default 8192 + +config MAIN_STACK_SIZE + default 3072 if PM + default 2304 + +endif # BT + +endif # BOARD_XG22_EK2710A diff --git a/boards/silabs/dev_kits/xg22_ek2710a/Kconfig.xg22_ek2710a b/boards/silabs/dev_kits/xg22_ek2710a/Kconfig.xg22_ek2710a new file mode 100644 index 0000000000000..91be6fa58b85c --- /dev/null +++ b/boards/silabs/dev_kits/xg22_ek2710a/Kconfig.xg22_ek2710a @@ -0,0 +1,5 @@ +# Copyright The Zephyr Project Contributors +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_XG22_EK2710A + select SOC_PART_NUMBER_EFR32MG22E224F512IM40 diff --git a/boards/silabs/dev_kits/xg22_ek2710a/board.cmake b/boards/silabs/dev_kits/xg22_ek2710a/board.cmake new file mode 100644 index 0000000000000..f62e0c1e1501d --- /dev/null +++ b/boards/silabs/dev_kits/xg22_ek2710a/board.cmake @@ -0,0 +1,8 @@ +# Copyright The Zephyr Project Contributors +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(jlink "--device=EFR32MG22C224F512IM40" "--reset-after-load") +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) + +board_runner_args(silabs_commander "--device=EFR32MG22E224F512IM40") +include(${ZEPHYR_BASE}/boards/common/silabs_commander.board.cmake) diff --git a/boards/silabs/dev_kits/xg22_ek2710a/board.yml b/boards/silabs/dev_kits/xg22_ek2710a/board.yml new file mode 100644 index 0000000000000..9d4fb22806ebe --- /dev/null +++ b/boards/silabs/dev_kits/xg22_ek2710a/board.yml @@ -0,0 +1,6 @@ +board: + name: xg22_ek2710a + full_name: EFR32xG22 Explorer Kit (xG22-EK2710A) + vendor: silabs + socs: + - name: efr32mg22e224f512im40 diff --git a/boards/silabs/dev_kits/xg22_ek2710a/doc/index.rst b/boards/silabs/dev_kits/xg22_ek2710a/doc/index.rst new file mode 100644 index 0000000000000..53d1533969bdb --- /dev/null +++ b/boards/silabs/dev_kits/xg22_ek2710a/doc/index.rst @@ -0,0 +1,133 @@ +.. zephyr:board:: xg22_ek2710a + +Overview +******** + +The EFR32xG22E Explorer Kit (xG22-EK2710A) contains +a Wireless System-On-Chip from the EFR32MG22 family built on an +ARM Cortex®-M33 processor with excellent low power capabilities. + +Hardware +******** + +- EFR32MG22E224F512IM40 Mighty Gecko SoC +- CPU core: ARM Cortex®-M33 with FPU +- Flash memory: 512 kB +- RAM: 32 kB +- Transmit power: up to +6 dBm +- Operation frequency: 2.4 GHz +- Crystal for HFXO (38.4 MHz) + +For more information about the EFR32MG22 SoC and BRD2710A board, refer to these +documents: + +- `EFR32MG22 Website`_ +- `EFR32MG22E Datasheet`_ +- `EFR32xG22 Reference Manual`_ +- `BRD2710A User Guide`_ + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +Connections and IOs +=================== + +In the following table, the column **Name** contains Pin names. For example, PA2 +means Pin number 2 on PORTA, as used in the board's datasheets and manuals. + ++-------+-------------+-------------------------------------+ +| Name | Function | Usage | ++=======+=============+=====================================+ +| PA4 | GPIO | LED0 | ++-------+-------------+-------------------------------------+ +| PC7 | GPIO | Push Button 0 | ++-------+-------------+-------------------------------------+ +| PA5 | USART1_TX | UART Console VCOM_TX US0_TX | ++-------+-------------+-------------------------------------+ +| PA6 | USART1_RX | UART Console VCOM_RX US0_RX | ++-------+-------------+-------------------------------------+ + +The default configuration can be found in +:zephyr_file:`boards/silabs/dev_kits/xg22_ek2710a/xg22_ek2710a_defconfig` + +System Clock +============ + +The EFR32MG22E SoC is configured to use the 38.4 MHz external oscillator on the +board, and can operate a clock speeds of up to 76.8 MHz. + +Serial Port +=========== + +The EFR32MG22E SoC has two USARTs and one EUART. +USART1 is connected to the board controller and is used for the console. + +Programming and Debugging +************************* + +.. zephyr:board-supported-runners:: + +.. note:: + Before using the kit the first time, you should update the J-Link firmware + in Simplicity Studio. + +Flashing +======== + +The sample application :zephyr:code-sample:`hello_world` is used for this example. +Build the Zephyr kernel and application: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: xg22_ek2710a + :goals: build + +Connect the xg22_ek2710a to your host computer using the USB port and you +should see a USB connection. + +Open a serial terminal (minicom, putty, etc.) with the following settings: + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Reset the board and you'll see the following message on the corresponding serial port +terminal session: + +.. code-block:: console + + Hello World! xg22_ek2710a/efr32mg22e224f512im40 + +Bluetooth +========= + +To use the BLE function, run the command below to retrieve necessary binary +blobs from the SiLabs HAL repository. + +.. code-block:: console + + west blobs fetch hal_silabs + +Then build the Zephyr kernel and a Bluetooth sample with the following +command. The :zephyr:code-sample:`bluetooth_observer` sample application is used in +this example. + +.. zephyr-app-commands:: + :zephyr-app: samples/bluetooth/observer + :board: xg22_ek2710a + :goals: build + +.. _EFR32MG22 Website: + https://www.silabs.com/wireless/zigbee/efr32mg22-series-2-socs# + +.. _EFR32MG22E Datasheet: + https://www.silabs.com/documents/public/data-sheets/efr32mg22e-datasheet.pdf + +.. _EFR32xG22 Reference Manual: + https://www.silabs.com/documents/public/reference-manuals/efr32xg22-rm.pdf + +.. _BRD2710A User Guide: + https://www.silabs.com/documents/public/user-guides/ug582-brd2710a-user-guide.pdf diff --git a/boards/silabs/dev_kits/xg22_ek2710a/xg22_ek2710a-pinctrl.dtsi b/boards/silabs/dev_kits/xg22_ek2710a/xg22_ek2710a-pinctrl.dtsi new file mode 100644 index 0000000000000..25f6b1e5b2eb0 --- /dev/null +++ b/boards/silabs/dev_kits/xg22_ek2710a/xg22_ek2710a-pinctrl.dtsi @@ -0,0 +1,47 @@ +/* + * Copyright The Zephyr Project Contributors + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&pinctrl { + itm_default: itm_default { + group0 { + pins = ; + drive-push-pull; + output-high; + }; + }; + + i2c0_default: i2c0_default { + group0 { + pins = , ; + bias-pull-up; + drive-open-drain; + }; + }; + + pti_default: pti_default { + group0 { + pins = , ; + drive-push-pull; + output-high; + }; + }; + + usart1_default: usart1_default { + group0 { + pins = ; + drive-push-pull; + output-high; + }; + + group1 { + pins = ; + input-enable; + silabs,input-filter; + }; + }; +}; diff --git a/boards/silabs/dev_kits/xg22_ek2710a/xg22_ek2710a.dts b/boards/silabs/dev_kits/xg22_ek2710a/xg22_ek2710a.dts new file mode 100644 index 0000000000000..eb57ae67be0dd --- /dev/null +++ b/boards/silabs/dev_kits/xg22_ek2710a/xg22_ek2710a.dts @@ -0,0 +1,174 @@ +/* + * Copyright The Zephyr Project Contributors + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include +#include +#include "xg22_ek2710a-pinctrl.dtsi" + +/ { + model = "Silicon Labs BRD2710A (xG22 Explorer Kit)"; + compatible = "silabs,xg22_ek2710a", "silabs,efr32mg22"; + + chosen { + zephyr,bt-hci = &bt_hci_silabs; + zephyr,code-partition = &slot0_partition; + zephyr,console = &usart1; + zephyr,flash = &flash0; + zephyr,shell-uart = &usart1; + zephyr,sram = &sram0; + zephyr,uart-pipe = &usart1; + }; + + aliases { + led0 = &led0; + sw0 = &button0; + watchdog0 = &wdog0; + + /* If enabled, MCUboot uses this for recovery mode entrance */ + mcuboot-led0 = &led0; + mcuboot-button0 = &button0; + }; + + leds { + compatible = "gpio-leds"; + + led0: led_0 { + gpios = <&gpioa 4 GPIO_ACTIVE_HIGH>; + }; + }; + + buttons { + compatible = "gpio-keys"; + + button0: button_0 { + gpios = <&gpioc 7 GPIO_ACTIVE_LOW>; + zephyr,code = ; + }; + }; +}; + +&cpu0 { + clock-frequency = <76800000>; +}; + +&itm { + pinctrl-0 = <&itm_default>; + pinctrl-names = "default"; + swo-ref-frequency = ; +}; + +&hfxo { + ctune = <121>; + precision = <50>; + status = "okay"; +}; + +&hfrcodpll { + clock-frequency = ; + clocks = <&hfxo>; + dpll-autorecover; + dpll-edge = "fall"; + dpll-lock = "phase"; + dpll-m = <1919>; + dpll-n = <3839>; +}; + +&usart1 { + pinctrl-0 = <&usart1_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&i2c0 { + pinctrl-0 = <&i2c0_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&wdog0 { + status = "okay"; +}; + +&gpio { + status = "okay"; +}; + +&gpioa { + status = "okay"; +}; + +&gpiob { + status = "okay"; +}; + +&gpioc { + status = "okay"; +}; + +&gpiod { + status = "okay"; +}; + +&rtcc0 { + status = "okay"; +}; + +&adc0 { + status = "okay"; +}; + +&trng { + status = "okay"; +}; + +&dcdc { + regulator-boot-on; + regulator-initial-mode = ; + status = "okay"; +}; + +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserve 48 KiB for the bootloader */ + boot_partition: partition@0 { + reg = <0x00000000 0x0000c000>; + label = "mcuboot"; + read-only; + }; + + /* Reserve 224 KiB for the application in slot 0 */ + slot0_partition: partition@c000 { + reg = <0x0000c000 0x00038000>; + label = "image-0"; + }; + + /* Reserve 224 KiB for the application in slot 1 */ + slot1_partition: partition@44000 { + reg = <0x00044000 0x00038000>; + label = "image-1"; + }; + + /* Set 16 KiB of storage at the end of the 512 KiB of flash */ + storage_partition: partition@7c000 { + reg = <0x0007c000 0x00004000>; + label = "storage"; + }; + }; +}; + +&radio { + pa-voltage-mv = <1800>; +}; + +&bt_hci_silabs { + status = "okay"; +}; diff --git a/boards/silabs/dev_kits/xg22_ek2710a/xg22_ek2710a.yaml b/boards/silabs/dev_kits/xg22_ek2710a/xg22_ek2710a.yaml new file mode 100644 index 0000000000000..11a3ad5c8da80 --- /dev/null +++ b/boards/silabs/dev_kits/xg22_ek2710a/xg22_ek2710a.yaml @@ -0,0 +1,24 @@ +identifier: xg22_ek2710a +name: EFR32xG22 Explorer Kit (xG22-EK2710A, BRD2710A) +type: mcu +arch: arm +ram: 32 +flash: 512 +toolchain: + - zephyr + - gnuarmemb +supported: + - bluetooth + - counter + - gpio + - uart + - watchdog + - clock_control + - comparator + - i2c + - dma + - spi +testing: + ignore_tags: + - pm +vendor: silabs diff --git a/boards/silabs/dev_kits/xg22_ek2710a/xg22_ek2710a_defconfig b/boards/silabs/dev_kits/xg22_ek2710a/xg22_ek2710a_defconfig new file mode 100644 index 0000000000000..50c49da054e57 --- /dev/null +++ b/boards/silabs/dev_kits/xg22_ek2710a/xg22_ek2710a_defconfig @@ -0,0 +1,12 @@ +# Copyright The Zephyr Project Contributors +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_ARM_MPU=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_GPIO=y +CONFIG_HW_STACK_PROTECTION=y +CONFIG_REGULATOR=y +CONFIG_SOC_GECKO_EMU_DCDC=y +CONFIG_SOC_GECKO_EMU_DCDC_MODE_ON=y