From 5a0898daf554594a216ea6f4e2a75766ece76fa0 Mon Sep 17 00:00:00 2001 From: Khaoula Bidani Date: Wed, 2 Jul 2025 15:05:06 +0200 Subject: [PATCH 1/4] dts: bindings: clocks: Add clocks bindings for stm32l0 series Add hsi clock for stm32l0. Signed-off-by: Khaoula Bidani --- dts/bindings/clock/st,stm32l0-hsi-clock.yaml | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) create mode 100644 dts/bindings/clock/st,stm32l0-hsi-clock.yaml diff --git a/dts/bindings/clock/st,stm32l0-hsi-clock.yaml b/dts/bindings/clock/st,stm32l0-hsi-clock.yaml new file mode 100644 index 000000000000..e1e4230fdfec --- /dev/null +++ b/dts/bindings/clock/st,stm32l0-hsi-clock.yaml @@ -0,0 +1,18 @@ +# Copyright (c) 2025 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +description: STM32L0 HSI Clock + +compatible: "st,stm32l0-hsi-clock" + +include: [fixed-clock.yaml] + +properties: + hsi-div: + type: int + required: true + description: | + HSI clock divider. Configures the output HSI clock frequency + enum: + - 1 # hsi_clk = 16MHz + - 4 # hsi_clk = 4MHz From ba13cdbe3904def96c6a64885cc1751fbec12294 Mon Sep 17 00:00:00 2001 From: Khaoula Bidani Date: Wed, 2 Jul 2025 15:23:14 +0200 Subject: [PATCH 2/4] drivers: clock_control: add HSI_DIV on STM32L0 Enable support for HSI_DIV and its use as a clock source on STM32L0 SoCs. Signed-off-by: Khaoula Bidani --- include/zephyr/drivers/clock_control/stm32_clock_control.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/zephyr/drivers/clock_control/stm32_clock_control.h b/include/zephyr/drivers/clock_control/stm32_clock_control.h index d6e710a89ab5..a3c236a36181 100644 --- a/include/zephyr/drivers/clock_control/stm32_clock_control.h +++ b/include/zephyr/drivers/clock_control/stm32_clock_control.h @@ -485,6 +485,7 @@ #define STM32_HSI_ENABLED 1 #define STM32_HSI_FREQ DT_PROP(DT_NODELABEL(clk_hsi), clock_frequency) #elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hsi), st_stm32h7_hsi_clock, okay) \ + || DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hsi), st_stm32l0_hsi_clock, okay) \ || DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hsi), st_stm32g0_hsi_clock, okay) \ || DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hsi), st_stm32c0_hsi_clock, okay) \ || DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hsi), st_stm32n6_hsi_clock, okay) From e9b43b9fc586acdfc4ae47e1dcc4ebffb7df1f2a Mon Sep 17 00:00:00 2001 From: Khaoula Bidani Date: Wed, 2 Jul 2025 15:42:40 +0200 Subject: [PATCH 3/4] dts: arm: st: l0: update hsi clock node to use hsi divider Updated the clk_hsi node to use the "st,stm32l0-hsi-clock" compatible to use hsi divider. Signed-off-by: Khaoula Bidani --- dts/arm/st/l0/stm32l0.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/dts/arm/st/l0/stm32l0.dtsi b/dts/arm/st/l0/stm32l0.dtsi index c594d23665de..d0d82e340a81 100644 --- a/dts/arm/st/l0/stm32l0.dtsi +++ b/dts/arm/st/l0/stm32l0.dtsi @@ -56,8 +56,9 @@ clk_hsi: clk-hsi { #clock-cells = <0>; - compatible = "fixed-clock"; + compatible = "st,stm32l0-hsi-clock"; clock-frequency = ; + hsi-div = <1>; status = "disabled"; }; From 7285b1a51f3896560c802f7c23c7eaa1b7313252 Mon Sep 17 00:00:00 2001 From: Khaoula Bidani Date: Wed, 2 Jul 2025 15:54:33 +0200 Subject: [PATCH 4/4] drivers: clock_control: fix PLL input frequency Updated the PLL input frequency calculation to include division by the HSI clock divider. Enable HSI divider using LL_RCC_HSI_EnableDivider(). Signed-off-by: Khaoula Bidani --- drivers/clock_control/clock_stm32_ll_common.c | 10 ++++++++++ drivers/clock_control/clock_stm32l0_l1.c | 4 ++++ 2 files changed, 14 insertions(+) diff --git a/drivers/clock_control/clock_stm32_ll_common.c b/drivers/clock_control/clock_stm32_ll_common.c index 3097af2912fc..69c825f310e0 100644 --- a/drivers/clock_control/clock_stm32_ll_common.c +++ b/drivers/clock_control/clock_stm32_ll_common.c @@ -456,7 +456,11 @@ static int stm32_clock_control_get_subsys_rate(const struct device *clock, #endif #if defined(STM32_SRC_HSI) case STM32_SRC_HSI: +#if defined(CONFIG_SOC_SERIES_STM32L0X) + *rate = STM32_HSI_FREQ / STM32_HSI_DIVISOR; +#else *rate = STM32_HSI_FREQ; +#endif break; #endif #if defined(STM32_SRC_MSI) @@ -662,7 +666,13 @@ static void set_up_fixed_clock_sources(void) } } #if STM32_HSI_DIV_ENABLED +#if defined(CONFIG_SOC_SERIES_STM32L0X) + if (STM32_HSI_DIVISOR == 4) { + LL_RCC_HSI_EnableDivider(); + } +#else LL_RCC_SetHSIDiv(hsi_divider(STM32_HSI_DIVISOR)); +#endif #endif } diff --git a/drivers/clock_control/clock_stm32l0_l1.c b/drivers/clock_control/clock_stm32l0_l1.c index d378b1285256..dc6b3adbcf35 100644 --- a/drivers/clock_control/clock_stm32l0_l1.c +++ b/drivers/clock_control/clock_stm32l0_l1.c @@ -49,7 +49,11 @@ __unused uint32_t get_pllsrc_frequency(void) { if (IS_ENABLED(STM32_PLL_SRC_HSI)) { +#if defined(CONFIG_SOC_SERIES_STM32L0X) + return STM32_HSI_FREQ / STM32_HSI_DIVISOR; +#else return STM32_HSI_FREQ; +#endif } else if (IS_ENABLED(STM32_PLL_SRC_HSE)) { return STM32_HSE_FREQ; }