diff --git a/drivers/espi/Kconfig.it8xxx2 b/drivers/espi/Kconfig.it8xxx2 index f9a57f347385..7b91943291dc 100644 --- a/drivers/espi/Kconfig.it8xxx2 +++ b/drivers/espi/Kconfig.it8xxx2 @@ -20,6 +20,12 @@ config ESPI_PERIPHERAL_8042_KBC config ESPI_PERIPHERAL_HOST_IO default y +config ESPI_PERIPHERAL_HOST_IO_PVT + default y + +config ESPI_PERIPHERAL_HOST_IO_PVT_PORT_NUM + default 0x0068 + config ESPI_PERIPHERAL_DEBUG_PORT_80 default y diff --git a/drivers/espi/espi_it8xxx2.c b/drivers/espi/espi_it8xxx2.c index 02bf92828eeb..6ad985dd8d6a 100644 --- a/drivers/espi/espi_it8xxx2.c +++ b/drivers/espi/espi_it8xxx2.c @@ -32,6 +32,7 @@ LOG_MODULE_REGISTER(espi, CONFIG_ESPI_LOG_LEVEL); #define IT8XXX2_PORT_80_IRQ DT_INST_IRQ_BY_IDX(0, 5, irq) #define IT8XXX2_PMC2_IBF_IRQ DT_INST_IRQ_BY_IDX(0, 6, irq) #define IT8XXX2_TRANS_IRQ DT_INST_IRQ_BY_IDX(0, 7, irq) +#define IT8XXX2_PMC3_IBF_IRQ DT_INST_IRQ_BY_IDX(0, 8, irq) /* General Capabilities and Configuration 1 */ #define IT8XXX2_ESPI_MAX_FREQ_MASK GENMASK(2, 0) @@ -306,8 +307,20 @@ struct pmc_regs { volatile uint8_t MBXCTRL; /* 0x1a-0x1f: Reserved2 */ volatile uint8_t reserved2[6]; - /* 0x20-0xff: Reserved3 */ - volatile uint8_t reserved3[0xe0]; + /* 0x20: Host Interface PM Channel 3 Status */ + volatile uint8_t PM3STS; + /* 0x21: Host Interface PM Channel 3 Data Out Port */ + volatile uint8_t PM3DO; + /* 0x22: Host Interface PM Channel 3 Data In Port */ + volatile uint8_t PM3DI; + /* 0x23: Host Interface PM Channel 3 Control */ + volatile uint8_t PM3CTL; + /* 0x24: Host Interface PM Channel 3 Interrupt Control */ + volatile uint8_t PM3IC; + /* 0x25: Host Interface PM Channel 3 Interrupt Enable */ + volatile uint8_t PM3IE; + /* 0x26-0xff: Reserved3 */ + volatile uint8_t reserved3[0xda]; }; /* Input Buffer Full Interrupt Enable */ @@ -325,6 +338,8 @@ struct pmc_regs { #define PMC_PM2CTL_IBFIE BIT(0) /* General Purpose Flag */ #define PMC_PM2STS_GPF BIT(2) +/* PMC3 Input Buffer Full Interrupt Enable */ +#define PMC_PM3CTL_IBFIE BIT(0) /* * Dedicated Interrupt @@ -614,6 +629,12 @@ IT8XXX2_ESPI_REG_OFFSET_CHECK(pmc_regs, PM2DO, 0x11); IT8XXX2_ESPI_REG_OFFSET_CHECK(pmc_regs, PM2DI, 0x14); IT8XXX2_ESPI_REG_OFFSET_CHECK(pmc_regs, PM2CTL, 0x16); IT8XXX2_ESPI_REG_OFFSET_CHECK(pmc_regs, MBXCTRL, 0x19); +IT8XXX2_ESPI_REG_OFFSET_CHECK(pmc_regs, PM3STS, 0x20); +IT8XXX2_ESPI_REG_OFFSET_CHECK(pmc_regs, PM3DO, 0x21); +IT8XXX2_ESPI_REG_OFFSET_CHECK(pmc_regs, PM3DI, 0x22); +IT8XXX2_ESPI_REG_OFFSET_CHECK(pmc_regs, PM3CTL, 0x23); +IT8XXX2_ESPI_REG_OFFSET_CHECK(pmc_regs, PM3IC, 0x24); +IT8XXX2_ESPI_REG_OFFSET_CHECK(pmc_regs, PM3IE, 0x25); /* eSPI slave register structure check */ IT8XXX2_ESPI_REG_SIZE_CHECK(espi_slave_regs, 0xd8); @@ -746,6 +767,29 @@ static const struct ec2i_t pmc1_settings[] = { {HOST_INDEX_LDA, 0x01}, }; +#ifdef CONFIG_ESPI_PERIPHERAL_HOST_IO_PVT +#define IT8XXX2_ESPI_HOST_IO_PVT_DATA_PORT_MSB \ + ((CONFIG_ESPI_PERIPHERAL_HOST_IO_PVT_PORT_NUM >> 8) & 0xff) +#define IT8XXX2_ESPI_HOST_IO_PVT_DATA_PORT_LSB (CONFIG_ESPI_PERIPHERAL_HOST_IO_PVT_PORT_NUM & 0xff) +#define IT8XXX2_ESPI_HOST_IO_PVT_CMD_PORT_MSB \ + (((CONFIG_ESPI_PERIPHERAL_HOST_IO_PVT_PORT_NUM + 4) >> 8) & 0xff) +#define IT8XXX2_ESPI_HOST_IO_PVT_CMD_PORT_LSB \ + ((CONFIG_ESPI_PERIPHERAL_HOST_IO_PVT_PORT_NUM + 4) & 0xff) +static const struct ec2i_t pmc3_settings[] = { + /* Select logical device 17h(PMC3) */ + {HOST_INDEX_LDN, LDN_PMC3}, + /* I/O Port Base Address (data/command ports) */ + {HOST_INDEX_IOBAD0_MSB, IT8XXX2_ESPI_HOST_IO_PVT_DATA_PORT_MSB}, + {HOST_INDEX_IOBAD0_LSB, IT8XXX2_ESPI_HOST_IO_PVT_DATA_PORT_LSB}, + {HOST_INDEX_IOBAD1_MSB, IT8XXX2_ESPI_HOST_IO_PVT_CMD_PORT_MSB}, + {HOST_INDEX_IOBAD1_LSB, IT8XXX2_ESPI_HOST_IO_PVT_CMD_PORT_LSB}, + /* Set IRQ=00h for logical device */ + {HOST_INDEX_IRQNUMX, 0x00}, + /* Enable logical device */ + {HOST_INDEX_LDA, 0x01}, +}; +#endif + #ifdef CONFIG_ESPI_PERIPHERAL_EC_HOST_CMD #define IT8XXX2_ESPI_HC_DATA_PORT_MSB \ ((CONFIG_ESPI_PERIPHERAL_HOST_CMD_DATA_PORT_NUM >> 8) & 0xff) @@ -953,6 +997,9 @@ static void pnpcfg_it8xxx2_init(const struct device *dev) #ifdef CONFIG_ESPI_PERIPHERAL_EC_HOST_CMD PNPCFG(pmc2); #endif +#ifdef CONFIG_ESPI_PERIPHERAL_HOST_IO_PVT + PNPCFG(pmc3); +#endif #if defined(CONFIG_ESPI_PERIPHERAL_EC_HOST_CMD) || \ defined(CONFIG_ESPI_PERIPHERAL_ACPI_SHM_REGION) PNPCFG(smfi); @@ -1171,6 +1218,33 @@ static void pmc2_it8xxx2_init(const struct device *dev) } #endif +#ifdef CONFIG_ESPI_PERIPHERAL_HOST_IO_PVT +/* PMC3 (Host private port) */ +static void pmc3_it8xxx2_ibf_isr(const struct device *dev) +{ + const struct espi_it8xxx2_config *const config = dev->config; + struct espi_it8xxx2_data *const data = dev->data; + struct pmc_regs *const pmc_reg = (struct pmc_regs *)config->base_pmc; + struct espi_event evt = {.evt_type = ESPI_BUS_PERIPHERAL_NOTIFICATION, + .evt_details = ESPI_PERIPHERAL_HOST_IO_PVT, + .evt_data = ESPI_PERIPHERAL_NODATA}; + + evt.evt_data = pmc_reg->PM3DI; + espi_send_callbacks(&data->callbacks, dev, evt); +} + +static void pmc3_it8xxx2_init(const struct device *dev) +{ + const struct espi_it8xxx2_config *const config = dev->config; + struct pmc_regs *const pmc_reg = (struct pmc_regs *)config->base_pmc; + + /* Enable pmc3 input buffer full interrupt */ + pmc_reg->PM3CTL |= PMC_PM3CTL_IBFIE; + IRQ_CONNECT(IT8XXX2_PMC3_IBF_IRQ, 0, pmc3_it8xxx2_ibf_isr, DEVICE_DT_INST_GET(0), 0); + irq_enable(IT8XXX2_PMC3_IBF_IRQ); +} +#endif + /* eSPI api functions */ #define VW_CHAN(signal, index, level, valid) \ [signal] = {.vw_index = index, .level_mask = level, .valid_mask = valid} @@ -2518,6 +2592,10 @@ static int espi_it8xxx2_init(const struct device *dev) /* enable pmc2 for host command port */ pmc2_it8xxx2_init(dev); #endif +#ifdef CONFIG_ESPI_PERIPHERAL_HOST_IO_PVT + /* enable pmc3 for host private port */ + pmc3_it8xxx2_init(dev); +#endif /* Reset vwidx_cached_flag[] at initialization */ espi_it8xxx2_reset_vwidx_cache(dev); diff --git a/dts/riscv/ite/it51xxx.dtsi b/dts/riscv/ite/it51xxx.dtsi index d28319f68960..9b19d069962b 100644 --- a/dts/riscv/ite/it51xxx.dtsi +++ b/dts/riscv/ite/it51xxx.dtsi @@ -1237,7 +1237,8 @@ IT51XXX_IRQ_PMC1_IBF IRQ_TYPE_LEVEL_HIGH IT51XXX_IRQ_PCH_P80 IRQ_TYPE_LEVEL_HIGH IT51XXX_IRQ_PMC2_IBF IRQ_TYPE_LEVEL_HIGH - IT51XXX_IRQ_WKINTD IRQ_TYPE_LEVEL_HIGH>; + IT51XXX_IRQ_WKINTD IRQ_TYPE_LEVEL_HIGH + IT51XXX_IRQ_PMC3_IBF IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&intc>; wucctrl = <&wuc_wu42>; #address-cells = <1>; diff --git a/dts/riscv/ite/it8xxx2.dtsi b/dts/riscv/ite/it8xxx2.dtsi index 05610ce98435..586a143e619d 100644 --- a/dts/riscv/ite/it8xxx2.dtsi +++ b/dts/riscv/ite/it8xxx2.dtsi @@ -441,7 +441,8 @@ IT8XXX2_IRQ_PMC1_IBF IRQ_TYPE_LEVEL_HIGH IT8XXX2_IRQ_PCH_P80 IRQ_TYPE_LEVEL_HIGH IT8XXX2_IRQ_PMC2_IBF IRQ_TYPE_LEVEL_HIGH - IT8XXX2_IRQ_WKINTD IRQ_TYPE_LEVEL_HIGH>; + IT8XXX2_IRQ_WKINTD IRQ_TYPE_LEVEL_HIGH + IT8XXX2_IRQ_PMC3_IBF IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&intc>; wucctrl = <&wuc_wu42>; #address-cells = <1>; diff --git a/include/zephyr/dt-bindings/interrupt-controller/ite-intc.h b/include/zephyr/dt-bindings/interrupt-controller/ite-intc.h index 83ad4e5f805f..2ee832825306 100644 --- a/include/zephyr/dt-bindings/interrupt-controller/ite-intc.h +++ b/include/zephyr/dt-bindings/interrupt-controller/ite-intc.h @@ -57,6 +57,8 @@ #define IT8XXX2_IRQ_WU67 55 /* Group 7 */ #define IT8XXX2_IRQ_TIMER2 58 +/* Group 8 */ +#define IT8XXX2_IRQ_PMC3_IBF 67 /* Group 9 */ #define IT8XXX2_IRQ_WU70 72 #define IT8XXX2_IRQ_WU71 73 diff --git a/include/zephyr/dt-bindings/interrupt-controller/ite-it51xxx-intc.h b/include/zephyr/dt-bindings/interrupt-controller/ite-it51xxx-intc.h index 1176c1b9db97..74c4c0e85eb5 100644 --- a/include/zephyr/dt-bindings/interrupt-controller/ite-it51xxx-intc.h +++ b/include/zephyr/dt-bindings/interrupt-controller/ite-it51xxx-intc.h @@ -59,6 +59,8 @@ #define IT51XXX_IRQ_WU67 55 /* Group 7 */ #define IT51XXX_IRQ_TIMER2 58 +/* Group 8 */ +#define IT51XXX_IRQ_PMC3_IBF 67 /* Group 9 */ #define IT51XXX_IRQ_WU70 72 #define IT51XXX_IRQ_WU71 73