From 32b995252f29d646054793396989315048b09f8f Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Fri, 13 Jun 2025 17:13:18 +0200 Subject: [PATCH 1/5] soc: Add SOC_COMPATIBLE_NRF54LM20* options In preparation for simulated nRF54LM20 targets, let's add kconfig options aking to the ones we have for the nRF54L15 devices. Signed-off-by: Alberto Escolar Piedras --- soc/Kconfig | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/soc/Kconfig b/soc/Kconfig index a1ea1f97896b..cf1bde8aa4d4 100644 --- a/soc/Kconfig +++ b/soc/Kconfig @@ -49,6 +49,12 @@ config SOC_COMPATIBLE_NRF54L15 config SOC_COMPATIBLE_NRF54L15_CPUAPP bool +config SOC_COMPATIBLE_NRF54LM20A + bool + +config SOC_COMPATIBLE_NRF54LM20A_CPUAPP + bool + config SOC_DEPRECATED_RELEASE string help From 233206e79245221a11fea1dbf019c0ea952494a7 Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Fri, 13 Jun 2025 17:15:46 +0200 Subject: [PATCH 2/5] boards nrf_bsim: Add a new nrf54lm20bsim target Add a new simulated nrf54lm20 cpuapp target Signed-off-by: Alberto Escolar Piedras --- boards/native/nrf_bsim/Kconfig | 10 ++ boards/native/nrf_bsim/Kconfig.nrf54lm20bsim | 5 + boards/native/nrf_bsim/board.yml | 5 + boards/native/nrf_bsim/board_soc.h | 2 +- .../nrf54lm20bsim_nrf54lm20a_cpuapp.dts | 144 ++++++++++++++++++ .../nrf54lm20bsim_nrf54lm20a_cpuapp.yaml | 17 +++ .../nrf54lm20bsim_nrf54lm20a_cpuapp_defconfig | 8 + modules/hal_nordic/nrfx/CMakeLists.txt | 2 + 8 files changed, 192 insertions(+), 1 deletion(-) create mode 100644 boards/native/nrf_bsim/Kconfig.nrf54lm20bsim create mode 100644 boards/native/nrf_bsim/nrf54lm20bsim_nrf54lm20a_cpuapp.dts create mode 100644 boards/native/nrf_bsim/nrf54lm20bsim_nrf54lm20a_cpuapp.yaml create mode 100644 boards/native/nrf_bsim/nrf54lm20bsim_nrf54lm20a_cpuapp_defconfig diff --git a/boards/native/nrf_bsim/Kconfig b/boards/native/nrf_bsim/Kconfig index a8865941d741..3596ccec0240 100644 --- a/boards/native/nrf_bsim/Kconfig +++ b/boards/native/nrf_bsim/Kconfig @@ -45,6 +45,16 @@ config BOARD_NRF54L15BSIM_NRF54L15_CPUAPP Will produce a console Linux process which can be executed natively. It needs the BabbleSim simulator both in compile time and to execute +config BOARD_NRF54LM20BSIM_NRF54LM20A_CPUAPP + bool + select SOC_SERIES_BSIM_NRF54LX + select SOC_COMPATIBLE_NRF54LM20A + select SOC_COMPATIBLE_NRF54LM20A_CPUAPP + select CLOCK_CONTROL + help + Simulated NRF54LM20 Application core + Will produce a console Linux process which can be executed natively. + It needs the BabbleSim simulator both in compile time and to execute if SOC_SERIES_BSIM_NRFXX diff --git a/boards/native/nrf_bsim/Kconfig.nrf54lm20bsim b/boards/native/nrf_bsim/Kconfig.nrf54lm20bsim new file mode 100644 index 000000000000..f5d8f6400971 --- /dev/null +++ b/boards/native/nrf_bsim/Kconfig.nrf54lm20bsim @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NRF54LM20BSIM + select SOC_POSIX diff --git a/boards/native/nrf_bsim/board.yml b/boards/native/nrf_bsim/board.yml index 0ba40b336773..0a94a177d500 100644 --- a/boards/native/nrf_bsim/board.yml +++ b/boards/native/nrf_bsim/board.yml @@ -14,5 +14,10 @@ boards: vendor: zephyr socs: - name: nrf54l15 +- name: nrf54lm20bsim + full_name: nRF54LM20 simulated boards (BabbleSim) + vendor: zephyr + socs: + - name: nrf54lm20a # Note the 53 and 54 are referring to the real SOC yamls, but we only use their name and cpu-cluster # definitions. In practice these board uses the same native SOC (SOC_POSIX) as the nrf52_bsim diff --git a/boards/native/nrf_bsim/board_soc.h b/boards/native/nrf_bsim/board_soc.h index e0b1cb60a594..ee77478caabb 100644 --- a/boards/native/nrf_bsim/board_soc.h +++ b/boards/native/nrf_bsim/board_soc.h @@ -38,7 +38,7 @@ #define OFFLOAD_SW_IRQ EGU0_IRQn #elif defined(CONFIG_BOARD_NRF5340BSIM_NRF5340_CPUNET) #define OFFLOAD_SW_IRQ SWI0_IRQn -#elif defined(CONFIG_BOARD_NRF54L15BSIM) +#elif defined(CONFIG_SOC_SERIES_BSIM_NRF54LX) #define OFFLOAD_SW_IRQ SWI00_IRQn #endif diff --git a/boards/native/nrf_bsim/nrf54lm20bsim_nrf54lm20a_cpuapp.dts b/boards/native/nrf_bsim/nrf54lm20bsim_nrf54lm20a_cpuapp.dts new file mode 100644 index 000000000000..bd424f2e15ec --- /dev/null +++ b/boards/native/nrf_bsim/nrf54lm20bsim_nrf54lm20a_cpuapp.dts @@ -0,0 +1,144 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include <../boards/nordic/nrf54lm20dk/nrf54lm20dk_nrf54lm20a-pinctrl.dtsi> + +/ { + model = "Nordic NRF54LM20 BSIM NRF54LM20A Application MCU"; + compatible = "bsim,nrf54lm20-bsim-nrf54lm20a-cpuapp", "bsim,nrf54"; + + chosen { + zephyr,console = &uart20; + zephyr,entropy = &rng; + zephyr,bt-c2h-uart = &uart20; + zephyr,flash-controller = &rram_controller; + zephyr,flash = &cpuapp_rram; + }; + + /delete-node/ cpus; + /delete-node/ sw-pwm; + + soc { + /delete-node/ memory@20000000; + /delete-node/ memory@20067c00; + + peripheral@50000000 { + /delete-node/ vpr@4c000; + /delete-node/ interrupt-controller@f0000000; + /delete-node/spi@4d000; + /delete-node/usbhs@5a000; + /delete-node/i2c@c6000; + /delete-node/spi@c6000; + /delete-node/i2c@c7000; + /delete-node/spi@c7000; + /delete-node/i2c@c8000; + /delete-node/spi@c8000; + /delete-node/pdm@d0000; + /delete-node/pdm@d1000; + /delete-node/pwm@d2000; + /delete-node/pwm@d3000; + /delete-node/pwm@d4000; + /delete-node/adc@d5000; + /delete-node/nfct@d6000; + /delete-node/qdec@e0000; + /delete-node/qdec@e1000; + /delete-node/tdm@e8000; + /delete-node/i2c@ed000; + /delete-node/spi@ed000; + /delete-node/i2c@ee000; + /delete-node/spi@ee000; + /delete-node/i2c@104000; + /delete-node/spi@104000; + /delete-node/comparator@106000; + /delete-node/watchdog@108000; + /delete-node/watchdog@109000; + /delete-node/regulator@120000; + }; + }; + + rng: rng { + status = "okay"; + compatible = "nordic,nrf-cracen-ctrdrbg"; + }; + + psa_rng: psa-rng { + status = "disabled"; + }; +}; + +&grtc { + owned-channels = <0 1 2 3 4 5 6 7 8 9 10 11>; + /* Channels 7-11 reserved for Zero Latency IRQs, 3-4 for FLPR */ + child-owned-channels = <3 4 7 8 9 10 11>; + status = "okay"; +}; + +&cpuapp_rram { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + storage_partition: partition@0 { + label = "storage"; + reg = <0x0 DT_SIZE_K(500)>; + }; + }; +}; + +&uart20 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart20_default>; + pinctrl-1 = <&uart20_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&uart30 { + current-speed = <115200>; + pinctrl-0 = <&uart30_default>; + pinctrl-1 = <&uart30_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&gpiote20 { + status = "okay"; +}; + +&gpiote30 { + status = "okay"; +}; + +&temp { + status = "okay"; +}; + +&radio { + status = "okay"; + /* These features are not yet supported by the RADIO model */ + /delete-property/ dfe-supported; + /delete-property/ cs-supported; +}; + +&clock { + status = "okay"; +}; diff --git a/boards/native/nrf_bsim/nrf54lm20bsim_nrf54lm20a_cpuapp.yaml b/boards/native/nrf_bsim/nrf54lm20bsim_nrf54lm20a_cpuapp.yaml new file mode 100644 index 000000000000..7941cd317ee5 --- /dev/null +++ b/boards/native/nrf_bsim/nrf54lm20bsim_nrf54lm20a_cpuapp.yaml @@ -0,0 +1,17 @@ +identifier: nrf54lm20bsim/nrf54lm20a/cpuapp +name: NRF54LM20 BabbleSim - Application Core target +type: native +arch: posix +simulation: + - name: native +env: + - BSIM_OUT_PATH +toolchain: + - zephyr +supported: + - counter + - gpio +testing: + ignore_tags: + - modem + - bsim_skip_CI diff --git a/boards/native/nrf_bsim/nrf54lm20bsim_nrf54lm20a_cpuapp_defconfig b/boards/native/nrf_bsim/nrf54lm20bsim_nrf54lm20a_cpuapp_defconfig new file mode 100644 index 000000000000..0fde4e01b583 --- /dev/null +++ b/boards/native/nrf_bsim/nrf54lm20bsim_nrf54lm20a_cpuapp_defconfig @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2023 Nordic Semiconductor ASA + +CONFIG_CONSOLE=y +CONFIG_NO_OPTIMIZATIONS=y + +# Start SYSCOUNTER on driver init +CONFIG_NRF_GRTC_START_SYSCOUNTER=y diff --git a/modules/hal_nordic/nrfx/CMakeLists.txt b/modules/hal_nordic/nrfx/CMakeLists.txt index 5ade40168183..547f5174026e 100644 --- a/modules/hal_nordic/nrfx/CMakeLists.txt +++ b/modules/hal_nordic/nrfx/CMakeLists.txt @@ -66,6 +66,8 @@ zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF54L20_ENGA_CPUFLPR NRF_FLPR) zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF54LM20A_ENGA NRF54LM20A_ENGA_XXAA) zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF54LM20A_ENGA_CPUAPP NRF_APPLICATION) zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF54LM20A_ENGA_CPUFLPR NRF_FLPR) +zephyr_compile_definitions_ifdef(CONFIG_SOC_COMPATIBLE_NRF54LM20A NRF54LM20A_ENGA_XXAA) +zephyr_compile_definitions_ifdef(CONFIG_SOC_COMPATIBLE_NRF54LM20A_CPUAPP NRF_APPLICATION) zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF9120 NRF9120_XXAA) zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF9160 NRF9160_XXAA) From 194cf6bc6bb5402d174c52211f7adea7ab1c792f Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Mon, 16 Jun 2025 11:29:40 +0200 Subject: [PATCH 3/5] tests drivers counter: Enable for nrf54lm20bsim_nrf54lm20_cpuapp These tests run fine in this board, let's provide an overlay and enable them. Signed-off-by: Alberto Escolar Piedras --- .../boards/nrf54lm20bsim_nrf54lm20a_cpuapp.overlay | 3 +++ 1 file changed, 3 insertions(+) create mode 100644 tests/drivers/counter/counter_basic_api/boards/nrf54lm20bsim_nrf54lm20a_cpuapp.overlay diff --git a/tests/drivers/counter/counter_basic_api/boards/nrf54lm20bsim_nrf54lm20a_cpuapp.overlay b/tests/drivers/counter/counter_basic_api/boards/nrf54lm20bsim_nrf54lm20a_cpuapp.overlay new file mode 100644 index 000000000000..03676317e382 --- /dev/null +++ b/tests/drivers/counter/counter_basic_api/boards/nrf54lm20bsim_nrf54lm20a_cpuapp.overlay @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: Apache-2.0 */ + +#include "nrf54lm20dk_nrf54lm20_common.dtsi" From 4f7515bade9bcdb905ba5413b9e83a1782594587 Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Tue, 17 Jun 2025 12:38:54 +0200 Subject: [PATCH 4/5] soc/nordic/nrf54l: Set SOC_COMPATIBLE for 54L CPUAPP targets So we can enable features for both the real and simulated targets based on these same options. Signed-off-by: Alberto Escolar Piedras --- soc/nordic/nrf54l/Kconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/soc/nordic/nrf54l/Kconfig b/soc/nordic/nrf54l/Kconfig index 1170bca99d89..86f5200ee0d6 100644 --- a/soc/nordic/nrf54l/Kconfig +++ b/soc/nordic/nrf54l/Kconfig @@ -34,12 +34,16 @@ config SOC_NRF54L10_CPUAPP config SOC_NRF54L15_CPUAPP select SOC_NRF54L_CPUAPP_COMMON + select SOC_COMPATIBLE_NRF54L15 + select SOC_COMPATIBLE_NRF54L15_CPUAPP config SOC_NRF54L20_ENGA_CPUAPP select SOC_NRF54L_CPUAPP_COMMON config SOC_NRF54LM20A_ENGA_CPUAPP select SOC_NRF54L_CPUAPP_COMMON + select SOC_COMPATIBLE_NRF54LM20A + select SOC_COMPATIBLE_NRF54LM20A_CPUAPP config SOC_NRF54L05_CPUFLPR select RISCV_CORE_NORDIC_VPR From ccac78b853a35bd2bff1cd874b962b84a5c80c2f Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Wed, 25 Jun 2025 15:00:04 +0200 Subject: [PATCH 5/5] tests/drivers/uart/: Add overlays for the nrf54lm20bsim This target can also run this tests, we just overlays including the ones for the real boards. Signed-off-by: Alberto Escolar Piedras --- .../boards/nrf54lm20bsim_nrf54lm20a_cpuapp.overlay | 3 +++ .../boards/nrf54lm20bsim_nrf54lm20a_cpuapp.overlay | 7 +++++++ tests/drivers/uart/uart_mix_fifo_poll/testcase.yaml | 1 + .../uart_pm/boards/nrf54lm20bsim_nrf54lm20a_cpuapp.overlay | 3 +++ tests/drivers/uart/uart_pm/testcase.yaml | 2 ++ 5 files changed, 16 insertions(+) create mode 100644 tests/drivers/uart/uart_async_api/boards/nrf54lm20bsim_nrf54lm20a_cpuapp.overlay create mode 100644 tests/drivers/uart/uart_mix_fifo_poll/boards/nrf54lm20bsim_nrf54lm20a_cpuapp.overlay create mode 100644 tests/drivers/uart/uart_pm/boards/nrf54lm20bsim_nrf54lm20a_cpuapp.overlay diff --git a/tests/drivers/uart/uart_async_api/boards/nrf54lm20bsim_nrf54lm20a_cpuapp.overlay b/tests/drivers/uart/uart_async_api/boards/nrf54lm20bsim_nrf54lm20a_cpuapp.overlay new file mode 100644 index 000000000000..aef400ac2b1f --- /dev/null +++ b/tests/drivers/uart/uart_async_api/boards/nrf54lm20bsim_nrf54lm20a_cpuapp.overlay @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: Apache-2.0 */ + +#include "nrf54lm20dk_nrf54lm20a_cpuapp.overlay" diff --git a/tests/drivers/uart/uart_mix_fifo_poll/boards/nrf54lm20bsim_nrf54lm20a_cpuapp.overlay b/tests/drivers/uart/uart_mix_fifo_poll/boards/nrf54lm20bsim_nrf54lm20a_cpuapp.overlay new file mode 100644 index 000000000000..8e7299a0d758 --- /dev/null +++ b/tests/drivers/uart/uart_mix_fifo_poll/boards/nrf54lm20bsim_nrf54lm20a_cpuapp.overlay @@ -0,0 +1,7 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "nrf54lm20dk_nrf54lm20a_cpuapp.overlay" diff --git a/tests/drivers/uart/uart_mix_fifo_poll/testcase.yaml b/tests/drivers/uart/uart_mix_fifo_poll/testcase.yaml index a901abda9e43..25a37526d27b 100644 --- a/tests/drivers/uart/uart_mix_fifo_poll/testcase.yaml +++ b/tests/drivers/uart/uart_mix_fifo_poll/testcase.yaml @@ -13,6 +13,7 @@ common: - nrf54l15dk/nrf54l15/cpuapp - nrf54l20pdk/nrf54l20/cpuapp - nrf54lm20dk/nrf54lm20a/cpuapp + - nrf54lm20bsim/nrf54lm20a/cpuapp - nrf54l15bsim/nrf54l15/cpuapp - nrf54h20dk/nrf54h20/cpuapp - nrf54h20dk/nrf54h20/cpurad diff --git a/tests/drivers/uart/uart_pm/boards/nrf54lm20bsim_nrf54lm20a_cpuapp.overlay b/tests/drivers/uart/uart_pm/boards/nrf54lm20bsim_nrf54lm20a_cpuapp.overlay new file mode 100644 index 000000000000..aef400ac2b1f --- /dev/null +++ b/tests/drivers/uart/uart_pm/boards/nrf54lm20bsim_nrf54lm20a_cpuapp.overlay @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: Apache-2.0 */ + +#include "nrf54lm20dk_nrf54lm20a_cpuapp.overlay" diff --git a/tests/drivers/uart/uart_pm/testcase.yaml b/tests/drivers/uart/uart_pm/testcase.yaml index 9bb360677577..cb039650136b 100644 --- a/tests/drivers/uart/uart_pm/testcase.yaml +++ b/tests/drivers/uart/uart_pm/testcase.yaml @@ -9,6 +9,7 @@ common: - nrf54l15dk/nrf54l15/cpuapp - nrf54l20pdk/nrf54l20/cpuapp - nrf54lm20dk/nrf54lm20a/cpuapp + - nrf54lm20bsim/nrf54lm20a/cpuapp - nrf54l15bsim/nrf54l15/cpuapp - nrf54h20dk/nrf54h20/cpuapp - nrf52_bsim @@ -37,6 +38,7 @@ tests: - nrf54l15dk/nrf54l15/cpuapp - nrf54l20pdk/nrf54l20/cpuapp - nrf54lm20dk/nrf54lm20a/cpuapp + - nrf54lm20bsim/nrf54lm20a/cpuapp - nrf54l15bsim/nrf54l15/cpuapp - nrf54h20dk/nrf54h20/cpuapp - nrf52_bsim