From 9f305a12184a94368b8023aca6debf0d309ec7fe Mon Sep 17 00:00:00 2001 From: Luc BEAUFILS Date: Thu, 19 Jun 2025 10:36:23 +0200 Subject: [PATCH 1/7] drivers: wdt_wwdg_stm32: freeze watchdog in debug mode for mp2x SoCs Like the H7x series, the MP2x series has a WWDG1 peripheral in the APB3 bus. The MP2 has the same LL function to freeze the watchdog in debug mode. Signed-off-by: Luc BEAUFILS --- drivers/watchdog/wdt_wwdg_stm32.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/watchdog/wdt_wwdg_stm32.c b/drivers/watchdog/wdt_wwdg_stm32.c index ccdb456fb90fe..9947d3859b331 100644 --- a/drivers/watchdog/wdt_wwdg_stm32.c +++ b/drivers/watchdog/wdt_wwdg_stm32.c @@ -173,7 +173,7 @@ static int wwdg_stm32_setup(const struct device *dev, uint8_t options) #elif defined(CONFIG_SOC_SERIES_STM32C0X) || defined(CONFIG_SOC_SERIES_STM32G0X) LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_DBGMCU); #endif -#if defined(CONFIG_SOC_SERIES_STM32H7X) +#if defined(CONFIG_SOC_SERIES_STM32H7X) || defined(CONFIG_SOC_SERIES_STM32MP2X) LL_DBGMCU_APB3_GRP1_FreezePeriph(LL_DBGMCU_APB3_GRP1_WWDG1_STOP); #elif defined(CONFIG_SOC_SERIES_STM32MP1X) LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_WWDG1_STOP); From d97c9798ae8af8be6604a3dd65f07497aa4dcd5c Mon Sep 17 00:00:00 2001 From: Luc BEAUFILS Date: Thu, 19 Jun 2025 11:00:13 +0200 Subject: [PATCH 2/7] dt-bindings: stm32mp2_clock: add wwdg1 clock Add clock binding for WWDG1 peripheral in STM32MP2 series. Signed-off-by: Luc BEAUFILS --- include/zephyr/dt-bindings/clock/stm32mp2_clock.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/include/zephyr/dt-bindings/clock/stm32mp2_clock.h b/include/zephyr/dt-bindings/clock/stm32mp2_clock.h index ba462a0f2874d..535371064c92b 100644 --- a/include/zephyr/dt-bindings/clock/stm32mp2_clock.h +++ b/include/zephyr/dt-bindings/clock/stm32mp2_clock.h @@ -50,7 +50,10 @@ #define STM32_CLOCK_PERIPH_UART8 0x798 #define STM32_CLOCK_PERIPH_UART9 0x79C +/* Watchdog Peripheral */ +#define STM32_CLOCK_PERIPH_WWDG1 0x89C + #define STM32_CLOCK_PERIPH_MIN STM32_CLOCK_PERIPH_GPIOA -#define STM32_CLOCK_PERIPH_MAX STM32_CLOCK_PERIPH_UART9 +#define STM32_CLOCK_PERIPH_MAX STM32_CLOCK_PERIPH_WWDG1 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32MP2_CLOCK_H_ */ From 55ec92c4a059d4201be32a3737940ac5d026ad6a Mon Sep 17 00:00:00 2001 From: Luc BEAUFILS Date: Thu, 19 Jun 2025 11:03:10 +0200 Subject: [PATCH 3/7] dts: arm: stm32mp2_m33: add wwdg1 node Add the wwdg1 node, which is the wwdg for non-secure world. Signed-off-by: Luc BEAUFILS --- dts/arm/st/mp2/stm32mp2_m33.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/dts/arm/st/mp2/stm32mp2_m33.dtsi b/dts/arm/st/mp2/stm32mp2_m33.dtsi index 262545ef67415..55cfa83a54633 100644 --- a/dts/arm/st/mp2/stm32mp2_m33.dtsi +++ b/dts/arm/st/mp2/stm32mp2_m33.dtsi @@ -240,6 +240,14 @@ interrupts = <150 0>; status = "disabled"; }; + + wwdg: wwdg1: watchdog@44050000 { + compatible = "st,stm32-window-watchdog"; + reg = <0x44050000 DT_SIZE_K(1)>; + clocks = <&rcc STM32_CLOCK(WWDG1, STM32_CLK)>; + interrupts = <8 0>; + status = "disabled"; + }; }; }; From 2c8a31ecd0c4e4c58f959d0a8363db7e7a64599b Mon Sep 17 00:00:00 2001 From: Luc BEAUFILS Date: Tue, 24 Jun 2025 11:15:20 +0200 Subject: [PATCH 4/7] clock_control: clock_stm32_ll_mp2: add wwdg1 clock support WWDG1 clock = ((MCU clock / LSMCU div) /APB3 prescaler) Signed-off-by: Luc BEAUFILS --- drivers/clock_control/clock_stm32_ll_mp2.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/clock_control/clock_stm32_ll_mp2.c b/drivers/clock_control/clock_stm32_ll_mp2.c index 96e4553337753..39008a613da52 100644 --- a/drivers/clock_control/clock_stm32_ll_mp2.c +++ b/drivers/clock_control/clock_stm32_ll_mp2.c @@ -72,6 +72,11 @@ static int stm32_clock_control_get_subsys_rate(const struct device *dev, case STM32_CLOCK_PERIPH_UART9: *rate = LL_RCC_GetUARTClockFreq(LL_RCC_UART9_CLKSOURCE); break; + case STM32_CLOCK_PERIPH_WWDG1: + /* The WWDG1 clock is derived from the APB3 clock */ + int wwdg1_clock = 400000000 >> LL_RCC_Get_LSMCUDIVR(); + *rate = wwdg1_clock >> LL_RCC_GetAPB3Prescaler(); + break; default: return -ENOTSUP; } From 6d01da788af752965b652c7e09727f1c8b39335c Mon Sep 17 00:00:00 2001 From: Luc BEAUFILS Date: Thu, 19 Jun 2025 11:04:45 +0200 Subject: [PATCH 5/7] drivers: wdt_iwdg_stm32.c: freeze watchdog in debug mode for mp2x SoCs The IWDG4 is on the APB3 bus on STM32MP2x SoCs. When the system is in debug mode, the watchdog should be frozen to prevent it from expiring and resetting the system during debugging sessions. Signed-off-by: Luc BEAUFILS --- drivers/watchdog/wdt_iwdg_stm32.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/watchdog/wdt_iwdg_stm32.c b/drivers/watchdog/wdt_iwdg_stm32.c index 682963b10701b..95dec9ad412c6 100644 --- a/drivers/watchdog/wdt_iwdg_stm32.c +++ b/drivers/watchdog/wdt_iwdg_stm32.c @@ -105,6 +105,8 @@ static int iwdg_stm32_setup(const struct device *dev, uint8_t options) LL_DBGMCU_APB4_GRP1_FreezePeriph(LL_DBGMCU_APB4_GRP1_IWDG1_STOP); #elif defined(CONFIG_SOC_SERIES_STM32H7RSX) LL_DBGMCU_APB4_GRP1_FreezePeriph(LL_DBGMCU_APB4_GRP1_IWDG_STOP); +#elif defined(CONFIG_SOC_SERIES_STM32MP2X) + LL_DBGMCU_APB3_GRP1_FreezePeriph(LL_DBGMCU_APB3_GRP1_IWDG4_STOP); #else LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_IWDG_STOP); #endif From beaae5b029979886a6f798eba592bc25534c5f4b Mon Sep 17 00:00:00 2001 From: Luc BEAUFILS Date: Thu, 19 Jun 2025 11:09:23 +0200 Subject: [PATCH 6/7] dt-bindings: stm32mp2_clock: add iwdg4 clock Add the IWDG4 clock definition to the STM32MP2 clock bindings. Signed-off-by: Luc BEAUFILS --- include/zephyr/dt-bindings/clock/stm32mp2_clock.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/zephyr/dt-bindings/clock/stm32mp2_clock.h b/include/zephyr/dt-bindings/clock/stm32mp2_clock.h index 535371064c92b..12da24484c250 100644 --- a/include/zephyr/dt-bindings/clock/stm32mp2_clock.h +++ b/include/zephyr/dt-bindings/clock/stm32mp2_clock.h @@ -51,6 +51,7 @@ #define STM32_CLOCK_PERIPH_UART9 0x79C /* Watchdog Peripheral */ +#define STM32_CLOCK_PERIPH_IWDG4 0x894 #define STM32_CLOCK_PERIPH_WWDG1 0x89C #define STM32_CLOCK_PERIPH_MIN STM32_CLOCK_PERIPH_GPIOA From 344a37fc969ae48caed019019a5bbb222bb403ed Mon Sep 17 00:00:00 2001 From: Luc BEAUFILS Date: Thu, 19 Jun 2025 11:07:37 +0200 Subject: [PATCH 7/7] dts: arm: stm32mp2_m33.dtsi: add iwdg4 watchdog node This is the independent watchdog for the non-secure world of M33 core. Signed-off-by: Luc BEAUFILS --- dts/arm/st/mp2/stm32mp2_m33.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/dts/arm/st/mp2/stm32mp2_m33.dtsi b/dts/arm/st/mp2/stm32mp2_m33.dtsi index 55cfa83a54633..c719f74b8d59b 100644 --- a/dts/arm/st/mp2/stm32mp2_m33.dtsi +++ b/dts/arm/st/mp2/stm32mp2_m33.dtsi @@ -241,6 +241,13 @@ status = "disabled"; }; + iwdg: iwdg4: watchdog@44040000 { + compatible = "st,stm32-watchdog"; + reg = <0x44040000 DT_SIZE_K(1)>; + clocks = <&rcc STM32_CLOCK(IWDG4, STM32_CLK)>; + status = "disabled"; + }; + wwdg: wwdg1: watchdog@44050000 { compatible = "st,stm32-window-watchdog"; reg = <0x44050000 DT_SIZE_K(1)>;