diff --git a/drivers/clock_control/clock_stm32_ll_mp2.c b/drivers/clock_control/clock_stm32_ll_mp2.c
index 96e4553337753..39008a613da52 100644
--- a/drivers/clock_control/clock_stm32_ll_mp2.c
+++ b/drivers/clock_control/clock_stm32_ll_mp2.c
@@ -72,6 +72,11 @@ static int stm32_clock_control_get_subsys_rate(const struct device *dev,
 	case STM32_CLOCK_PERIPH_UART9:
 		*rate = LL_RCC_GetUARTClockFreq(LL_RCC_UART9_CLKSOURCE);
 		break;
+	case STM32_CLOCK_PERIPH_WWDG1:
+		/* The WWDG1 clock is derived from the APB3 clock */
+		int wwdg1_clock = 400000000 >> LL_RCC_Get_LSMCUDIVR();
+		*rate = wwdg1_clock >> LL_RCC_GetAPB3Prescaler();
+		break;
 	default:
 		return -ENOTSUP;
 	}
diff --git a/drivers/watchdog/wdt_iwdg_stm32.c b/drivers/watchdog/wdt_iwdg_stm32.c
index 682963b10701b..95dec9ad412c6 100644
--- a/drivers/watchdog/wdt_iwdg_stm32.c
+++ b/drivers/watchdog/wdt_iwdg_stm32.c
@@ -105,6 +105,8 @@ static int iwdg_stm32_setup(const struct device *dev, uint8_t options)
 		LL_DBGMCU_APB4_GRP1_FreezePeriph(LL_DBGMCU_APB4_GRP1_IWDG1_STOP);
 #elif defined(CONFIG_SOC_SERIES_STM32H7RSX)
 		LL_DBGMCU_APB4_GRP1_FreezePeriph(LL_DBGMCU_APB4_GRP1_IWDG_STOP);
+#elif defined(CONFIG_SOC_SERIES_STM32MP2X)
+		LL_DBGMCU_APB3_GRP1_FreezePeriph(LL_DBGMCU_APB3_GRP1_IWDG4_STOP);
 #else
 		LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_IWDG_STOP);
 #endif
diff --git a/drivers/watchdog/wdt_wwdg_stm32.c b/drivers/watchdog/wdt_wwdg_stm32.c
index ccdb456fb90fe..9947d3859b331 100644
--- a/drivers/watchdog/wdt_wwdg_stm32.c
+++ b/drivers/watchdog/wdt_wwdg_stm32.c
@@ -173,7 +173,7 @@ static int wwdg_stm32_setup(const struct device *dev, uint8_t options)
 #elif defined(CONFIG_SOC_SERIES_STM32C0X) || defined(CONFIG_SOC_SERIES_STM32G0X)
 		LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_DBGMCU);
 #endif
-#if defined(CONFIG_SOC_SERIES_STM32H7X)
+#if defined(CONFIG_SOC_SERIES_STM32H7X) || defined(CONFIG_SOC_SERIES_STM32MP2X)
 		LL_DBGMCU_APB3_GRP1_FreezePeriph(LL_DBGMCU_APB3_GRP1_WWDG1_STOP);
 #elif defined(CONFIG_SOC_SERIES_STM32MP1X)
 		LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_WWDG1_STOP);
diff --git a/dts/arm/st/mp2/stm32mp2_m33.dtsi b/dts/arm/st/mp2/stm32mp2_m33.dtsi
index 262545ef67415..c719f74b8d59b 100644
--- a/dts/arm/st/mp2/stm32mp2_m33.dtsi
+++ b/dts/arm/st/mp2/stm32mp2_m33.dtsi
@@ -240,6 +240,21 @@
 			interrupts = <150 0>;
 			status = "disabled";
 		};
+
+		iwdg: iwdg4: watchdog@44040000 {
+			compatible = "st,stm32-watchdog";
+			reg = <0x44040000 DT_SIZE_K(1)>;
+			clocks = <&rcc STM32_CLOCK(IWDG4, STM32_CLK)>;
+			status = "disabled";
+		};
+
+		wwdg: wwdg1: watchdog@44050000 {
+			compatible = "st,stm32-window-watchdog";
+			reg = <0x44050000 DT_SIZE_K(1)>;
+			clocks = <&rcc STM32_CLOCK(WWDG1, STM32_CLK)>;
+			interrupts = <8 0>;
+			status = "disabled";
+		};
 	};
 };
 
diff --git a/include/zephyr/dt-bindings/clock/stm32mp2_clock.h b/include/zephyr/dt-bindings/clock/stm32mp2_clock.h
index ba462a0f2874d..12da24484c250 100644
--- a/include/zephyr/dt-bindings/clock/stm32mp2_clock.h
+++ b/include/zephyr/dt-bindings/clock/stm32mp2_clock.h
@@ -50,7 +50,11 @@
 #define STM32_CLOCK_PERIPH_UART8	0x798
 #define STM32_CLOCK_PERIPH_UART9	0x79C
 
+/* Watchdog Peripheral */
+#define STM32_CLOCK_PERIPH_IWDG4	0x894
+#define STM32_CLOCK_PERIPH_WWDG1	0x89C
+
 #define STM32_CLOCK_PERIPH_MIN	STM32_CLOCK_PERIPH_GPIOA
-#define STM32_CLOCK_PERIPH_MAX	STM32_CLOCK_PERIPH_UART9
+#define STM32_CLOCK_PERIPH_MAX	STM32_CLOCK_PERIPH_WWDG1
 
 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32MP2_CLOCK_H_ */