From 719d539a4e6833c37fb301772350e669784a2500 Mon Sep 17 00:00:00 2001 From: Scott Worley Date: Mon, 16 Jun 2025 11:53:26 -0400 Subject: [PATCH] dts: arm: microchip: mec: Add MEC5 HAL based GIRQ information Microchip MEC SoC's include an interrupt aggregator affecting the routing of interrupt to the ARM NVIC. IA can not be treated as a true second level interrupt controller. All interrupt sources with the exception of GPIOs and eSPI virtual wires can be routed by IA to individial NVIC inputs. Each bank of GPIOs and VWires are aggregated into a single NVIC input per bank. For the NVIC to receive the interrupt signal the respective GIRQ enable must be set. We attempted to add this informatation by encoding the DT irq property. This exeperiment failed due to how Zephyr builds the interrupt tables and MEC IA is not a true second level interrupt controller. Therefore, drivers for MEC peripherals need to GIRQ number and bit position to pass to HAL API's or if a driver is implemented in the linux style without using the full MEC HAL the GIRQ information is present in DT. Signed-off-by: Scott Worley --- dts/arm/microchip/mec/mec5.dtsi | 158 +++++++++++++----- .../microchip/mec/mec5/mec5_pkg176_uarts.dtsi | 25 --- dts/arm/microchip/mec/mec5_mec1743qlj.dtsi | 29 +++- dts/arm/microchip/mec/mec5_mec1743qsz.dtsi | 15 +- dts/arm/microchip/mec/mec5_mec1753qlj.dtsi | 27 ++- dts/arm/microchip/mec/mec5_mec1753qsz.dtsi | 15 +- dts/arm/microchip/mec/mec5_mech1723nlj.dtsi | 1 + dts/arm/microchip/mec/mec5_mech1723nsz.dtsi | 1 + dts/bindings/gpio/microchip,mec5-gpio.yaml | 2 +- .../microchip,dmec-ecia-girq.yaml | 23 +++ dts/bindings/serial/microchip,mec5-uart.yaml | 2 +- dts/bindings/spi/microchip,mec5-qspi.yaml | 2 +- dts/bindings/timer/microchip,mec5-ktimer.yaml | 2 +- 13 files changed, 226 insertions(+), 76 deletions(-) delete mode 100644 dts/arm/microchip/mec/mec5/mec5_pkg176_uarts.dtsi create mode 100644 dts/bindings/interrupt-controller/microchip,dmec-ecia-girq.yaml diff --git a/dts/arm/microchip/mec/mec5.dtsi b/dts/arm/microchip/mec/mec5.dtsi index e21e470a6765..d66cd69cb383 100644 --- a/dts/arm/microchip/mec/mec5.dtsi +++ b/dts/arm/microchip/mec/mec5.dtsi @@ -33,6 +33,7 @@ reg = <0x40080100 0x100 0x4000a400 0x100>; reg-names = "pcrr", "vbatr"; interrupts = <174 0>; + girqs = <20 9>; status = "disabled"; }; ecia: ecia@4000e000 { @@ -150,6 +151,7 @@ reg = < 0x40081000 0x80 0x40081300 0x04 0x40081380 0x04 0x400813fc 0x04>; interrupts = <3 2>; + girqs = <11 255>; gpio-controller; #gpio-cells=<2>; }; @@ -158,6 +160,7 @@ reg = < 0x40081080 0x80 0x40081304 0x04 0x40081384 0x04 0x400813f8 0x4>; interrupts = <2 2>; + girqs = <10 255>; gpio-controller; #gpio-cells=<2>; }; @@ -167,6 +170,7 @@ 0x40081388 0x04 0x400813f4 0x04>; gpio-controller; interrupts = <1 2>; + girqs = <9 255>; #gpio-cells=<2>; }; gpio_140_176: gpio@40081180 { @@ -175,6 +179,7 @@ 0x4008138c 0x04 0x400813f0 0x04>; gpio-controller; interrupts = <0 2>; + girqs = <8 255>; #gpio-cells=<2>; }; gpio_200_236: gpio@40081200 { @@ -183,6 +188,7 @@ 0x40081390 0x04 0x400813ec 0x04>; gpio-controller; interrupts = <4 2>; + girqs = <12 255>; #gpio-cells=<2>; }; gpio_240_276: gpio@40081280 { @@ -191,27 +197,32 @@ 0x40081394 0x04 0x400813e8 0x04>; gpio-controller; interrupts = <17 2>; + girqs = <26 255>; #gpio-cells=<2>; }; }; uart0: uart@400f2400 { reg = <0x400f2400 0x400>; interrupts = <40 1>; + girqs = <15 0>; status = "disabled"; }; uart1: uart@400f2800 { reg = <0x400f2800 0x400>; interrupts = <41 1>; + girqs = <15 1>; status = "disabled"; }; watchdog0: watchdog@40000400 { reg = <0x40000400 0x400>; interrupts = <171 0>; + girqs = <21 2>; status = "disabled"; }; rtimer: timer@40007400 { reg = <0x40007400 0x10>; interrupts = <111 0>; + girqs = <23 10>; clock-frequency = <32768>; max-value = <0xffffffff>; status = "disabled"; @@ -219,6 +230,7 @@ timer0: timer@40000c00 { reg = <0x40000c00 0x20>; interrupts = <136 0>; + girqs = <23 0>; clock-frequency = <48000000>; prescaler = <0>; max-value = <0xffff>; @@ -227,6 +239,7 @@ timer1: timer@40000c20 { reg = <0x40000c20 0x20>; interrupts = <137 0>; + girqs = <23 1>; clock-frequency = <48000000>; prescaler = <0>; max-value = <0xffff>; @@ -235,6 +248,7 @@ timer2: timer@40000c40 { reg = <0x40000c40 0x20>; interrupts = <138 0>; + girqs = <23 2>; clock-frequency = <48000000>; prescaler = <0>; max-value = <0xffff>; @@ -243,6 +257,7 @@ timer3: timer@40000c60 { reg = <0x40000c60 0x20>; interrupts = <139 0>; + girqs = <23 3>; clock-frequency = <48000000>; prescaler = <0>; max-value = <0xffff>; @@ -251,6 +266,7 @@ timer4: timer@40000c80 { reg = <0x40000c80 0x20>; interrupts = <140 0>; + girqs = <23 4>; clock-frequency = <48000000>; prescaler = <0>; max-value = <0xffffffff>; @@ -259,6 +275,7 @@ timer5: timer@40000ca0 { reg = <0x40000ca0 0x20>; interrupts = <141 0>; + girqs = <23 5>; clock-frequency = <48000000>; prescaler = <0>; max-value = <0xffffffff>; @@ -267,49 +284,61 @@ cntr0: timer@40000d00 { reg = <0x40000d00 0x20>; interrupts = <142 0>; + girqs = <23 6>; status = "disabled"; }; cntr1: timer@40000d20 { reg = <0x40000d20 0x20>; interrupts = <143 0>; + girqs = <23 7>; status = "disabled"; }; cntr2: timer@40000d40 { reg = <0x40000d40 0x20>; interrupts = <144 0>; + girqs = <23 8>; status = "disabled"; }; cntr3: timer@40000d60 { reg = <0x40000d60 0x20>; interrupts = <145 0>; + girqs = <23 9>; status = "disabled"; }; cctmr0: timer@40001000 { reg = <0x40001000 0x40>; interrupts = <146 0>, <147 0>, <148 0>, <149 0>, - <150 0>, <151 0>, <152 0>, <153 0>, - <154 0>; + <150 0>, <151 0>, <152 0>, <153 0>, <154 0>; + interrupt-names = "counter", "cap0", "cap1", "cap2", "cap3", + "cap4", "cap5", "comp0", "comp1"; + girqs = <18 20>, <18 21>, <18 22>, <18 23>, + <18 24>, <18 25>, <18 26>, <18 27>, <18 28>; status = "disabled"; }; hibtimer0: timer@40009800 { reg = <0x40009800 0x20>; interrupts = <112 0>; + girqs = <23 16>; status = "disabled"; }; hibtimer1: timer@40009820 { reg = <0x40009820 0x20>; interrupts = <113 0>; + girqs = <23 17>; status = "disabled"; }; weektmr0: timer@4000ac80 { reg = <0x4000ac80 0x80>; - interrupts = <114 0>, <115 0>, <116 0>, - <117 0>, <118 0>; + interrupts = <114 0>, <115 0>, <116 0>, <117 0>, <118 0>; + interrupt-names = "wk_alarm", "subwk_alarm", "one_sec", "sub_sec", "syspp"; + girqs = <21 3>, <21 4>, <21 5>, <21 6>, <21 7>; status = "disabled"; }; rtc0: rtc@400f5000 { reg = <0x400f5000 0x100>; interrupts = <119 3>, <120 3>; + interrupt-names = "rtc", "rtc_alarm"; + girqs = <21 8>, <21 9>; status = "disabled"; }; bbram: bb-ram@4000a800 { @@ -319,14 +348,17 @@ }; vci0: vci@4000ae00 { reg = <0x4000ae00 0x40>; - interrupts = <121 0>, <122 0>, <123 0>, - <124 0>, <125 0>; + interrupts = <121 2>, <122 2>, <123 2>, <124 2>, <125 2>, <126 2>; + interrupt-names = "vci_ovrd_in", "vci_in0", "vci_in1", "vci_in2", + "vci_in3", "vci_in4"; + girqs = <21 10>, <21 11>, <21 12>, <21 13>, <21 14>, <21 15>; status = "disabled"; }; i2c_smb_0: i2c@40004000 { reg = <0x40004000 0x80>; clock-frequency = ; - interrupts = <20 1>; + interrupts = <20 2>; + girqs = <13 0>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -334,7 +366,8 @@ i2c_smb_1: i2c@40004400 { reg = <0x40004400 0x80>; clock-frequency = ; - interrupts = <21 1>; + interrupts = <21 2>; + girqs = <13 1>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -342,7 +375,8 @@ i2c_smb_2: i2c@40004800 { reg = <0x40004800 0x80>; clock-frequency = ; - interrupts = <22 1>; + interrupts = <22 2>; + girqs = <13 2>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -350,7 +384,8 @@ i2c_smb_3: i2c@40004c00 { reg = <0x40004C00 0x80>; clock-frequency = ; - interrupts = <23 1>; + interrupts = <23 2>; + girqs = <13 3>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -358,14 +393,16 @@ i2c_smb_4: i2c@40005000 { reg = <0x40005000 0x80>; clock-frequency = ; - interrupts = <158 1>; + interrupts = <158 2>; + girqs = <13 4>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; ps2_0: ps2@40009000 { reg = <0x40009000 0x40>; - interrupts = <100 1>; + interrupts = <100 3>; + girqs = <18 10>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -417,45 +454,55 @@ }; tach0: tach@40006000 { reg = <0x40006000 0x10>; - interrupts = <71 4>; + interrupts = <71 3>; + girqs = <17 1>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; tach1: tach@40006010 { reg = <0x40006010 0x10>; - interrupts = <72 4>; + interrupts = <72 3>; + girqs = <17 2>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; tach2: tach@40006020 { reg = <0x40006020 0x10>; - interrupts = <73 4>; + interrupts = <73 3>; + girqs = <17 3>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; tach3: tach@40006030 { reg = <0x40006030 0x10>; - interrupts = <159 4>; + interrupts = <159 3>; + girqs = <17 4>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; rpmfan0: rpmfan@4000a000 { reg = <0x4000a000 0x80>; - interrupts = <74 1>, <75 1>; + interrupts = <74 3>, <75 3>; + interrupt-names = "stall", "spin"; + girqs = <17 20>, <17 21>; status = "disabled"; }; rpmfan1: rpmfan@4000a080 { reg = <0x4000a080 0x80>; - interrupts = <76 1>, <77 1>; + interrupts = <76 3>, <77 3>; + interrupt-names = "stall", "spin"; + girqs = <17 22>, <17 23>; status = "disabled"; }; adc0: adc@40007c00 { reg = <0x40007c00 0x90>; - interrupts = <78 0>, <79 0>; + interrupts = <78 3>, <79 3>; + interrupt-names = "single", "repeat"; + girqs = <17 8>, <17 9>; interrupt-names = "single", "repeat"; status = "disabled"; #io-channel-cells = <1>; @@ -463,7 +510,8 @@ }; peci0: peci@40006400 { reg = <0x40006400 0x80>; - interrupts = <70 4>; + interrupts = <70 3>; + girqs = <17 0>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -471,53 +519,64 @@ qspi0: spi@40070000 { reg = <0x40070000 0x400>; interrupts = <91 2>; + girqs = <18 1>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; prochot0: prochot@40003400 { reg = <0x40003400 0x20>; - interrupts = <87 0>; + interrupts = <87 3>; + girqs = <17 17>; status = "disabled"; }; rcid0: rcid@40001400 { reg = <0x40001400 0x80>; - interrupts = <80 0>; + interrupts = <80 3>; + girqs = <17 10>; status = "disabled"; }; rcid1: rcid@40001480 { reg = <0x40001480 0x80>; - interrupts = <81 0>; + interrupts = <81 3>; + girqs = <17 11>; status = "disabled"; }; rcid2: rcid@40001500 { reg = <0x40001500 0x80>; - interrupts = <82 0>; + interrupts = <82 3>; + girqs = <17 12>; status = "disabled"; }; bbled0: bbled@4000b800 { reg = <0x4000b800 0x100>; - interrupts = <83 0>; + interrupts = <83 3>; + girqs = <17 13>; status = "disabled"; }; bbled1: bbled@4000b900 { reg = <0x4000b900 0x100>; - interrupts = <84 0>; + interrupts = <84 3>; + girqs = <17 14>; status = "disabled"; }; bbled2: bbled@4000ba00 { reg = <0x4000ba00 0x100>; - interrupts = <85 0>; + interrupts = <85 3>; + girqs = <17 15>; status = "disabled"; }; bbled3: bbled@4000bb00 { reg = <0x4000bb00 0x100>; - interrupts = <86 0>; + interrupts = <86 3>; + girqs = <17 16>; status = "disabled"; }; bclink0: bclink@4000cd00 { reg = <0x4000cd00 0x20>; - interrupts = <96 0>, <97 0>; + interrupts = <96 3>, <97 3>; + interrupt-names = "bcm_err", "bcm_done"; + girqs = <18 7>, <18 6>; status = "disabled"; }; tfdp0: tfdp@40008c00 { @@ -541,6 +600,8 @@ interrupt-names = "pc", "bm1", "bm2", "ltr", "oob_up", "oob_dn", "fc", "erst", "vw_chan_en", "vwct_0_6", "vwct_7_10"; + girqs = <19 0>, <19 1>, <19 2>, <19 3>, <19 4>, <19 5>, + <19 6>, <19 7>, <19 8>, <24 255>, <25 255>; status = "disabled"; /* Devices accessible to the Host via Logical Device mechanism. @@ -551,68 +612,80 @@ mbox0: mbox@400f0000 { reg = <0x400f0000 0x200>; interrupts = <60 3>; + girqs = <15 20>; status = "disabled"; }; kbc0: kbc@400f0400 { reg = <0x400f0400 0x400>, <0x400f2000 0x400>; interrupts = <59 3>, <58 3>; interrupt-names = "ibf", "obe"; + girqs = <15 19>, <15 18>; status = "disabled"; }; acpi_ec0: acpi_ec@400f0800 { reg = <0x400f0800 0x400>; interrupts = <45 3>, <46 3>; interrupt-names = "ibf", "obe"; + girqs = <15 5>, <15 6>; status = "disabled"; }; acpi_ec1: acpi_ec@400f0c00 { reg = <0x400f0c00 0x400>; interrupts = <47 3>, <48 3>; interrupt-names = "ibf", "obe"; + girqs = <15 7>, <15 8>; status = "disabled"; }; acpi_ec2: acpi_ec@400f1000 { reg = <0x400f1000 0x400>; interrupts = <49 3>, <50 3>; interrupt-names = "ibf", "obe"; + girqs = <15 9>, <15 10>; status = "disabled"; }; acpi_ec3: acpi_ec@400f1400 { reg = <0x400f1400 0x400>; interrupts = <51 3>, <52 3>; interrupt-names = "ibf", "obe"; + girqs = <15 11>, <15 12>; status = "disabled"; }; acpi_ec4: acpi_ec@400f1800 { reg = <0x400f1800 0x400>; interrupts = <53 3>, <54 3>; interrupt-names = "ibf", "obe"; + girqs = <15 13>, <15 14>; status = "disabled"; }; acpi_pm1: acpi_pm1@400f1c00 { reg = <0x400f1c00 0x400>; interrupts = <55 3>, <56 3>, <57 3>; interrupt-names = "ctl", "en", "sts"; + girqs = <15 15>, <15 16>, <15 17>; status = "disabled"; }; glue: glue_logic@400f3c00 { reg = <0x400f3c00 0x200>; interrupts = <172 1>; + girqs = <21 26>; status = "disabled"; }; emi0: emi@400f4000 { reg = <0x400f4000 0x400>; interrupts = <42 3>; + girqs = <15 2>; status = "disabled"; }; emi1: emi@400f4400 { reg = <0x400f4400 0x400>; interrupts = <43 3>; + girqs = <15 3>; status = "disabled"; }; emi2: emi@400f4800 { reg = <0x400f4800 0x400>; interrupts = <44 3>; + girqs = <15 4>; status = "disabled"; }; /* Capture Host writes to a 4-byte I/O range @@ -622,20 +695,23 @@ p80bd0: p80bd@400f8000 { reg = <0x400f8000 0x400>; interrupts = <62 0>; + girqs = <15 22>; + status = "disabled"; + }; + + /* eSPI target attached flash controller. + * When this device is fully activated via its driver, it takes + * ownership of the QSPI controller. EC access to QSPI + * registers is discarded by hardware. + */ + espi_taf0: espi_taf@40008000 { + reg = <0x40008000 0x400>, <0x40071000 0x400>; + reg-names = "tafbr", "tafcomm"; + interrupts = <166 3>, <167 3>; + interrupt-names = "done", "err"; + girqs = <19 9>, <19 10>; status = "disabled"; }; - }; - /* eSPI target attached flash controller. - * When this device is fully activated via its driver, it takes - * ownership of the QSPI controller. EC access to QSPI - * registers is discarded by hardware. - */ - espi_taf0: espi_taf@40008000 { - reg = <0x40008000 0x400>, <0x40070000 0x400>, <0x40071000 0x400>; - reg-names = "tafbr", "tafqspi", "tafcomm"; - interrupts = <166 3>, <167 3>; - interrupt-names = "done", "err"; - status = "disabled"; }; }; }; diff --git a/dts/arm/microchip/mec/mec5/mec5_pkg176_uarts.dtsi b/dts/arm/microchip/mec/mec5/mec5_pkg176_uarts.dtsi deleted file mode 100644 index b1ebea455270..000000000000 --- a/dts/arm/microchip/mec/mec5/mec5_pkg176_uarts.dtsi +++ /dev/null @@ -1,25 +0,0 @@ -/* - * Copyright (c) 2024 Microchip Technology Inc. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/* Microchip MEC5 MEC174x, MEC540x, MEC175x, and MEC550x add two more UART's - * in the 176-pin (LJ) package. - * Include this file in the soc {} section in the above chip DTSI files. - */ -uart2: uart@400f2c00 { - reg = <0x400f2c00 0x400>; - interrupts = <183 1>; - clock-frequency = <1843200>; - current-speed = <38400>; - status = "disabled"; -}; - -uart3: uart@400f3000 { - reg = <0x400f3000 0x400>; - interrupts = <184 1>; - clock-frequency = <1843200>; - current-speed = <38400>; - status = "disabled"; -}; diff --git a/dts/arm/microchip/mec/mec5_mec1743qlj.dtsi b/dts/arm/microchip/mec/mec5_mec1743qlj.dtsi index 694e95fa885e..3cc2cc8d2d56 100644 --- a/dts/arm/microchip/mec/mec5_mec1743qlj.dtsi +++ b/dts/arm/microchip/mec/mec5_mec1743qlj.dtsi @@ -23,11 +23,38 @@ #include "mec5/mec5_gpspi_v2.dtsi" #include "mec5/mec5_eeprom_8kb.dtsi" #include "mec5/mec5_pkg176_pwms.dtsi" - #include "mec5/mec5_pkg176_uarts.dtsi" + + ps2_1: ps2@40009040 { + reg = <0x40009040 0x40>; + interrupts = <101 3>; + girqs = <18 11>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; kscan0: kscan@40009c00 { reg = <0x40009c00 0x18>; interrupts = <135 0>; + girqs = <21 25>; + status = "disabled"; + }; + + uart2: uart@400f2c00 { + reg = <0x400f2c00 0x400>; + interrupts = <183 2>; + girqs = <15 25>; + clock-frequency = <1843200>; + current-speed = <115200>; + status = "disabled"; + }; + + uart3: uart@400f3000 { + reg = <0x400f3000 0x400>; + interrupts = <184 2>; + girqs = <15 26>; + clock-frequency = <1843200>; + current-speed = <115200>; status = "disabled"; }; }; diff --git a/dts/arm/microchip/mec/mec5_mec1743qsz.dtsi b/dts/arm/microchip/mec/mec5_mec1743qsz.dtsi index 5d16b727bf5c..e5b18db3e2f8 100644 --- a/dts/arm/microchip/mec/mec5_mec1743qsz.dtsi +++ b/dts/arm/microchip/mec/mec5_mec1743qsz.dtsi @@ -23,17 +23,28 @@ #include "mec5/mec5_gpspi_v2.dtsi" #include "mec5/mec5_eeprom_8kb.dtsi" + ps2_1: ps2@40009040 { + reg = <0x40009040 0x40>; + interrupts = <101 3>; + girqs = <18 11>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + kscan0: kscan@40009c00 { reg = <0x40009c00 0x18>; interrupts = <135 0>; + girqs = <21 25>; status = "disabled"; }; uart2: uart@400f2c00 { reg = <0x400f2c00 0x400>; - interrupts = <183 1>; + interrupts = <183 2>; + girqs = <15 25>; clock-frequency = <1843200>; - current-speed = <38400>; + current-speed = <115200>; status = "disabled"; }; }; diff --git a/dts/arm/microchip/mec/mec5_mec1753qlj.dtsi b/dts/arm/microchip/mec/mec5_mec1753qlj.dtsi index d7bacf673535..cd9fa15534c6 100644 --- a/dts/arm/microchip/mec/mec5_mec1753qlj.dtsi +++ b/dts/arm/microchip/mec/mec5_mec1753qlj.dtsi @@ -23,14 +23,39 @@ #include "mec5/mec5_eeprom_8kb.dtsi" #include "mec5/mec5_gpspi_v2.dtsi" #include "mec5/mec5_pkg176_pwms.dtsi" - #include "mec5/mec5_pkg176_uarts.dtsi" #include "mec5/mec5_i3c.dtsi" + ps2_1: ps2@40009040 { + reg = <0x40009040 0x40>; + interrupts = <101 3>; + girqs = <18 11>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + kscan0: kscan@40009c00 { reg = <0x40009c00 0x18>; interrupts = <135 0>; status = "disabled"; }; + uart2: uart@400f2c00 { + reg = <0x400f2c00 0x400>; + interrupts = <183 2>; + girqs = <15 25>; + clock-frequency = <1843200>; + current-speed = <115200>; + status = "disabled"; + }; + + uart3: uart@400f3000 { + reg = <0x400f3000 0x400>; + interrupts = <184 2>; + girqs = <15 26>; + clock-frequency = <1843200>; + current-speed = <115200>; + status = "disabled"; + }; }; }; diff --git a/dts/arm/microchip/mec/mec5_mec1753qsz.dtsi b/dts/arm/microchip/mec/mec5_mec1753qsz.dtsi index df3085144572..f80e73d29f64 100644 --- a/dts/arm/microchip/mec/mec5_mec1753qsz.dtsi +++ b/dts/arm/microchip/mec/mec5_mec1753qsz.dtsi @@ -24,17 +24,28 @@ #include "mec5/mec5_gpspi_v2.dtsi" #include "mec5/mec5_i3c.dtsi" + ps2_1: ps2@40009040 { + reg = <0x40009040 0x40>; + interrupts = <101 3>; + girqs = <18 11>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + kscan0: kscan@40009c00 { reg = <0x40009c00 0x18>; interrupts = <135 0>; + girqs = <21 25>; status = "disabled"; }; uart2: uart@400f2c00 { reg = <0x400f2c00 0x400>; - interrupts = <183 1>; + interrupts = <183 2>; + girqs = <15 25>; clock-frequency = <1843200>; - current-speed = <38400>; + current-speed = <115200>; status = "disabled"; }; }; diff --git a/dts/arm/microchip/mec/mec5_mech1723nlj.dtsi b/dts/arm/microchip/mec/mec5_mech1723nlj.dtsi index 82a0aa2b2e04..ef52a56ea76d 100644 --- a/dts/arm/microchip/mec/mec5_mech1723nlj.dtsi +++ b/dts/arm/microchip/mec/mec5_mech1723nlj.dtsi @@ -27,6 +27,7 @@ kscan0: kscan@40009c00 { reg = <0x40009c00 0x18>; interrupts = <135 0>; + girqs = <21 25>; status = "disabled"; }; }; diff --git a/dts/arm/microchip/mec/mec5_mech1723nsz.dtsi b/dts/arm/microchip/mec/mec5_mech1723nsz.dtsi index 02cdbab26fc6..8184582e83c1 100644 --- a/dts/arm/microchip/mec/mec5_mech1723nsz.dtsi +++ b/dts/arm/microchip/mec/mec5_mech1723nsz.dtsi @@ -26,6 +26,7 @@ kscan0: kscan@40009c00 { reg = <0x40009c00 0x18>; interrupts = <135 0>; + girqs = <21 25>; status = "disabled"; }; }; diff --git a/dts/bindings/gpio/microchip,mec5-gpio.yaml b/dts/bindings/gpio/microchip,mec5-gpio.yaml index d9ae269a5d70..da82c417e01d 100644 --- a/dts/bindings/gpio/microchip,mec5-gpio.yaml +++ b/dts/bindings/gpio/microchip,mec5-gpio.yaml @@ -5,7 +5,7 @@ description: Microchip MEC5 GPIO compatible: "microchip,mec5-gpio" -include: [gpio-controller.yaml, base.yaml] +include: ["gpio-controller.yaml", "base.yaml", "microchip,dmec-ecia-girq.yaml"] properties: reg: diff --git a/dts/bindings/interrupt-controller/microchip,dmec-ecia-girq.yaml b/dts/bindings/interrupt-controller/microchip,dmec-ecia-girq.yaml new file mode 100644 index 000000000000..6b5a028ca18b --- /dev/null +++ b/dts/bindings/interrupt-controller/microchip,dmec-ecia-girq.yaml @@ -0,0 +1,23 @@ +description: Microchip DEC/MEC series External Interrupt Aggregator GIRQ + +compatible: "microchip,dmec-ecia-girq" + +include: base.yaml + +properties: + girqs: + type: array + required: true + description: | + Many DEC/MEC periperals interrupt signals are direct capable. The signals are + connected to bits in a GIRQ. Each GIRQ is composed of 5 32-bit registers: + status(latched or r/w1-c), set-enable, clr-enable, and result (read-only). + The read-only result register bits are the bitwise AND of status and enable. + Direct mode routes the individual result register bits to NVIC inputs. If + direct mode is disable by setting direct mode bit to 0 in the EC subsystem + interrupt control register then the result register outputs are OR'd together + and the OR'd result is connected to an NVIC input based on GIRQ number. + To enable an interrupt a driver must know: + a. NVIC input number and priority from the interrupts property + b. GIRQ number and bit position from the girqs property + The number of entries in interrupts and girqs should be the same in a DT node. diff --git a/dts/bindings/serial/microchip,mec5-uart.yaml b/dts/bindings/serial/microchip,mec5-uart.yaml index d37c196d046b..701ec588db5b 100644 --- a/dts/bindings/serial/microchip,mec5-uart.yaml +++ b/dts/bindings/serial/microchip,mec5-uart.yaml @@ -5,7 +5,7 @@ description: Microchip MEC5 UART compatible: "microchip,mec5-uart" -include: [uart-controller.yaml, pinctrl-device.yaml] +include: [uart-controller.yaml, pinctrl-device.yaml, "microchip,dmec-ecia-girq.yaml"] properties: reg: diff --git a/dts/bindings/spi/microchip,mec5-qspi.yaml b/dts/bindings/spi/microchip,mec5-qspi.yaml index b7cff7fb8d9b..01adeadbfd4b 100644 --- a/dts/bindings/spi/microchip,mec5-qspi.yaml +++ b/dts/bindings/spi/microchip,mec5-qspi.yaml @@ -5,7 +5,7 @@ description: Microchip MEC5 series QSPI controller compatible: "microchip,mec5-qspi" -include: [spi-controller.yaml, pinctrl-device.yaml] +include: ["spi-controller.yaml", "pinctrl-device.yaml", "microchip,dmec-ecia-girq.yaml"] properties: reg: diff --git a/dts/bindings/timer/microchip,mec5-ktimer.yaml b/dts/bindings/timer/microchip,mec5-ktimer.yaml index d498650a09e7..06a77113fba9 100644 --- a/dts/bindings/timer/microchip,mec5-ktimer.yaml +++ b/dts/bindings/timer/microchip,mec5-ktimer.yaml @@ -7,7 +7,7 @@ description: | compatible: "microchip,mec5-ktimer" -include: base.yaml +include: ["base.yaml", "microchip,dmec-ecia-girq.yaml"] properties: reg: