diff --git a/boards/scdz/ch32v307evt/Kconfig.ch32v307evt b/boards/scdz/ch32v307evt/Kconfig.ch32v307evt new file mode 100644 index 0000000000000..dae10745271e5 --- /dev/null +++ b/boards/scdz/ch32v307evt/Kconfig.ch32v307evt @@ -0,0 +1,5 @@ +# Copyright (c) 2025 Thomas Boje +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_CH32V307EVT + select SOC_CH32V307 diff --git a/boards/scdz/ch32v307evt/board.cmake b/boards/scdz/ch32v307evt/board.cmake new file mode 100644 index 0000000000000..cdcac844a3cc4 --- /dev/null +++ b/boards/scdz/ch32v307evt/board.cmake @@ -0,0 +1,8 @@ +# Copyright (c) 2024 Michael Hope +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(minichlink "--dt-flash=y") +include(${ZEPHYR_BASE}/boards/common/minichlink.board.cmake) + +board_runner_args(openocd "--use-elf" "--cmd-reset-halt" "halt") +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/scdz/ch32v307evt/board.yml b/boards/scdz/ch32v307evt/board.yml new file mode 100644 index 0000000000000..21d2e019277a1 --- /dev/null +++ b/boards/scdz/ch32v307evt/board.yml @@ -0,0 +1,6 @@ +board: + name: ch32v307evt + full_name: SCDZ_CH32V307EVT + vendor: scdz + socs: + - name: ch32v307 diff --git a/boards/scdz/ch32v307evt/ch32v307evt-pinctrl.dtsi b/boards/scdz/ch32v307evt/ch32v307evt-pinctrl.dtsi new file mode 100644 index 0000000000000..ade4058c760e7 --- /dev/null +++ b/boards/scdz/ch32v307evt/ch32v307evt-pinctrl.dtsi @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2025 Thomas Boje + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&pinctrl { + usart1_default: usart1_default { + group1 { + pinmux = ; + output-high; + drive-push-pull; + slew-rate = "max-speed-10mhz"; + }; + + group2 { + pinmux = ; + bias-pull-up; + }; + }; +}; diff --git a/boards/scdz/ch32v307evt/ch32v307evt.dts b/boards/scdz/ch32v307evt/ch32v307evt.dts new file mode 100644 index 0000000000000..9b7e44792f022 --- /dev/null +++ b/boards/scdz/ch32v307evt/ch32v307evt.dts @@ -0,0 +1,82 @@ +/* + * Copyright (c) 2025 Thomas Boje + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include +#include "ch32v307evt-pinctrl.dtsi" + +/ { + model = "scdz_ch32v307evt"; + compatible = "scdz,ch32v307"; + + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,console = &usart1; + zephyr,shell-uart = &usart1; + }; + + leds { + compatible = "gpio-leds"; + + /* + * Please connect the unconnected LED1 on the SCDZ CH32V307EVT + * board to a suitable GPIO pin (like PD1) and then change + * this status to "okay". + */ + status = "disabled"; + + red_led: led0 { + gpios = <&gpiod 1 GPIO_ACTIVE_LOW>; + }; + }; + buttons { + compatible = "gpio-keys"; + + user_button0: sw0 { + label = "User SW0"; + gpios = <&gpioa 1 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + zephyr,code = ; + }; + }; + + aliases { + led0 = &red_led; + sw0 = &user_button0; + }; +}; + +&clk_hse { + clock-frequency = ; + status = "okay"; +}; + +&pll { + clocks = <&clk_hse>; + status = "okay"; +}; + +&rcc { + clocks = <&pll>; +}; + + +&gpioa { + status = "okay"; +}; + +&gpioc { + status = "okay"; +}; + +&usart1 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&usart1_default>; + pinctrl-names = "default"; +}; diff --git a/boards/scdz/ch32v307evt/ch32v307evt.yaml b/boards/scdz/ch32v307evt/ch32v307evt.yaml new file mode 100644 index 0000000000000..e0504172fc23f --- /dev/null +++ b/boards/scdz/ch32v307evt/ch32v307evt.yaml @@ -0,0 +1,12 @@ +identifier: scdz_ch32v307evt +name: SCDZ CH32V307 Evaluation Board +type: mcu +arch: riscv +toolchain: + - cross-compile + - zephyr +ram: 32 +flash: 256 +supported: + - gpio + - i2c diff --git a/boards/scdz/ch32v307evt/ch32v307evt_defconfig b/boards/scdz/ch32v307evt/ch32v307evt_defconfig new file mode 100644 index 0000000000000..5040cb059c9ca --- /dev/null +++ b/boards/scdz/ch32v307evt/ch32v307evt_defconfig @@ -0,0 +1,8 @@ +# Copyright (c) 2025 Thomas Boje +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_GPIO=y + +CONFIG_SERIAL=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/scdz/ch32v307evt/doc/img/ch32v003evt.webp b/boards/scdz/ch32v307evt/doc/img/ch32v003evt.webp new file mode 100644 index 0000000000000..9c1e800c7adc8 Binary files /dev/null and b/boards/scdz/ch32v307evt/doc/img/ch32v003evt.webp differ diff --git a/boards/scdz/ch32v307evt/doc/index.rst b/boards/scdz/ch32v307evt/doc/index.rst new file mode 100644 index 0000000000000..621f0ece07723 --- /dev/null +++ b/boards/scdz/ch32v307evt/doc/index.rst @@ -0,0 +1,82 @@ +.. zephyr:board:: ch32v307evt + +Overview +******** + +The `SCDZ`_ CH32V307EVT hardware provides support for QingKe V4F 32-bit RISC-V +processor. + +The `WCH webpage on CH32V307`_ contains +the processor's information and the datasheet. + +Hardware +******** + +The QingKe V4F 32-bit RISC-V processor of the SCDZ CH32V307EVT is clocked by an external +32 MHz crystal or the internal 8 MHz oscillator and runs with 127 MHz. +The CH32V307 SoC features 8 USART, 5 GPIO banks, 3 SPI, 2 I2C, 2 ADC, RTC, +2 CAN, USB Host/Device, Ethernet and 4 OPA. + +Supported Features +================== +- GPIO +- USART + +Connections and IOs +=================== + +LED +--- + +* LED1 = Unconnected. Connect to an I/O pin (PD0). +* LED2 = Unconnected. Connect to an I/O pin (PD1). + +BUTTON +------ + +* USER0 = Unconnected. Connect to an I/O pinn (PC0). + +.. zephyr:board-supported-hw:: + +Programming and Debugging +************************* + +Applications for the ``ch32v307evt`` board target can be built and flashed +in the usual way (see :ref:`build_an_application` and :ref:`application_run` +for more details); however, an external programmer (like the `WCH LinkE`_) is required since the board +does not have any built-in debug support. + +The following pins of the external programmer must be connected to the +following pins on the PCB (best way is to use a ribbon cable): + +* VCC = VCC (do not power the board from the USB port at the same time) +* GND = GND +* SWIO = PA13 + +Flashing +======== + +You can use ``minichlink`` to flash the board. Once ``minichlink`` has been set +up, build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Here is an example for the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: ch32v307evt + :goals: build flash + +Debugging +========= + +This board can be debugged via OpenOCD using the WCH openOCD liberated fork, available at https://github.com/jnk0le/openocd-wch. + +References +********** + +.. target-notes:: + +.. _WCH: http://www.wch-ic.com +.. _WCH webpage on CH32V307: https://www.wch-ic.com/products/CH32V307.html +.. _WCH LinkE: https://www.wch-ic.com/products/WCH-Link.html diff --git a/boards/scdz/ch32v307evt/support/openocd.cfg b/boards/scdz/ch32v307evt/support/openocd.cfg new file mode 100644 index 0000000000000..56a18d77eec4d --- /dev/null +++ b/boards/scdz/ch32v307evt/support/openocd.cfg @@ -0,0 +1,18 @@ +#interface wlink +adapter driver wlinke +adapter speed 6000 +transport select sdi + +wlink_set_address 0x00000000 +set _CHIPNAME wch_riscv +sdi newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x00001 + +set _TARGETNAME $_CHIPNAME.cpu + +target create $_TARGETNAME.0 wch_riscv -chain-position $_TARGETNAME +$_TARGETNAME.0 configure -work-area-phys 0x20000000 -work-area-size 10000 -work-area-backup 1 +set _FLASHNAME $_CHIPNAME.flash + +flash bank $_FLASHNAME wch_riscv 0x00000000 0 0 0 $_TARGETNAME.0 + +echo "Ready for Remote Connections" diff --git a/boards/scdz/index.rst b/boards/scdz/index.rst new file mode 100644 index 0000000000000..c83fe1bfffa4d --- /dev/null +++ b/boards/scdz/index.rst @@ -0,0 +1,10 @@ +.. _boards-scdz: + +SCDZ - Shenzhen Qiushi IoT Technology Co., Ltd. +############################################### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/dts/bindings/vendor-prefixes.txt b/dts/bindings/vendor-prefixes.txt index c6874ab32dee0..c62a253a758e6 100644 --- a/dts/bindings/vendor-prefixes.txt +++ b/dts/bindings/vendor-prefixes.txt @@ -595,6 +595,7 @@ sandisk Sandisk Corporation satoz Satoz International Co., Ltd sbs Smart Battery System sc Space Cubics, LLC +scdz Shenzhen Qiushi IoT Technology Co., Ltd. schindler Schindler sciosense Sciosense B.V. seagate Seagate Technology PLC diff --git a/dts/riscv/wch/ch32v307/ch32v307.dtsi b/dts/riscv/wch/ch32v307/ch32v307.dtsi new file mode 100644 index 0000000000000..6e651d64251d6 --- /dev/null +++ b/dts/riscv/wch/ch32v307/ch32v307.dtsi @@ -0,0 +1,226 @@ +/* + * Copyright (c) 2025 Thomas Boje + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include +#include + +/ { + clocks { + clk_hse: clk-hse { + #clock-cells = <0>; + compatible = "wch,ch32v00x-hse-clock"; + clock-frequency = ; + status = "disabled"; + }; + + clk_hsi: clk-hsi { + #clock-cells = <0>; + compatible = "wch,ch32v00x-hsi-clock"; + clock-frequency = ; + status = "disabled"; + }; + + clk_lsi: clk-lsi { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = ; + status = "disabled"; + }; + + pll: pll { + #clock-cells = <0>; + compatible = "wch,ch32v20x_30x-pll-clock"; + mul = <18>; + status = "disabled"; + }; + }; + + soc { + sram0: memory@20000000 { + compatible = "mmio-sram"; + reg = <0x20000000 DT_SIZE_K(32)>; + }; + + flash: flash-controller@40022000 { + compatible = "wch,ch32v20x_30x-flash-controller"; + reg = <0x40022000 0x400>; + + #address-cells = <1>; + #size-cells = <1>; + + flash0: flash@8000000 { + compatible = "soc-nv-flash"; + reg = <0x08000000 DT_SIZE_K(480)>; + }; + }; + + pwr: pwr@40007000 { + compatible = "wch,pwr"; + reg = <0x40007000 16>; + }; + + pinctrl: pin-controller@40010000 { + compatible = "wch,20x_30x-afio"; + reg = <0x40010000 16>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&rcc CH32V20X_V30X_CLOCK_AFIO>; + + gpioa: gpio@40010800 { + compatible = "wch,gpio"; + reg = <0x40010800 0x20>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + clocks = <&rcc CH32V20X_V30X_CLOCK_IOPA>; + }; + + gpiob: gpio@40010C00 { + compatible = "wch,gpio"; + reg = <0x40010C00 0x20>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + clocks = <&rcc CH32V20X_V30X_CLOCK_IOPB>; + }; + + gpioc: gpio@40011000 { + compatible = "wch,gpio"; + reg = <0x40011000 0x20>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + clocks = <&rcc CH32V20X_V30X_CLOCK_IOPC>; + }; + + gpiod: gpio@40011400 { + compatible = "wch,gpio"; + reg = <0x40011400 0x20>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + clocks = <&rcc CH32V20X_V30X_CLOCK_IOPD>; + }; + + gpioe: gpio@40011800 { + compatible = "wch,gpio"; + reg = <0x40011800 0x20>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + clocks = <&rcc CH32V20X_V30X_CLOCK_IOPE>; + }; + }; + + usart1: uart@40013800 { + compatible = "wch,usart"; + reg = <0x40013800 0x20>; + clocks = <&rcc CH32V20X_V30X_CLOCK_USART1>; + interrupt-parent = <&pfic>; + interrupts = <53>; + status = "disabled"; + }; + + usart2: uart@40004400 { + compatible = "wch,usart"; + reg = <0x40004400 0x20>; + clocks = <&rcc CH32V20X_V30X_CLOCK_USART2>; + interrupt-parent = <&pfic>; + interrupts = <54>; + status = "disabled"; + }; + + usart3: uart@40004800 { + compatible = "wch,usart"; + reg = <0x40004800 0x20>; + clocks = <&rcc CH32V20X_V30X_CLOCK_USART3>; + interrupt-parent = <&pfic>; + interrupts = <55>; + status = "disabled"; + }; + + usart4: uart@40004c00 { + compatible = "wch,usart"; + reg = <0x40004C00 0x20>; + clocks = <&rcc CH32V20X_V30X_CLOCK_USART4>; + interrupt-parent = <&pfic>; + interrupts = <68>; + status = "disabled"; + }; + + usart5: uart@40005000 { + compatible = "wch,usart"; + reg = <0x40005000 0x20>; + clocks = <&rcc CH32V20X_V30X_CLOCK_USART5>; + interrupt-parent = <&pfic>; + interrupts = <69>; + status = "disabled"; + }; + + usart6: uart@40001800 { + compatible = "wch,usart"; + reg = <0x40001800 0x20>; + clocks = <&rcc CH32V20X_V30X_CLOCK_USART6>; + interrupt-parent = <&pfic>; + interrupts = <87>; + status = "disabled"; + }; + + usart7: uart@40001c00 { + compatible = "wch,usart"; + reg = <0x40001c00 0x20>; + clocks = <&rcc CH32V20X_V30X_CLOCK_USART7>; + interrupt-parent = <&pfic>; + interrupts = <88>; + status = "disabled"; + }; + + usart8: uart@40002000 { + compatible = "wch,usart"; + reg = <0x40002000 0x20>; + clocks = <&rcc CH32V20X_V30X_CLOCK_USART8>; + interrupt-parent = <&pfic>; + interrupts = <89>; + status = "disabled"; + }; + + rcc: rcc@40021000 { + compatible = "wch,rcc"; + reg = <0x40021000 16>; + #clock-cells = <1>; + status = "okay"; + }; + + dma1: dma@40020000 { + compatible = "wch,wch-dma"; + reg = <0x40020000 0x90>; + clocks = <&rcc CH32V20X_V30X_CLOCK_DMA1>; + #dma-cells = <1>; + interrupt-parent = <&pfic>; + interrupts = <27>, <28>, <29>, <30>, <31>, <32>, <33>; + dma-channels = <7>; + }; + + dma2: dma@40020400 { + compatible = "wch,wch-dma"; + reg = <0x40020400 0x90>; + clocks = <&rcc CH32V20X_V30X_CLOCK_DMA2>; + #dma-cells = <1>; + interrupt-parent = <&pfic>; + interrupts = <72>, <73>, <74>, <75>, <76>, <98>, <99>, <100>, + <101>, <102>, <103>; + dma-channels = <11>; + }; + }; +}; + +&cpu0 { + clock-frequency = ; +}; diff --git a/dts/riscv/wch/ch32v307/ch32v307rc.dtsi b/dts/riscv/wch/ch32v307/ch32v307rc.dtsi new file mode 100644 index 0000000000000..2ff0f6e6fb2ca --- /dev/null +++ b/dts/riscv/wch/ch32v307/ch32v307rc.dtsi @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2025 Thomas Boje + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&gpiod { + gpio-reserved-ranges = <3 13>; +}; + +&gpioe { + gpio-reserved-ranges = <0 16>; +}; diff --git a/dts/riscv/wch/ch32v307/ch32v307vc.dtsi b/dts/riscv/wch/ch32v307/ch32v307vc.dtsi new file mode 100644 index 0000000000000..99a507d21d9e4 --- /dev/null +++ b/dts/riscv/wch/ch32v307/ch32v307vc.dtsi @@ -0,0 +1,8 @@ +/* + * Copyright (c) 2025 Thomas Boje + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + \ No newline at end of file diff --git a/dts/riscv/wch/ch32v307/ch32v307wc.dtsi b/dts/riscv/wch/ch32v307/ch32v307wc.dtsi new file mode 100644 index 0000000000000..6598f55d2f703 --- /dev/null +++ b/dts/riscv/wch/ch32v307/ch32v307wc.dtsi @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2025 Thomas Boje + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&gpiod { + gpio-reserved-ranges = <3 5>, <10 6>; +}; + +&gpioe { + gpio-reserved-ranges = <1 15>; +}; diff --git a/soc/wch/ch32v/qingke_v4f/Kconfig.defconfig.ch32v307 b/soc/wch/ch32v/qingke_v4f/Kconfig.defconfig.ch32v307 new file mode 100644 index 0000000000000..ba74f463f2dbd --- /dev/null +++ b/soc/wch/ch32v/qingke_v4f/Kconfig.defconfig.ch32v307 @@ -0,0 +1,12 @@ +# Copyright (c) 2025 Thomas Boje +# SPDX-License-Identifier: Apache-2.0 + +if SOC_CH32V307 + +config VECTOR_TABLE_SIZE + default 103 + +config NUM_IRQS + default 128 + +endif # SOC_CH32V307 diff --git a/soc/wch/ch32v/qingke_v4f/Kconfig.soc.ch32v307 b/soc/wch/ch32v/qingke_v4f/Kconfig.soc.ch32v307 new file mode 100644 index 0000000000000..fbe3f12243c46 --- /dev/null +++ b/soc/wch/ch32v/qingke_v4f/Kconfig.soc.ch32v307 @@ -0,0 +1,9 @@ +# Copyright (c) 2025 Thomas Boje +# SPDX-License-Identifier: Apache-2.0 + +config SOC_CH32V307 + bool + select SOC_SERIES_QINGKE_V4F + +config SOC + default "ch32v307" if SOC_CH32V307 diff --git a/soc/wch/ch32v/qingke_v4f/vector.S b/soc/wch/ch32v/qingke_v4f/vector.S index 97766e820fddf..16ebe1b4c0271 100644 --- a/soc/wch/ch32v/qingke_v4f/vector.S +++ b/soc/wch/ch32v/qingke_v4f/vector.S @@ -18,9 +18,11 @@ GTEXT(__initialize) SECTION_FUNC(vectors, ivt) .option norvc + #ifndef SOC_CH32V307 /* Jump to 0x08000008, into the main flash zone where j __start is */ lui x5, 0x8000 jr 0x8(x5) + #endif // SOC_CH32V307 j __start .rept CONFIG_VECTOR_TABLE_SIZE .word _isr_wrapper diff --git a/soc/wch/ch32v/soc.yml b/soc/wch/ch32v/soc.yml index bc63f90869378..99406af090e29 100644 --- a/soc/wch/ch32v/soc.yml +++ b/soc/wch/ch32v/soc.yml @@ -1,4 +1,5 @@ # Copyright (c) 2024 Michael Hope +# Copyright (c) 2025 Thomas Boje # SPDX-License-Identifier: Apache-2.0 family: @@ -19,3 +20,4 @@ family: - name: qingke-v4f socs: - name: ch32v303 + - name: ch32v307