diff --git a/boards/renesas/rza3m_ek/Kconfig.rza3m_ek b/boards/renesas/rza3m_ek/Kconfig.rza3m_ek new file mode 100644 index 000000000000..8675734db1ca --- /dev/null +++ b/boards/renesas/rza3m_ek/Kconfig.rza3m_ek @@ -0,0 +1,5 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_RZA3M_EK + select SOC_R9A07G066M04GBG diff --git a/boards/renesas/rza3m_ek/board.cmake b/boards/renesas/rza3m_ek/board.cmake new file mode 100644 index 000000000000..5622192b6c5e --- /dev/null +++ b/boards/renesas/rza3m_ek/board.cmake @@ -0,0 +1,10 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(jlink "--device=R9A07G066M04") +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) + +if(CONFIG_BUILD_WITH_RZA_IPL) + set(RZA_PLAT a3m) + set(RZA_BOARD a3m_ek_nor) +endif() diff --git a/boards/renesas/rza3m_ek/board.yml b/boards/renesas/rza3m_ek/board.yml new file mode 100644 index 000000000000..1329537f95b5 --- /dev/null +++ b/boards/renesas/rza3m_ek/board.yml @@ -0,0 +1,6 @@ +board: + name: rza3m_ek + full_name: RZ/A3M Evaluation Kit + vendor: renesas + socs: + - name: r9a07g066m04gbg diff --git a/boards/renesas/rza3m_ek/doc/index.rst b/boards/renesas/rza3m_ek/doc/index.rst new file mode 100644 index 000000000000..7291e148453c --- /dev/null +++ b/boards/renesas/rza3m_ek/doc/index.rst @@ -0,0 +1,162 @@ +.. zephyr:board:: rza3m_ek + +Overview +******** + +The EK-RZ/A3M evaluation kit enables users to easily evaluate the features of the RZ/A3M MPU. +This kit includes an EK-RZ/A3M board, 5-inch 720x1280 pixel LCD MIPI graphics expansion board, and +USB cables, allowing the seamless evaluation of high-definition human machine interface (HMI), camera +input through USB, and more features. Equipped with an on-board J-Link debugger, users can +conveniently start debugging without additional debuggers. +Additionally, it also has several expansion connectors such as SDIO, PMOD,and Arduino to connect +sensors, Wi-Fi, and Bluetooth® Low Energy (LE), allowing users to add more features without +expanding the board space. + +* Special Feature Access + + * MIPI DSI 4 lanes & parallel graphics expansion ports + * 5-inch MIPI LCD panel (720x1280 pixels) + * USB High-Speed Host & Device + * 32MB External QSPI NOR Flash + * 128MB External QSPI NAND Flash + * External sound codec + * External RTC + +* MPU Native Pin Access + + * R9A07G066M04GBG MPU + * 1GHz, Arm Cortex®-A55 core w/NEON extension + * Built-in 128MB DDR3L DRAM + * 128KB SRAM w/ECC + * 244 pins, BGA package + * Native pin access + * MPU & USB current measurement + +* Ecosystem & System Control Access + + * USB High-Speed Host & Device + * 5V input through USB (Debug, HS, USB-PD) or external power supply + * Debug on-board (Segger J-Link®) + * Debug external (SWD & JTAG) + * SCIF download (SWD) + * 3 user LEDs & 2 user buttons + * 2 SeeedGrove® system (I2C & analog) + * 2 Digilent Pmod™ (I2C, SPI or UART selectable) + * Arduino™ (Uno R3) + * MikroElektronika™ mikroBUS + * SparkFun® Qwiic® (I2C) + * MPU boot configuration switch + * Audio In/Out 4-pole + * MicroSD card slot + +* Kit Contents + + * EK-RZ/A3M board + * MIPI graphics expansion board + * USB cable (USB C to USB C) + * USB cable (USB A female to USB C) + * USB cable (USB A male to USB C) + * Screw and spacer for fixing the sub board + +Hardware +******** +The Renesas RZ/A3M MPU documentation can be found at `RZ/A3M Group Website`_ + +.. figure:: rza3m_block_diagram.webp + :width: 600px + :align: center + :alt: RZ/A3M group feature + + RZ/A3M block diagram (Credit: Renesas Electronics Corporation) + +Detailed hardware features for the board can be found at `EK-RZ/A3M Website`_ + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +Programming and Debugging +************************* + +EK-RZ/A3M uses Initial Program Loader (IPL) to perform initial settings and copy the Zephyr image from flash to DDR SRAM for execution. +It only needs to be written to flash at lease once before running Zephyr. + +1. For the board setup and connections, follow "3.2 Board Setup" of `Getting Started with RZ/A Flexible Software Package`_. + +2. Enable the IPL build with ``-DCONFIG_BUILD_WITH_RZA_IPL=y``. + The IPL image ``rza3m_ek_nor_ipl.bin`` is generated under zephyrproject/zephyr/build/rza_ipl/a3m/release + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: rza3m_ek + :goals: build + :gen-args: -DCONFIG_BUILD_WITH_RZA_IPL=y + +.. note:: + Currently, the IPL source code can built on Linux environment only. + For Windows, please follow `Initial Program Loader Application Note`_ + +3. Flash it onto the board at address 0x20000000 by Jlink command `Segger JLink Renesas R9A07G066`_ + +.. code-block:: console + + $ JLinkExe + J-Link> connect + Device> R9A07G066M04 + TIF> s + Speed> [Enter] + J-Link> h + J-Link> loadfile 0x20000000 + +Where ```` is the path to the ``rza3m_ek_nor_ipl.bin`` in the output directory. + +Applications for the ``rza3m_ek`` board can be built in the usual way as +documented in :ref:`build_an_application`. + +Console +======= +The UART port is accessed by USB Debug connector (J10). + +Debugging +========= + +It is possible to load and execute a Zephyr application binary on this board on the Cortex-A55 System Core +from the DDR SDRAM, using ``JLink`` debugger (:ref:`jlink-debug-host-tools`). + +Here is an example for building and debugging with the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: rza3m_ek + :goals: build debug + +Flashing +======== + +Zephyr application can be flashed to Quad-SPI storage and then loaded by Initial Program Loader. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: rza3m_ek + :goals: build flash + +References +********** + +.. target-notes:: + +.. _RZ/A3M Group Website: + https://www.renesas.com/en/products/microcontrollers-microprocessors/rz-mpus/rza3m-powerful-1ghz-mpus-built-ddr3l-sdram-high-definition-hmi + +.. _EK-RZ/A3M Website: + https://www.renesas.com/en/products/microcontrollers-microprocessors/rz-mpus/ek-rza3m-evaluation-kit-rza3m-mpu + +.. _Initial Program Loader Application Note: + https://github.com/renesas/rza-initial-program-loader/tree/main/application_note + +.. _Getting Started with RZ/A Flexible Software Package: + https://www.renesas.com/en/document/apn/rza-getting-started-flexible-software-package + +.. _Segger JLink Renesas R9A07G066: + https://kb.segger.com/Renesas_R9A07G066 diff --git a/boards/renesas/rza3m_ek/doc/rza3m_block_diagram.webp b/boards/renesas/rza3m_ek/doc/rza3m_block_diagram.webp new file mode 100644 index 000000000000..b3ca900ac02e Binary files /dev/null and b/boards/renesas/rza3m_ek/doc/rza3m_block_diagram.webp differ diff --git a/boards/renesas/rza3m_ek/doc/rza3m_ek.webp b/boards/renesas/rza3m_ek/doc/rza3m_ek.webp new file mode 100644 index 000000000000..2fb1c7b51a6d Binary files /dev/null and b/boards/renesas/rza3m_ek/doc/rza3m_ek.webp differ diff --git a/boards/renesas/rza3m_ek/rza3m_ek-pinctrl.dtsi b/boards/renesas/rza3m_ek/rza3m_ek-pinctrl.dtsi new file mode 100644 index 000000000000..fa21bc8f910e --- /dev/null +++ b/boards/renesas/rza3m_ek/rza3m_ek-pinctrl.dtsi @@ -0,0 +1,18 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +&pinctrl { + /omit-if-no-ref/ scif0_pins: scif0 { + scif0-pinmux { + pinmux = , /* RXD */ + ; /* TXD */ + drive-strength = <1>; + slew-rate = "fast"; + }; + }; +}; diff --git a/boards/renesas/rza3m_ek/rza3m_ek.dts b/boards/renesas/rza3m_ek/rza3m_ek.dts new file mode 100644 index 000000000000..da1360388274 --- /dev/null +++ b/boards/renesas/rza3m_ek/rza3m_ek.dts @@ -0,0 +1,124 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include +#include +#include +#include "rza3m_ek-pinctrl.dtsi" + +/ { + model = "Renesas RZ/A3M EK"; + compatible = "renesas,rza3m-ek"; + + chosen { + zephyr,sram = &ddr; + zephyr,flash = &spi_flash; + zephyr,console = &scif0; + zephyr,shell-uart = &scif0; + zephyr,code-partition= &slot0_partition; + }; + + ddr: memory@40200000 { + compatible ="zephyr,memory-region", "mmio-sram"; + reg = <0x40200000 (DT_SIZE_M(128) - 0x200000)>; + zephyr,memory-region = "DDR"; + }; + + sram: memory@1e000 { + compatible ="zephyr,memory-region", "mmio-sram"; + reg = <0x1e000 DT_SIZE_K(72)>; + zephyr,memory-region = "SRAM"; + }; + + spi_flash: memory@20020000 { + compatible = "mmio-sram"; + reg = <0x20020000 (DT_SIZE_M(16) - 0x20000)>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + header: partition@0 { + label = "header"; + reg = <0x00000000 0x200>; + read-only; + }; + + slot0_partition: partition@200 { + label = "image-0"; + reg = <0x00000200 (DT_SIZE_M(16) - 0x20200)>; + read-only; + }; + }; + }; + + aliases { + led0 = &led1; + sw0 = &sw1; + }; + + leds { + compatible = "gpio-leds"; + + led1: led1 { + gpios = <&gpio10 1 GPIO_ACTIVE_HIGH>; + label = "led1"; + }; + + led2: led2 { + gpios = <&gpio20 3 GPIO_ACTIVE_HIGH>; + label = "led2"; + }; + + led3: led3 { + gpios = <&gpio20 4 GPIO_ACTIVE_HIGH>; + label = "led3"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + + sw1: sw1 { + label = "sw1"; + gpios = <&gpio10 3 GPIO_ACTIVE_HIGH>; + zephyr,code = ; + }; + + sw2: sw2 { + label = "sw2"; + gpios = <&gpio11 1 GPIO_ACTIVE_HIGH>; + zephyr,code = ; + }; + }; +}; + +&scif0 { + current-speed = <115200>; + pinctrl-0 = <&scif0_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&gpio { + status = "okay"; +}; + +&gpio10 { + status = "okay"; +}; + +&gpio11 { + status = "okay"; +}; + +&gpio20 { + status = "okay"; +}; diff --git a/boards/renesas/rza3m_ek/rza3m_ek.yaml b/boards/renesas/rza3m_ek/rza3m_ek.yaml new file mode 100644 index 000000000000..a723d7ee3c18 --- /dev/null +++ b/boards/renesas/rza3m_ek/rza3m_ek.yaml @@ -0,0 +1,13 @@ +identifier: rza3m_ek +name: Renesas RZ/A3M Evaluation Kit +type: mcu +arch: arm64 +toolchain: + - zephyr + - cross-compile +supported: + - uart + - gpio +testing: + ignore_tags: + - bluetooth diff --git a/boards/renesas/rza3m_ek/rza3m_ek_defconfig b/boards/renesas/rza3m_ek/rza3m_ek_defconfig new file mode 100644 index 000000000000..dd2f33248dd5 --- /dev/null +++ b/boards/renesas/rza3m_ek/rza3m_ek_defconfig @@ -0,0 +1,19 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_XIP=n + +# MMU Options +CONFIG_MAX_XLAT_TABLES=24 + +# Cache Options +CONFIG_CACHE_MANAGEMENT=y +CONFIG_DCACHE_LINE_SIZE_DETECT=y +CONFIG_ICACHE_LINE_SIZE_DETECT=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/drivers/gpio/gpio_renesas_rz.h b/drivers/gpio/gpio_renesas_rz.h index 3258ca8bd06b..04ef2c062c9f 100644 --- a/drivers/gpio/gpio_renesas_rz.h +++ b/drivers/gpio/gpio_renesas_rz.h @@ -15,7 +15,7 @@ #if defined(CONFIG_SOC_SERIES_RZG3S) || defined(CONFIG_SOC_SERIES_RZA3UL) || \ defined(CONFIG_SOC_SERIES_RZV2L) || defined(CONFIG_SOC_SERIES_RZG2L) || \ defined(CONFIG_SOC_SERIES_RZV2H) || defined(CONFIG_SOC_SERIES_RZG2UL) || \ - defined(CONFIG_SOC_SERIES_RZV2N) + defined(CONFIG_SOC_SERIES_RZV2N) || defined(CONFIG_SOC_SERIES_RZA3M) #include #if defined(CONFIG_SOC_SERIES_RZG3S) @@ -40,6 +40,18 @@ static const uint8_t gpio_rz_int[GPIO_RZ_MAX_PORT_NUM] = {0, 4, 9, 13, 17, 23 static const uint8_t gpio_rz_int[GPIO_RZ_MAX_PORT_NUM] = {0, 4, 9, 13, 17, 23, 28, 33, 38, 43, 47, 52, 56, 58, 63, 66, 70, 72, 76}; +#elif defined(CONFIG_SOC_SERIES_RZA3M) +#define GPIO_RZ_P_REG_BASE_GET (&R_GPIO->P01) +#define GPIO_RZ_PM_REG_BASE_GET (&R_GPIO->PM01) +#define GPIO_RZ_PFC_REG_BASE_GET (&R_GPIO->PFC01) +#define GPIO_RZ_MAX_PORT_NUM 24 +#define GPIO_RZ_TINT_IRQ_OFFSET 476 +#define R_INTC R_INTC_IA55 +#define GPIO_RZ_TINT_STATUS_REG_CLEAR(tint_num) (R_INTC_IA55->TSCR &= ~BIT(tint_num)) +static const uint8_t gpio_rz_int[GPIO_RZ_MAX_PORT_NUM] = {0, 4, 9, 13, 17, 23, 28, 33, 38, 42, + 47, 52, 56, 0, 0, 0, 0, 0, 0, 0, + 58, 64, 67, 72}; + #elif defined(CONFIG_SOC_SERIES_RZV2H) || defined(CONFIG_SOC_SERIES_RZV2N) #define GPIO_RZ_P_REG_BASE_GET (&R_GPIO->P20) #define GPIO_RZ_PM_REG_BASE_GET (&R_GPIO->PM20) diff --git a/dts/arm64/renesas/rz/rza/r9a07g066.dtsi b/dts/arm64/renesas/rz/rza/r9a07g066.dtsi new file mode 100644 index 000000000000..89194ac329fd --- /dev/null +++ b/dts/arm64/renesas/rz/rza/r9a07g066.dtsi @@ -0,0 +1,384 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include + +/ { + compatible = "renesas,r9a07g066"; + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + clock-frequency = ; + reg = <0>; + }; + }; + + arch_timer: timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + interrupt-parent = <&gic>; + }; + + osc: osc { + compatible = "fixed-clock"; + clock-frequency = ; + #clock-cells = <0>; + }; + + soc { + interrupt-parent = <&gic>; + + gic: interrupt-controller@11900000 { + compatible = "arm,gic-v3", "arm,gic"; + reg = <0x11900000 0x10000>, /* GICD */ + <0x11940000 0x20000>; /* GICR */ + interrupt-controller; + #interrupt-cells = <4>; + status = "okay"; + }; + + pinctrl: pin-controller@11030000 { + compatible = "renesas,rza-pinctrl"; + reg = <0x11030000 DT_SIZE_K(64)>; + reg-names = "pinctrl"; + + gpio: gpio-common { + compatible = "renesas,rz-gpio-int"; + interrupts = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + gpio0: gpio@f00 { + compatible = "renesas,rz-gpio"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <4>; + reg = <0xf00>; + status = "disabled"; + }; + + gpio1: gpio@1000 { + compatible = "renesas,rz-gpio"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <5>; + reg = <0x1000>; + status = "disabled"; + }; + + gpio2: gpio@1100 { + compatible = "renesas,rz-gpio"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <4>; + reg = <0x1100>; + status = "disabled"; + }; + + gpio3: gpio@1200 { + compatible = "renesas,rz-gpio"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <4>; + reg = <0x1200>; + status = "disabled"; + }; + + gpio4: gpio@1300 { + compatible = "renesas,rz-gpio"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <6>; + reg = <0x1300>; + status = "disabled"; + }; + + gpio5: gpio@1400 { + compatible = "renesas,rz-gpio"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <5>; + reg = <0x1400>; + status = "disabled"; + }; + + gpio6: gpio@1500 { + compatible = "renesas,rz-gpio"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <5>; + reg = <0x1500>; + status = "disabled"; + }; + + gpio7: gpio@1600 { + compatible = "renesas,rz-gpio"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <2>; + reg = <0x1600>; + status = "disabled"; + }; + + gpio8: gpio@1700 { + compatible = "renesas,rz-gpio"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <4>; + reg = <0x1700>; + status = "disabled"; + }; + + gpio9: gpio@1800 { + compatible = "renesas,rz-gpio"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <5>; + reg = <0x1800>; + status = "disabled"; + }; + + gpio10: gpio@1900 { + compatible = "renesas,rz-gpio"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <4>; + reg = <0x1900>; + status = "disabled"; + }; + + gpio11: gpio@1a00 { + compatible = "renesas,rz-gpio"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <4>; + reg = <0x1a00>; + status = "disabled"; + }; + + gpio12: gpio@1b00 { + compatible = "renesas,rz-gpio"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <2>; + reg = <0x1b00>; + status = "disabled"; + }; + + gpio13: gpio@1c00 { + compatible = "renesas,rz-gpio"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <0>; + reg = <0x1c00>; + status = "disabled"; + }; + + gpio14: gpio@1d00 { + compatible = "renesas,rz-gpio"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <0>; + reg = <0x1d00>; + status = "disabled"; + }; + + gpio15: gpio@1e00 { + compatible = "renesas,rz-gpio"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <0>; + reg = <0x1e00>; + status = "disabled"; + }; + + gpio16: gpio@1f00 { + compatible = "renesas,rz-gpio"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <0>; + reg = <0x1f00>; + status = "disabled"; + }; + + gpio17: gpio@2000 { + compatible = "renesas,rz-gpio"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <0>; + reg = <0x2000>; + status = "disabled"; + }; + + gpio18: gpio@2100 { + compatible = "renesas,rz-gpio"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <0>; + reg = <0x2100>; + status = "disabled"; + }; + + gpio19: gpio@2200 { + compatible = "renesas,rz-gpio"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <0>; + reg = <0x2200>; + status = "disabled"; + }; + + gpio20: gpio@0 { + compatible = "renesas,rz-gpio"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <6>; + reg = <0x0>; + status = "disabled"; + }; + + gpio21: gpio@100 { + compatible = "renesas,rz-gpio"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <3>; + reg = <0x100>; + status = "disabled"; + }; + + gpio22: gpio@300 { + compatible = "renesas,rz-gpio"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <5>; + reg = <0x300>; + status = "disabled"; + }; + + gpio23: gpio@400 { + compatible = "renesas,rz-gpio"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <2>; + reg = <0x400>; + status = "disabled"; + }; + }; + }; + + scif0: serial@1004b800 { + compatible = "renesas,rz-scif-uart"; + channel = <0>; + reg = <0x1004b800 0x400>; + interrupts = , + , + , + , + ; + interrupt-names = "eri", "bri", "rxi", "txi", "tei"; + status = "disabled"; + }; + + scif1: serial@1004bc00 { + compatible = "renesas,rz-scif-uart"; + channel = <1>; + reg = <0x1004bc00 0x400>; + interrupts = , + , + , + , + ; + interrupt-names = "eri", "bri", "rxi", "txi", "tei"; + status = "disabled"; + }; + + scif2: serial@1004c000 { + compatible = "renesas,rz-scif-uart"; + channel = <2>; + reg = <0x1004c000 0x400>; + interrupts = , + , + , + , + ; + interrupt-names = "eri", "bri", "rxi", "txi", "tei"; + status = "disabled"; + }; + + scif3: serial@1004c400 { + compatible = "renesas,rz-scif-uart"; + channel = <3>; + reg = <0x1004c400 0x400>; + interrupts = , + , + , + , + ; + interrupt-names = "eri", "bri", "rxi", "txi", "tei"; + status = "disabled"; + }; + + scif4: serial@1004c800 { + compatible = "renesas,rz-scif-uart"; + channel = <4>; + reg = <0x1004c800 0x400>; + interrupts = , + , + , + , + ; + interrupt-names = "eri", "bri", "rxi", "txi", "tei"; + status = "disabled"; + }; + }; +}; diff --git a/include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-rza3m.h b/include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-rza3m.h new file mode 100644 index 000000000000..cc7dee10c741 --- /dev/null +++ b/include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-rza3m.h @@ -0,0 +1,68 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_RZA3M_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_RZA3M_H_ + +/* Superset list of all possible IO ports. */ +#define PORT_00 0x0F00 /* IO port 0 */ +#define PORT_01 0x1000 /* IO port 1 */ +#define PORT_02 0x1100 /* IO port 2 */ +#define PORT_03 0x1200 /* IO port 3 */ +#define PORT_04 0x1300 /* IO port 4 */ +#define PORT_05 0x1400 /* IO port 5 */ +#define PORT_06 0x1500 /* IO port 6 */ +#define PORT_07 0x1600 /* IO port 7 */ +#define PORT_08 0x1700 /* IO port 8 */ +#define PORT_09 0x1800 /* IO port 9 */ +#define PORT_10 0x1900 /* IO port 10 */ +#define PORT_11 0x1A00 /* IO port 11 */ +#define PORT_12 0x1B00 /* IO port 12 */ +#define PORT_20 0x0000 /* IO port 20 */ +#define PORT_21 0x0100 /* IO port 21 */ +#define PORT_22 0x0300 /* IO port 22 */ +#define PORT_23 0x0400 /* IO port 23 */ + +/* + * Create the value contain port/pin/function information + * + * port: port number BSP_IO_PORT_00..BSP_IO_PORT_18 + * pin: pin number + * func: pin function + */ +#define RZA_PINMUX(port, pin, func) (port | pin | (func << 4)) + +/* Special purpose port */ +#define BSP_IO_NMI 0xFFFF0001 /* NMI */ + +#define BSP_IO_TMS_SWDIO 0xFFFF0200 /* TMS_SWDIO */ + +#define BSP_IO_SD0_CLK 0xFFFF0400 /* SD0_CLK */ + +#define BSP_IO_QSPI0_SPCLK 0xFFFF0500 /* QSPI0_SPCLK */ +#define BSP_IO_QSPI0_IO0 0xFFFF0501 /* QSPI0_IO0 */ +#define BSP_IO_QSPI0_IO1 0xFFFF0502 /* QSPI0_IO1 */ +#define BSP_IO_QSPI0_SSL 0xFFFF0505 /* QSPI0_SSL */ + +#define BSP_IO_WDTOVF_PERROUT 0xFFFF0600 /* WDTOVF_PERROUT */ + +#define BSP_IO_RIIC0_SDA 0xFFFF0700 /* RIIC0_SDA */ +#define BSP_IO_RIIC0_SCL 0xFFFF0701 /* RIIC0_SCL */ + +/* FILNUM */ +#define RZA_FILNUM_4_STAGE 0 +#define RZA_FILNUM_8_STAGE 1 +#define RZA_FILNUM_12_STAGE 2 +#define RZA_FILNUM_16_STAGE 3 + +/* FILCLKSEL */ +#define RZA_FILCLKSEL_NOT_DIV 0 +#define RZA_FILCLKSEL_DIV_9000 1 +#define RZA_FILCLKSEL_DIV_18000 2 +#define RZA_FILCLKSEL_DIV_36000 3 + +#define RZA_FILTER_SET(filnum, filclksel) (((filnum) & 0x3) << 0x2) | (filclksel & 0x3) + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_RZA3M_H_ */ diff --git a/modules/Kconfig.renesas b/modules/Kconfig.renesas index 479d96f56e1b..8e647c6d1b5d 100644 --- a/modules/Kconfig.renesas +++ b/modules/Kconfig.renesas @@ -265,6 +265,21 @@ config USE_RZ_FSP_SCI_UART help Enable RZ FSP SCI UART driver +menuconfig BUILD_WITH_RZA_IPL + bool "Build with RZ/A Initial Program Loader (IPL)" + help + When enabled, this option instructs the Zephyr build process to + additionally generate IPL image for Renesas RZ/A series. + +if BUILD_WITH_RZA_IPL + +config RZA_IPL_BUILD_DEBUG + bool "Debug build" + help + When enabled, the build type of IPL would be debug. + +endif # BUILD_WITH_RZA_IPL + endif config HAS_RENESAS_RX_RDP diff --git a/soc/renesas/rz/common/pinctrl_rza.h b/soc/renesas/rz/common/pinctrl_rza.h index 5471a358699f..1d7d76bd2377 100644 --- a/soc/renesas/rz/common/pinctrl_rza.h +++ b/soc/renesas/rz/common/pinctrl_rza.h @@ -62,6 +62,14 @@ typedef struct pinctrl_soc_pin_t { #define RZA_FILTER_ON_OFF(node_id) COND_CODE_0(DT_PROP(node_id, renesas_filter), (0), (1)) +#if defined(CONFIG_SOC_SERIES_RZA3M) +#define RZA_GET_PFC(node_id, state_prop, idx) \ + (RZA_GET_FUNC(DT_PROP_BY_IDX(node_id, state_prop, idx)) - 1) +#else +#define RZA_GET_PFC(node_id, state_prop, idx) \ + (RZA_GET_FUNC(DT_PROP_BY_IDX(node_id, state_prop, idx))) +#endif + /* Process pinmux cfg */ #define Z_PINCTRL_PINMUX_INIT(node_id, state_prop, idx) \ { \ @@ -77,7 +85,7 @@ typedef struct pinctrl_soc_pin_t { .filonoff_reg = RZA_FILTER_ON_OFF(node_id), \ .filnum_reg = RZA_GET_FILNUM(node_id), \ .filclksel_reg = RZA_GET_FILCLKSEL(node_id), \ - .pfc_reg = RZA_GET_FUNC(DT_PROP_BY_IDX(node_id, state_prop, idx)), \ + .pfc_reg = RZA_GET_PFC(node_id, state_prop, idx), \ }, \ }, diff --git a/soc/renesas/rz/rza3m/CMakeLists.txt b/soc/renesas/rz/rza3m/CMakeLists.txt new file mode 100644 index 000000000000..b7bb7ee2f2a6 --- /dev/null +++ b/soc/renesas/rz/rza3m/CMakeLists.txt @@ -0,0 +1,11 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +zephyr_sources(soc.c) +zephyr_library_sources_ifdef(CONFIG_ARM_MMU mmu_regions.c) + +zephyr_include_directories(.) + +zephyr_linker_sources(SECTIONS sections.ld) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm64/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/renesas/rz/rza3m/Kconfig b/soc/renesas/rz/rza3m/Kconfig new file mode 100644 index 000000000000..8f2f4472080c --- /dev/null +++ b/soc/renesas/rz/rza3m/Kconfig @@ -0,0 +1,9 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_RZA3M + select ARM64 + select CPU_CORTEX_A55 + select ARM_ARCH_TIMER + select HAS_RENESAS_RZ_FSP + select SOC_EARLY_INIT_HOOK diff --git a/soc/renesas/rz/rza3m/Kconfig.defconfig b/soc/renesas/rz/rza3m/Kconfig.defconfig new file mode 100644 index 000000000000..2db397ea309e --- /dev/null +++ b/soc/renesas/rz/rza3m/Kconfig.defconfig @@ -0,0 +1,31 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_RZA3M + +config SYS_CLOCK_EXISTS + default y + +config NUM_IRQS + default 512 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default $(dt_node_int_prop_int,/osc,clock-frequency) + +config FLASH_SIZE + default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K) + +config FLASH_BASE_ADDRESS + default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH)) + +DT_CHOSEN_IMAGE_ZEPHYR = zephyr,code-partition +DT_CHOSEN_SRAM_ZEPHYR = zephyr,sram + +config BUILD_OUTPUT_ADJUST_LMA + default "$(dt_chosen_partition_addr_hex,$(DT_CHOSEN_IMAGE_ZEPHYR)) - \ + $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_SRAM_ZEPHYR))" + +config BUILD_OUTPUT_ADJUST_LMA_SECTIONS + default "*;!.header" + +endif # SOC_SERIES_RZA3M diff --git a/soc/renesas/rz/rza3m/Kconfig.soc b/soc/renesas/rz/rza3m/Kconfig.soc new file mode 100644 index 000000000000..b199157a0f95 --- /dev/null +++ b/soc/renesas/rz/rza3m/Kconfig.soc @@ -0,0 +1,20 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_RZA3M + bool + select SOC_FAMILY_RENESAS_RZ + help + Renesas RZ/A3M series + +config SOC_SERIES + default "rza3m" if SOC_SERIES_RZA3M + +config SOC_R9A07G066M04GBG + bool + select SOC_SERIES_RZA3M + help + R9A07G066M04GBG + +config SOC + default "r9a07g066m04gbg" if SOC_R9A07G066M04GBG diff --git a/soc/renesas/rz/rza3m/mmu_regions.c b/soc/renesas/rz/rza3m/mmu_regions.c new file mode 100644 index 000000000000..3f07572e5804 --- /dev/null +++ b/soc/renesas/rz/rza3m/mmu_regions.c @@ -0,0 +1,18 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +static const struct arm_mmu_region mmu_regions[] = { + MMU_REGION_FLAT_ENTRY("IO_REG", 0x10000000, 0x10000000, + MT_DEVICE_nGnRnE | MT_RW | MT_DEFAULT_SECURE_STATE), +}; + +const struct arm_mmu_config mmu_config = { + .num_regions = ARRAY_SIZE(mmu_regions), + .mmu_regions = mmu_regions, +}; diff --git a/soc/renesas/rz/rza3m/pinctrl_soc.h b/soc/renesas/rz/rza3m/pinctrl_soc.h new file mode 100644 index 000000000000..d3bfddf31073 --- /dev/null +++ b/soc/renesas/rz/rza3m/pinctrl_soc.h @@ -0,0 +1,11 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_SOC_RENESAS_RZ_RZA3M_PINCTRL_SOC_H_ +#define ZEPHYR_SOC_RENESAS_RZ_RZA3M_PINCTRL_SOC_H_ + +#include + +#endif /* ZEPHYR_SOC_RENESAS_RZ_RZA3M_PINCTRL_SOC_H_ */ diff --git a/soc/renesas/rz/rza3m/sections.ld b/soc/renesas/rz/rza3m/sections.ld new file mode 100644 index 000000000000..bdc29c67e39d --- /dev/null +++ b/soc/renesas/rz/rza3m/sections.ld @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +SECTION_PROLOGUE(.header, CONFIG_FLASH_BASE_ADDRESS,) +{ + QUAD(__start) + QUAD(0xFFFFFFFFFFFFFFFF-__start) + QUAD(CONFIG_SRAM_BASE_ADDRESS) + QUAD(0xFFFFFFFFFFFFFFFF-CONFIG_SRAM_BASE_ADDRESS) + QUAD(z_mapped_size) + QUAD(0xFFFFFFFFFFFFFFFF-z_mapped_size) + FILL(0x00) + . += 0x1B0; + QUAD(0x4120505346205a52) + QUAD(0x69746163696c7070) + QUAD(0x0000000000006e6f) + QUAD(0x0000000000000000) +} > FLASH + +z_mapped_size = z_mapped_end - z_mapped_start; diff --git a/soc/renesas/rz/rza3m/soc.c b/soc/renesas/rz/rza3m/soc.c new file mode 100644 index 000000000000..b989a4c42957 --- /dev/null +++ b/soc/renesas/rz/rza3m/soc.c @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief System/hardware module for Renesas RZ/A3UL Group + */ + +#include +#include "soc.h" + +uint32_t SystemCoreClock; + +void soc_early_init_hook(void) +{ + /* Configure system clocks. */ + bsp_clock_init(); + + /* Initialize SystemCoreClock variable. */ + SystemCoreClockUpdate(); +} diff --git a/soc/renesas/rz/rza3m/soc.h b/soc/renesas/rz/rza3m/soc.h new file mode 100644 index 000000000000..3769172507ed --- /dev/null +++ b/soc/renesas/rz/rza3m/soc.h @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_SOC_RENESAS_RZA3M_SOC_H_ +#define ZEPHYR_SOC_RENESAS_RZA3M_SOC_H_ + +#include + +#endif /* ZEPHYR_SOC_RENESAS_RZA3M_SOC_H_ */ diff --git a/soc/renesas/rz/soc.yml b/soc/renesas/rz/soc.yml index 929a3140b758..58cf25438348 100644 --- a/soc/renesas/rz/soc.yml +++ b/soc/renesas/rz/soc.yml @@ -4,6 +4,9 @@ family: - name: rza2m socs: - name: r7s921053vcbg + - name: rza3m + socs: + - name: r9a07g066m04gbg - name: rza3ul socs: - name: r9a07g063u02gbg diff --git a/tests/arch/arm64/arm64_high_addresses/testcase.yaml b/tests/arch/arm64/arm64_high_addresses/testcase.yaml index 9b09f9745a61..238ff45ee29d 100644 --- a/tests/arch/arm64/arm64_high_addresses/testcase.yaml +++ b/tests/arch/arm64/arm64_high_addresses/testcase.yaml @@ -2,6 +2,7 @@ common: arch_allow: arm64 platform_exclude: - rza3ul_smarc + - rza3m_ek tags: - arm - userspace diff --git a/tests/drivers/gpio/gpio_basic_api/boards/rza3m_ek.conf b/tests/drivers/gpio/gpio_basic_api/boards/rza3m_ek.conf new file mode 100644 index 000000000000..b9d02cf11d5d --- /dev/null +++ b/tests/drivers/gpio/gpio_basic_api/boards/rza3m_ek.conf @@ -0,0 +1 @@ +CONFIG_SKIP_PULL_TEST=y diff --git a/tests/drivers/gpio/gpio_basic_api/boards/rza3m_ek.overlay b/tests/drivers/gpio/gpio_basic_api/boards/rza3m_ek.overlay new file mode 100644 index 000000000000..bde8907a1fc1 --- /dev/null +++ b/tests/drivers/gpio/gpio_basic_api/boards/rza3m_ek.overlay @@ -0,0 +1,20 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + resources { + compatible = "test-gpio-basic-api"; + out-gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>; + in-gpios = <&gpio8 0 GPIO_ACTIVE_HIGH>; + }; +}; + +&gpio5 { + status = "okay"; +}; + +&gpio8 { + status = "okay"; +};