From be8f49b028cd4d926abfccf2911dc6fdf9dee6fe Mon Sep 17 00:00:00 2001
From: Michael Estes <michael.estes@byteserv.io>
Date: Sat, 31 May 2025 21:09:02 -0400
Subject: [PATCH] dts: xilinx: add cadence spi controllers to zynqmp.dtsi

Adds spi controller nodes for Cadence SPI controllers in zynqmp.dtsi.

Signed-off-by: Michael Estes <michael.estes@byteserv.io>
---
 dts/arm/xilinx/zynqmp.dtsi | 27 ++++++++++++++++++++++++++-
 1 file changed, 26 insertions(+), 1 deletion(-)

diff --git a/dts/arm/xilinx/zynqmp.dtsi b/dts/arm/xilinx/zynqmp.dtsi
index a524c2c271b2..80c4a5335498 100644
--- a/dts/arm/xilinx/zynqmp.dtsi
+++ b/dts/arm/xilinx/zynqmp.dtsi
@@ -304,6 +304,31 @@
 					IRQ_DEFAULT_PRIORITY>;
 			reg = <0xfd070000 0x30000>;
 		};
-	};
 
+		spi0: spi@ff040000 {
+			compatible = "cdns,spi";
+			reg = <0xff040000 0x1000>;
+			status = "disabled";
+			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL
+				      IRQ_DEFAULT_PRIORITY>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			fifo-width = <8>;
+			rx-fifo-depth = <128>;
+			tx-fifo-depth = <128>;
+		};
+
+		spi1: spi@ff050000 {
+			compatible = "cdns,spi";
+			reg = <0xff050000 0x1000>;
+			status = "disabled";
+			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL
+				      IRQ_DEFAULT_PRIORITY>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			fifo-width = <8>;
+			rx-fifo-depth = <128>;
+			tx-fifo-depth = <128>;
+		};
+	};
 };