From d54010a44ae47925013e07d421005c7261c50ff7 Mon Sep 17 00:00:00 2001 From: Quy Tran Date: Wed, 28 May 2025 09:47:05 +0700 Subject: [PATCH 01/10] manifest: hal: renesas: Update commit ID for adding RX261 HAL support Update commit ID for hal_renesas to add support Renesas RX261 Signed-off-by: Quy Tran --- west.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/west.yml b/west.yml index 7032362af5ce..7b73b00ff326 100644 --- a/west.yml +++ b/west.yml @@ -226,7 +226,7 @@ manifest: - hal - name: hal_renesas path: modules/hal/renesas - revision: 0769fe1520f6c14e6301188588da758a609f181d + revision: pull/104/head groups: - hal - name: hal_rpi_pico From cf40e54feebac2c6f1405a34c2a6eba16321362f Mon Sep 17 00:00:00 2001 From: Hau Ho Date: Wed, 14 May 2025 10:58:53 +0700 Subject: [PATCH 02/10] scripts: west: flash: Add support for scripts to flash using the RFP tool. Add support for scripts to flash using the RFP tool. Signed-off-by: Hau Ho --- scripts/west_commands/runners/rfp.py | 57 ++++++++++++++++++++++--- scripts/west_commands/tests/test_rfp.py | 20 ++++++--- 2 files changed, 65 insertions(+), 12 deletions(-) diff --git a/scripts/west_commands/runners/rfp.py b/scripts/west_commands/runners/rfp.py index 507c36e36428..0e885b9805b5 100644 --- a/scripts/west_commands/runners/rfp.py +++ b/scripts/west_commands/runners/rfp.py @@ -8,14 +8,17 @@ import platform import re +from pathlib import Path from runners.core import RunnerCaps, ZephyrBinaryRunner -if platform.system() == 'Darwin': +if platform.system() == 'Darwin' or 'Windows': DEFAULT_RFP_PORT = None else: DEFAULT_RFP_PORT = '/dev/ttyACM0' +RFP_CLI_EXE = 'rfp-cli' + def to_num(number): dev_match = re.search(r"^\d*\+dev", number) @@ -41,6 +44,8 @@ def __init__( erase=False, verify=False, port=DEFAULT_RFP_PORT, + tool=None, + interface=None, speed=None, ): super().__init__(cfg) @@ -49,6 +54,8 @@ def __init__( self.verify = verify self.erase = erase self.port = port + self.tool = tool + self.interface = interface self.device = device self.speed = speed @@ -62,14 +69,25 @@ def capabilities(cls): @classmethod def do_add_parser(cls, parser): + # Find the default efp-cli executable + cls.default_rfp() + parser.add_argument( - '--rfp-cli', default='rfp-cli', help='path to rfp-cli, default is rfp-cli' + '--rfp-cli', default=RFP_CLI_EXE, help='path to rfp-cli, default is rfp-cli' ) parser.add_argument( '--port', default=DEFAULT_RFP_PORT, help='serial port to use, default is ' + str(DEFAULT_RFP_PORT), ) + parser.add_argument( + '--tool', + help='emulator hardware to use (e2, e2l, jlink) when port is not set', + ) + parser.add_argument( + '--interface', + help='selects the communications interface (uart, swd)', + ) parser.add_argument('--device', help='Specify the device type to pass to rfp-cli') parser.add_argument('--verify', action='store_true', help='if given, verify after flash') parser.add_argument('--speed', help='Specify the serial port speed') @@ -81,11 +99,31 @@ def do_create(cls, cfg, args): rfp_cli=args.rfp_cli, device=args.device, port=args.port, + tool=args.tool, + interface=args.interface, erase=args.erase, speed=args.speed, verify=args.verify, ) + @staticmethod + def default_rfp(): + global RFP_CLI_EXE + + if platform.system() == 'Windows': + try: + import winreg + + registry = winreg.ConnectRegistry(None, winreg.HKEY_LOCAL_MACHINE) + key = winreg.OpenKey(registry, r"SOFTWARE\Classes\rpjfile\shell\Open\command") + val = winreg.QueryValue(key, None) + match = re.match(r'"(.*?)".*', val)[1] + RFP_CLI_EXE = str(Path(match).parent / 'rfp-cli.exe') + except Exception: + RFP_CLI_EXE = 'rfp-cli.exe' + else: + RFP_CLI_EXE = 'rfp-cli' + def do_run(self, command, **kwargs): if command == 'flash': self.do_flash(**kwargs) @@ -93,6 +131,7 @@ def do_run(self, command, **kwargs): self.logger.error("Unsuppported command") def do_flash(self, **kwargs): + self.require(self.rfp_cmd[0]) self.ensure_output('hex') hex_name = self.cfg.hex_file @@ -111,10 +150,18 @@ def do_flash(self, **kwargs): # Load image load_image += ['-p', '-file', hex_name] - port = ['-port', self.port] + if self.tool is None: + connection = ['-port', self.port] + else: + connection = ['-tool', self.tool] + + if self.interface: + connection += ['-interface', self.interface] + if self.speed: - port += ['-s', self.speed] + connection += ['-s', self.speed] + device = ['-device', self.device] - cmd = self.rfp_cmd + port + device + load_image + cmd = self.rfp_cmd + connection + device + load_image self.check_call(cmd) diff --git a/scripts/west_commands/tests/test_rfp.py b/scripts/west_commands/tests/test_rfp.py index 26440f8dbc8d..9d27a5b1a8c2 100644 --- a/scripts/west_commands/tests/test_rfp.py +++ b/scripts/west_commands/tests/test_rfp.py @@ -95,7 +95,7 @@ def require_patch(program): - assert program in ['rfp'] + assert program in ['rfp', 'rfp-cli', TEST_RFP_USR_LOCAL_RFP_CLI] os_path_isfile = os.path.isfile @@ -109,7 +109,8 @@ def os_path_isfile_patch(filename): @patch('runners.core.ZephyrBinaryRunner.require', side_effect=require_patch) @patch('runners.core.ZephyrBinaryRunner.check_call') -def test_rfp_init(cc, req, runner_config, tmpdir): +@patch('runners.rfp.RfpBinaryRunner.default_rfp') +def test_rfp_init(dr, cc, req, runner_config, tmpdir): """ Test commands using a runner created by constructor. @@ -129,7 +130,8 @@ def test_rfp_init(cc, req, runner_config, tmpdir): @patch('runners.core.ZephyrBinaryRunner.require', side_effect=require_patch) @patch('runners.core.ZephyrBinaryRunner.check_call') -def test_rfp_create(cc, req, runner_config, tmpdir): +@patch('runners.rfp.RfpBinaryRunner.default_rfp') +def test_rfp_create(dr, cc, req, runner_config, tmpdir): """ Test commands using a runner created from command line parameters. @@ -154,7 +156,8 @@ def test_rfp_create(cc, req, runner_config, tmpdir): @patch('runners.core.ZephyrBinaryRunner.require', side_effect=require_patch) @patch('runners.core.ZephyrBinaryRunner.check_call') -def test_rfp_create_with_speed(cc, req, runner_config, tmpdir): +@patch('runners.rfp.RfpBinaryRunner.default_rfp') +def test_rfp_create_with_speed(dr, cc, req, runner_config, tmpdir): """ Test commands using a runner created from command line parameters. @@ -185,7 +188,8 @@ def test_rfp_create_with_speed(cc, req, runner_config, tmpdir): @patch('runners.core.ZephyrBinaryRunner.require', side_effect=require_patch) @patch('runners.core.ZephyrBinaryRunner.check_call') -def test_rfp_create_with_erase(cc, req, runner_config, tmpdir): +@patch('runners.rfp.RfpBinaryRunner.default_rfp') +def test_rfp_create_with_erase(dr, cc, req, runner_config, tmpdir): """ Test commands using a runner created from command line parameters. @@ -207,7 +211,8 @@ def test_rfp_create_with_erase(cc, req, runner_config, tmpdir): @patch('runners.core.ZephyrBinaryRunner.require', side_effect=require_patch) @patch('runners.core.ZephyrBinaryRunner.check_call') -def test_rfp_create_with_verify(cc, req, runner_config, tmpdir): +@patch('runners.rfp.RfpBinaryRunner.default_rfp') +def test_rfp_create_with_verify(dr, cc, req, runner_config, tmpdir): """ Test commands using a runner created from command line parameters. @@ -229,7 +234,8 @@ def test_rfp_create_with_verify(cc, req, runner_config, tmpdir): @patch('runners.core.ZephyrBinaryRunner.require', side_effect=require_patch) @patch('runners.core.ZephyrBinaryRunner.check_call') -def test_rfp_create_with_rfp_cli(cc, req, runner_config, tmpdir): +@patch('runners.rfp.RfpBinaryRunner.default_rfp') +def test_rfp_create_with_rfp_cli(dr, cc, req, runner_config, tmpdir): """ Test commands using a runner created from command line parameters. From ab5e564daf86e9141bbbd9933a07b92fbb001c67 Mon Sep 17 00:00:00 2001 From: Phi Tran Date: Fri, 9 May 2025 11:08:54 +0700 Subject: [PATCH 03/10] arch: update fixed vectors for config HOCO frequency. Add macro to update fixed vectors to configure Hoco frequency via the register OFS1. Signed-off-by: Phi Tran --- arch/rx/core/vects.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/arch/rx/core/vects.c b/arch/rx/core/vects.c index 95e571e7b1fa..6835aeb86801 100644 --- a/arch/rx/core/vects.c +++ b/arch/rx/core/vects.c @@ -8,6 +8,7 @@ #include #include #include +#include typedef void (*fp)(void); extern void _start(void); @@ -24,6 +25,14 @@ extern void z_rx_irq_exit(void); #define __ISR__ __attribute__((interrupt, naked)) +#define SET_OFS1_HOCO_BITS(reg, freq) \ + ((reg) & ~(0b11 << 12)) | ((((freq) == 24000000 ? 0b10 \ + : (freq) == 32000000 ? 0b11 \ + : (freq) == 48000000 ? 0b01 \ + : (freq) == 64000000 ? 0b00 \ + : 0b11) \ + << 12)) + static ALWAYS_INLINE void REGISTER_SAVE(void) { __asm volatile( @@ -421,7 +430,9 @@ const void *FixedVectors[] FVECT_SECT = { /* Reserved for OFSM */ (fp)0xFFFFFFFF, (fp)0xFFFFFFFF, - (fp)0xFFFFFFFF, + (fp)(SET_OFS1_HOCO_BITS( + 0xFFFFFFFF, + (RX_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(hoco), clock_frequency, 32000000)))), (fp)0xFFFFFFFF, /* Reserved area */ (fp)0xFFFFFFFF, From f90ac3bb12e29fcda5c281e8a0bb9da430cd696e Mon Sep 17 00:00:00 2001 From: Hau Ho Date: Wed, 12 Mar 2025 10:11:24 +0700 Subject: [PATCH 04/10] soc: renesas: rx: Initial support for RX261 SOC This commit to initial support for RX261 SOC. Signed-off-by: Hau Ho Signed-off-by: Phi Tran --- soc/renesas/rx/rx261/CMakeLists.txt | 12 +++++++ soc/renesas/rx/rx261/Kconfig | 10 ++++++ soc/renesas/rx/rx261/Kconfig.defconfig | 23 ++++++++++++ soc/renesas/rx/rx261/Kconfig.soc | 20 +++++++++++ soc/renesas/rx/rx261/ofsm.c | 37 ++++++++++++++++++++ soc/renesas/rx/rx261/ofsm.ld | 16 +++++++++ soc/renesas/rx/rx261/soc.c | 48 ++++++++++++++++++++++++++ soc/renesas/rx/rx261/soc.h | 17 +++++++++ soc/renesas/rx/soc.yml | 3 ++ 9 files changed, 186 insertions(+) create mode 100644 soc/renesas/rx/rx261/CMakeLists.txt create mode 100644 soc/renesas/rx/rx261/Kconfig create mode 100644 soc/renesas/rx/rx261/Kconfig.defconfig create mode 100644 soc/renesas/rx/rx261/Kconfig.soc create mode 100644 soc/renesas/rx/rx261/ofsm.c create mode 100644 soc/renesas/rx/rx261/ofsm.ld create mode 100644 soc/renesas/rx/rx261/soc.c create mode 100644 soc/renesas/rx/rx261/soc.h diff --git a/soc/renesas/rx/rx261/CMakeLists.txt b/soc/renesas/rx/rx261/CMakeLists.txt new file mode 100644 index 000000000000..278090303888 --- /dev/null +++ b/soc/renesas/rx/rx261/CMakeLists.txt @@ -0,0 +1,12 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) + +zephyr_sources( + soc.c +) + +zephyr_linker_sources(SECTIONS ofsm.ld) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/rx/linker.ld CACHE INTERNAL "") diff --git a/soc/renesas/rx/rx261/Kconfig b/soc/renesas/rx/rx261/Kconfig new file mode 100644 index 000000000000..5add6ce4aac6 --- /dev/null +++ b/soc/renesas/rx/rx261/Kconfig @@ -0,0 +1,10 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_RX261 + select RX + select CPU_RXV3 + select XIP + select CLOCK_CONTROL_RENESAS_RX_CGC if CLOCK_CONTROL + select HAS_RENESAS_RX_RDP + select CLOCK_CONTROL diff --git a/soc/renesas/rx/rx261/Kconfig.defconfig b/soc/renesas/rx/rx261/Kconfig.defconfig new file mode 100644 index 000000000000..5851fe9fc574 --- /dev/null +++ b/soc/renesas/rx/rx261/Kconfig.defconfig @@ -0,0 +1,23 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_RX261 + +DT_CMT_PATH := $(dt_nodelabel_path,cmt) + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default $(dt_node_int_prop_int,$(DT_CMT_PATH),clock-frequency) + +# SYS_CLOCK_TICKS_PER_SEC is set to 100 if PCLKB is 48MHz or less. +# (PCLKB = SYS_CLOCK_HW_CYCLES_PER_SEC * 8) +config SYS_CLOCK_TICKS_PER_SEC + default 100 if SYS_CLOCK_HW_CYCLES_PER_SEC <= 6000000 + default 1000 + +config INITIALIZATION_STACK_SIZE + default 512 + +config BUILD_OUTPUT_HEX + default y + +endif # SOC_SERIES_RX261 diff --git a/soc/renesas/rx/rx261/Kconfig.soc b/soc/renesas/rx/rx261/Kconfig.soc new file mode 100644 index 000000000000..ce4ff62bee17 --- /dev/null +++ b/soc/renesas/rx/rx261/Kconfig.soc @@ -0,0 +1,20 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_RX261 + bool + select SOC_FAMILY_RENESAS_RX + help + Renesas RX261 series + +config SOC_R5F52618BGFP + bool + select SOC_SERIES_RX261 + help + SOC_R5F52618BGFP + +config SOC_SERIES + default "rx261" if SOC_SERIES_RX261 + +config SOC + default "r5f52618bgfp" if SOC_R5F52618BGFP diff --git a/soc/renesas/rx/rx261/ofsm.c b/soc/renesas/rx/rx261/ofsm.c new file mode 100644 index 000000000000..430b4c3f616a --- /dev/null +++ b/soc/renesas/rx/rx261/ofsm.c @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2021 KT-Elektronik, Klaucke und Partner GmbH + * Copyright (c) 2025 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + * + * + * Option-Setting Memory for the RX. This region of memory (located in flash) + * determines the state of the MCU after reset and can not be changed on runtime + * + * All registers are set to 0xffffffff by default, which are "safe" settings. + * Please refer to the Renesas RX Group User's Manual before changing any of + * the values as some changes can be permanent or lock access to the device. + * + * Address range: 0xFFFFFF80 to 0xFFFFFF8F (16 Bytes) + */ + +#define __OFS_MDE __attribute__((section(".ofs_mde"))) +#define __OFS0 __attribute__((section(".ofs0"))) +#define __OFS1 __attribute__((section(".ofs1"))) + +/* Endian Select Register (MDE) + * + * b2 to b0: endian select between (0 0 0) for big endian and (1 1 1) for little + * endian. Set this according to __BYTE_ORDER__ (cf. include\toolchain\gcc.h) + * + * b6-b4 (Bank Mode Select) indicate whether the flash is operated in + * Dual mode (0 0 0) or Linear mode (1 1 1). + * + * all other bits are reserved and have to be set to 1 + */ +const unsigned long __OFS_MDE __MDEreg = 0xffffffffU; /* little */ + +/* Option Function Select Register 0 (OFS0) */ +const unsigned long __OFS0 __OFS0reg = 0xffffffffU; + +/* Option Function Select Register 1 (OFS1) */ +const unsigned long __OFS1 __OFS1reg = 0xffffffffU; diff --git a/soc/renesas/rx/rx261/ofsm.ld b/soc/renesas/rx/rx261/ofsm.ld new file mode 100644 index 000000000000..86f2fcf81789 --- /dev/null +++ b/soc/renesas/rx/rx261/ofsm.ld @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +SECTION_PROLOGUE(.ofsm,,) +{ + __OFSM_START = .; + KEEP(*(.ofs_mde)) + . = __OFSM_START + 0x8; + KEEP(*(.ofs1)) + . = __OFSM_START + 0xC; + KEEP(*(.ofs0)) + __OFSM_END = .; +} GROUP_LINK_IN(OFSM) = 0xFF diff --git a/soc/renesas/rx/rx261/soc.c b/soc/renesas/rx/rx261/soc.c new file mode 100644 index 000000000000..4a6b7b193e4e --- /dev/null +++ b/soc/renesas/rx/rx261/soc.c @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @brief System/hardware module for RX SOC family + */ + +#include +#include +#include +#include +#include + +#include "platform.h" +#include "r_bsp_cpu.h" + +/** + * @brief Perform basic hardware initialization at boot. + * + * This needs to be run from the very beginning. + * So the init priority has to be 0 (zero). + * + * @return 0 + */ +void soc_early_init_hook(void) +{ +#ifdef CONFIG_HAS_RENESAS_RX_RDP + bsp_ram_initialize(); + bsp_interrupt_open(); + bsp_register_protect_open(); +#if CONFIG_RENESAS_NONE_USED_PORT_INIT == 1 + /* + * This is the function that initializes the unused port. + * Please see datails on this in the "Handling of Unused Pins" section of PORT chapter + * of RX MCU of User's manual. + * And please MUST set "BSP_PACKAGE_PINS" definition to your device of pin type in + * r_bsp_config.h Otherwise, the port may output without intention. + */ + bsp_non_existent_port_init(); + +#endif /* CONFIG_RENESAS_NONE_USED_PORT_INIT */ +#else + renesas_rx_register_protect_open(); +#endif /* CONFIG_HAS_RENESAS_RX_RDP */ +} diff --git a/soc/renesas/rx/rx261/soc.h b/soc/renesas/rx/rx261/soc.h new file mode 100644 index 000000000000..b6bfd9344d9e --- /dev/null +++ b/soc/renesas/rx/rx261/soc.h @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @brief SOC header file for Renesas RX SOC series + */ + +#ifndef _SOC_H_ +#define _SOC_H_ + +#include "reg_protection.h" +#include + +#endif /* _SOC_H_ */ diff --git a/soc/renesas/rx/soc.yml b/soc/renesas/rx/soc.yml index 5d28644afd65..754c783f95ce 100644 --- a/soc/renesas/rx/soc.yml +++ b/soc/renesas/rx/soc.yml @@ -7,3 +7,6 @@ family: - name: rx62n socs: - name: r5f562n8 + - name: rx261 + socs: + - name: r5f52618bgfp From ffc5e1bbaca7444af805c5a0dedbebbb8cd0815b Mon Sep 17 00:00:00 2001 From: Hau Ho Date: Wed, 12 Mar 2025 13:49:07 +0700 Subject: [PATCH 05/10] dts: renesas: initial support dts SoC layer on RX261. This commit to initial support dts SoC layer on RX261 Signed-off-by: Hau Ho Signed-off-by: Phi Tran --- dts/rx/renesas/r5f52618bgfp.dtsi | 235 +++++++++++++++ dts/rx/renesas/rx261-common.dtsi | 496 +++++++++++++++++++++++++++++++ 2 files changed, 731 insertions(+) create mode 100644 dts/rx/renesas/r5f52618bgfp.dtsi create mode 100644 dts/rx/renesas/rx261-common.dtsi diff --git a/dts/rx/renesas/r5f52618bgfp.dtsi b/dts/rx/renesas/r5f52618bgfp.dtsi new file mode 100644 index 000000000000..0f10f965af27 --- /dev/null +++ b/dts/rx/renesas/r5f52618bgfp.dtsi @@ -0,0 +1,235 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +/ { + clocks: clocks { + #address-cells = <1>; + #size-cells = <1>; + + xtal: clock-main-osc { + compatible = "renesas,rx-cgc-root-clock"; + clock-frequency = ; + mosel = <0>; + stabilization-time = <4>; + #clock-cells = <0>; + status = "disabled"; + }; + + hoco: clock-hoco { + compatible = "renesas,rx-cgc-root-clock"; + clock-frequency = ; + #clock-cells = <0>; + status = "okay"; + }; + + loco: clock-loco { + compatible = "renesas,rx-cgc-root-clock"; + clock-frequency = ; + #clock-cells = <0>; + status = "okay"; + }; + + subclk: clock-subclk { + compatible = "renesas,rx-cgc-root-clock"; + clock-frequency = <32768>; + drive-capacity = <0>; + mosel = <0>; + #clock-cells = <0>; + status = "disabled"; + }; + + iwdtlsclk: clock-iwdt-low-speed { + compatible = "renesas,rx-cgc-root-clock"; + clock-frequency = <15000>; + #clock-cells = <0>; + status = "disabled"; + }; + + pll: pll { + compatible = "renesas,rx-cgc-pll"; + #clock-cells = <0>; + div = <1>; + clocks = <&xtal>; + mul = ; + status = "disabled"; + }; + + pll2: pll2 { + compatible = "renesas,rx-cgc-pll"; + #clock-cells = <0>; + div = <1>; + clocks = <&xtal>; + mul = ; + status = "disabled"; + }; + + pclkblock: pclkblock@80010 { + compatible = "renesas,rx-cgc-pclk-block"; + reg = <0x00080010 4>, + <0x00080014 4>, + <0x00080018 4>, + <0x0008001C 4>; + reg-names = "MSTPA", "MSTPB", "MSTPC", "MSTPD"; + #clock-cells = <0>; + clocks = <&pll>; + status = "okay"; + + fclk: fclk { + compatible = "renesas,rx-cgc-pclk"; + div = <1>; + #clock-cells = <2>; + status = "okay"; + }; + + iclk: iclk { + compatible = "renesas,rx-cgc-pclk"; + div = <1>; + #clock-cells = <2>; + status = "okay"; + }; + + pclka: pclka { + compatible = "renesas,rx-cgc-pclk"; + div = <1>; + #clock-cells = <2>; + status = "okay"; + }; + + pclkb: pclkb { + compatible = "renesas,rx-cgc-pclk"; + div = <2>; + #clock-cells = <2>; + status = "okay"; + }; + + pclkd: pclkd { + compatible = "renesas,rx-cgc-pclk"; + div = <1>; + #clock-cells = <2>; + status = "okay"; + }; + }; + + canfdclk: canfdclk { + compatible = "renesas,rx-cgc-pclk"; + clocks = <&xtal>; + div = <2>; + #clock-cells = <2>; + status = "disabled"; + }; + + clkout: clkout { + compatible = "renesas,rx-cgc-pclk"; + clocks = <&xtal>; + div = <8>; + #clock-cells = <2>; + status = "disabled"; + }; + + uclk: uclk { + compatible = "renesas,rx-cgc-pclk"; + clocks = <&pll2>; + #clock-cells = <2>; + status = "disabled"; + }; + + lptclk: lptclk { + compatible = "renesas,rx-cgc-pclk"; + clocks = <&subclk>; + #clock-cells = <2>; + status = "disabled"; + }; + + canfdmclk: canfdmclk { + compatible = "renesas,rx-cgc-pclk"; + clocks = <&xtal>; + #clock-cells = <2>; + status = "disabled"; + }; + + cacmclk: cacmclk { + compatible = "renesas,rx-cgc-pclk"; + clocks = <&xtal>; + #clock-cells = <2>; + status = "disabled"; + }; + + cachclk: cachclk { + compatible = "renesas,rx-cgc-pclk"; + clocks = <&hoco>; + #clock-cells = <2>; + status = "disabled"; + }; + + cacsclk: cacsclk { + compatible = "renesas,rx-cgc-pclk"; + clocks = <&subclk>; + #clock-cells = <2>; + status = "disabled"; + }; + + remsclk: remsclk { + compatible = "renesas,rx-cgc-pclk"; + clocks = <&subclk>; + #clock-cells = <2>; + status = "disabled"; + }; + + rtcsclk: rtcsclk { + compatible = "renesas,rx-cgc-pclk"; + clocks = <&subclk>; + #clock-cells = <2>; + status = "disabled"; + }; + + caclclk: caclclk { + compatible = "renesas,rx-cgc-pclk"; + clocks = <&loco>; + #clock-cells = <2>; + status = "disabled"; + }; + + iwdtclk: iwdtclk { + compatible = "renesas,rx-cgc-pclk"; + clocks = <&iwdtlsclk>; + #clock-cells = <2>; + status = "disabled"; + }; + }; + + soc { + sram0: memory@0 { + device_type = "memory"; + compatible = "mmio-sram"; + reg = <0x0 DT_SIZE_K(128)>; + }; + + fcu: flash-controller@7e0000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "renesas,rx-flash.yaml"; + reg = <0x007e0000 0x1000>; + code_flash: flash@fff80000 { + compatible = "renesas,rx-nv-flash.yaml"; + reg = <0xfff80000 DT_SIZE_K(512)>; + write-block-size = <4>; + erase-block-size = <1024>; + }; + + data_flash: flash@100000 { + compatible = "renesas,rx-nv-flash.yaml"; + erased_undefined; + reg = <0x00100000 DT_SIZE_K(8)>; + write_block_size = <1>; + erase-block-size = <1024>; + }; + }; + }; +}; diff --git a/dts/rx/renesas/rx261-common.dtsi b/dts/rx/renesas/rx261-common.dtsi new file mode 100644 index 000000000000..49308688966e --- /dev/null +++ b/dts/rx/renesas/rx261-common.dtsi @@ -0,0 +1,496 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* + * common device tree elements of all (currently supported) RX MCUs + */ + +#include +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "renesas,rx"; + device_type = "cpu"; + reg = <0>; + status = "okay"; + }; + }; + + icu: interrupt-controller@87000 { + #interrupt-cells = <2>; + compatible = "renesas,rx-icu"; + interrupt-controller; + reg = <0x0087000 0xff>, + <0x0087200 0x1f>, + <0x0087300 0xff>, + <0x00872f0 0x02>, + <0x0087500 0x0f>, + <0x0087510 0x01>, + <0x0087514 0x01>; + reg-names = "IR", "IER", "IPR", "FIR","IRQCR","IRQFLTE","IRQFLTC0"; + }; /* icu */ + + soc { + #address-cells = <1>; + #size-cells = <1>; + device_type = "soc"; + compatible = "simple-bus"; + interrupt-parent = <&icu>; + + pinctrl: pin-controller@8c11f { + compatible = "renesas,rx-pinctrl"; + reg = <0x0008C11F 0xb8>; + status = "okay"; + }; + + pinmux0: pinmux@8c143 { + compatible = "renesas,rx-pinmux"; + #pinmux-cells = <2>; + reg = <0x00008c143 0x8>; /* P0nPFS */ + status = "okay"; + }; + + pinmux1: pinmux@8c14a { + compatible = "renesas,rx-pinmux"; + #pinmux-cells = <2>; + reg = <0x00008c14a 0x8>; /* P1nPFS */ + status = "okay"; + }; + + pinmux2: pinmux@8c150 { + compatible = "renesas,rx-pinmux"; + #pinmux-cells = <2>; + reg = <0x00008c150 0x8>; /* P2nPFS */ + status = "okay"; + }; + + pinmux3: pinmux@8c158 { + compatible = "renesas,rx-pinmux"; + #pinmux-cells = <2>; + reg = <0x00008c158 0x8>; /* P3nPFS */ + status = "okay"; + }; + + pinmux4: pinmux@8c160 { + compatible = "renesas,rx-pinmux"; + #pinmux-cells = <2>; + reg = <0x00008c160 0x8>; /* P4nPFS */ + status = "okay"; + }; + + pinmux5: pinmux@8c169 { + compatible = "renesas,rx-pinmux"; + #pinmux-cells = <2>; + reg = <0x00008c169 0x8>; /* P5nPFS */ + status = "okay"; + }; + + pinmuxa: pinmux@8c190 { + compatible = "renesas,rx-pinmux"; + #pinmux-cells = <2>; + reg = <0x00008c190 0x8>; /* PAnPFS */ + status = "okay"; + }; + + pinmuxb: pinmux@8c198 { + compatible = "renesas,rx-pinmux"; + #pinmux-cells = <2>; + reg = <0x00008c198 0x8>; /* PBnPFS */ + status = "okay"; + }; + + pinmuxc: pinmux@8c1a0 { + compatible = "renesas,rx-pinmux"; + #pinmux-cells = <2>; + reg = <0x00008c1a0 0x8>; /* PCnPFS */ + status = "okay"; + }; + + pinmuxd: pinmux@8c1a8 { + compatible = "renesas,rx-pinmux"; + #pinmux-cells = <2>; + reg = <0x00008c1a8 0x8>; /* PDnPFS */ + status = "okay"; + }; + + pinmuxe: pinmux@8c1b0 { + compatible = "renesas,rx-pinmux"; + #pinmux-cells = <2>; + reg = <0x00008c1b0 0x8>; /* PEnPFS */ + status = "okay"; + }; + + pinmuxh: pinmux@8c1c8 { + compatible = "renesas,rx-pinmux"; + #pinmux-cells = <2>; + reg = <0x00008c1c8 0x8>; /* PHnPFS */ + status = "okay"; + }; + + pinmuxj: pinmux@8c1d1 { + compatible = "renesas,rx-pinmux"; + #pinmux-cells = <2>; + reg = <0x00008c1d1 0x8>; /* PJnPFS */ + status = "okay"; + }; + + ioport0: gpio@8c000 { + compatible = "renesas,rx-gpio"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <5>; + port = <0>; + reg = <0x0008C000 0x01>, + <0x0008C020 0x01>, + <0x0008C040 0x01>, + <0x0008C060 0x01>, + <0x0008C0C0 0x01>; + reg-names = "PDR", "PODR", "PIDR", "PMR", "PCR"; + pinmux = <&pinmux0>; + status = "disabled"; + }; + + ioport1: gpio@8c001 { + compatible = "renesas,rx-gpio"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + port = <1>; + reg = <0x0008C001 0x01>, + <0x0008C021 0x01>, + <0x0008C041 0x01>, + <0x0008C061 0x01>, + <0x0008C082 0x01>, + <0x0008C083 0x01>, + <0x0008C0C1 0x01>; + reg-names = "PDR", "PODR", "PIDR", "PMR", "ODR0", "ODR1", "PCR"; + pinmux = <&pinmux1>; + status = "disabled"; + }; + + ioport2: gpio@8c002 { + compatible = "renesas,rx-gpio"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + port = <2>; + reg = <0x0008C002 0x01>, + <0x0008C022 0x01>, + <0x0008C042 0x01>, + <0x0008C062 0x01>, + <0x0008C084 0x01>, + <0x0008C085 0x01>, + <0x0008C0C2 0x01>; + reg-names = "PDR", "PODR", "PIDR", "PMR", "ODR0", "ODR1", "PCR"; + pinmux = <&pinmux2>; + status = "disabled"; + }; + + ioport3: gpio@8c003 { + compatible = "renesas,rx-gpio"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + port = <3>; + reg = <0x0008C003 0x01>, + <0x0008C023 0x01>, + <0x0008C043 0x01>, + <0x0008C063 0x01>, + <0x0008C086 0x01>, + <0x0008C087 0x01>, + <0x0008C0C3 0x01>; + reg-names = "PDR", "PODR", "PIDR", "PMR", "ODR0", "ODR1", "PCR"; + pinmux = <&pinmux3>; + status = "disabled"; + }; + + ioport4: gpio@8c004 { + compatible = "renesas,rx-gpio"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + port = <4>; + reg = <0x0008C004 0x01>, + <0x0008C024 0x01>, + <0x0008C044 0x01>, + <0x0008C064 0x01>, + <0x0008C0C4 0x01>; + reg-names = "PDR", "PODR", "PIDR", "PMR", "PCR"; + pinmux = <&pinmux4>; + status = "disabled"; + }; + + ioport5: gpio@8c005 { + compatible = "renesas,rx-gpio"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + port = <5>; + reg = <0x0008C005 0x01>, + <0x0008C025 0x01>, + <0x0008C045 0x01>, + <0x0008C065 0x01>, + <0x0008C08A 0x01>, + <0x0008C08B 0x01>, + <0x0008C0C5 0x01>; + reg-names = "PDR", "PODR", "PIDR", "PMR", "ODR0", "ODR1", "PCR"; + pinmux = <&pinmux5>; + status = "disabled"; + }; + + ioporta: gpio@8c00a { + compatible = "renesas,rx-gpio"; + gpio-controller; + #gpio-cells = <0x2>; + ngpios = <8>; + port = <10>; + reg = <0x0008C00A 0x01>, + <0x0008C02A 0x01>, + <0x0008C04A 0x01>, + <0x0008C06A 0x01>, + <0x0008C094 0x01>, + <0x0008C095 0x01>, + <0x0008C0CA 0x01>; + reg-names = "PDR", "PODR", "PIDR", "PMR", "ODR0", "ODR1", "PCR"; + pinmux = <&pinmuxa>; + status = "disabled"; + }; + + ioportb: gpio@8c00b { + compatible = "renesas,rx-gpio"; + gpio-controller; + #gpio-cells = <0x2>; + ngpios = <8>; + port = <11>; + reg = <0x0008C00B 0x01>, + <0x0008C02B 0x01>, + <0x0008C04B 0x01>, + <0x0008C06B 0x01>, + <0x0008C096 0x01>, + <0x0008C097 0x01>, + <0x0008C0CB 0x01>; + reg-names = "PDR", "PODR", "PIDR", "PMR", "ODR0", "ODR1", "PCR"; + pinmux = <&pinmuxb>; + status = "disabled"; + }; + + ioportc: gpio@8c00c { + compatible = "renesas,rx-gpio"; + gpio-controller; + #gpio-cells = <0x2>; + ngpios = <8>; + port = <12>; + reg = <0x0008C00C 0x01>, + <0x0008C02C 0x01>, + <0x0008C04C 0x01>, + <0x0008C06C 0x01>, + <0x0008C098 0x01>, + <0x0008C099 0x01>, + <0x0008C0CC 0x01>; + reg-names = "PDR", "PODR", "PIDR", "PMR", "ODR0", "ODR1", "PCR"; + pinmux = <&pinmuxc>; + status = "disabled"; + }; + + ioportd: gpio@8c00d { + compatible = "renesas,rx-gpio"; + gpio-controller; + #gpio-cells = <0x2>; + ngpios = <8>; + port = <13>; + reg = <0x0008C00D 0x01>, + <0x0008C02D 0x01>, + <0x0008C04D 0x01>, + <0x0008C06D 0x01>, + <0x0008C09A 0x01>, + <0x0008C0CD 0x01>; + reg-names = "PDR", "PODR", "PIDR", "PMR", "ODR0", "PCR"; + pinmux = <&pinmuxd>; + status = "okay"; + }; + + ioporte: gpio@8c00e { + compatible = "renesas,rx-gpio"; + gpio-controller; + #gpio-cells = <0x2>; + ngpios = <8>; + port = <14>; + reg = <0x0008C00E 0x01>, + <0x0008C02E 0x01>, + <0x0008C04E 0x01>, + <0x0008C06E 0x01>, + <0x0008C09C 0x01>, + <0x0008C0CE 0x01>; + reg-names = "PDR", "PODR", "PIDR", "PMR", "ODR0", "PCR"; + pinmux = <&pinmuxe>; + status = "disabled"; + }; + + ioporth: gpio@8c011 { + compatible = "renesas,rx-gpio"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + port = <17>; + reg = <0x0008C011 0x01>, + <0x0008C031 0x01>, + <0x0008C051 0x01>, + <0x0008C071 0x01>, + <0x0008C0D1 0x01>; + reg-names = "PDR", "PODR", "PIDR", "PMR", "PCR"; + pinmux = <&pinmuxh>; + status = "disabled"; + }; + + ioportj: gpio@8c012 { + compatible = "renesas,rx-gpio"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + port = <18>; + reg = <0x0008C012 0x01>, + <0x0008C032 0x01>, + <0x0008C052 0x01>, + <0x0008C072 0x01>, + <0x0008C0D2 0x01>; + reg-names = "PDR", "PODR", "PIDR", "PMR", "PCR"; + pinmux = <&pinmuxj>; + status = "disabled"; + }; + + sci1: sci1@8a020 { + compatible = "renesas,rx-sci"; + interrupts = <219 1>, <220 1>, <221 1>, <218 1>; + interrupt-names = "rxi", "txi", "tei", "eri"; + reg = <0x8A020 0x20>; + clocks = <&pclkb MSTPB 30>; + status = "disabled"; + channel = <1>; + + uart { + compatible = "renesas,rx-uart-sci"; + status = "disabled"; + }; + }; + + sci5: sci5@8a0a0 { + compatible = "renesas,rx-sci"; + interrupts = <223 1>, <224 1>, <225 1>, <222 1>; + interrupt-names = "rxi", "txi", "tei", "eri"; + reg = <0x8A0A0 0x20>; + clocks = <&pclkb MSTPB 26>; + status = "disabled"; + channel = <5>; + + uart { + compatible = "renesas,rx-uart-sci"; + status = "disabled"; + }; + }; + + sci6: sci6@8a0c0 { + compatible = "renesas,rx-sci"; + interrupts = <227 1>, <228 1>, <229 1>, <226 1>; + interrupt-names = "rxi", "txi", "tei", "eri"; + reg = <0x8A0C0 0x20>; + clocks = <&pclkb MSTPB 25>; + status = "disabled"; + channel = <6>; + + uart { + compatible = "renesas,rx-uart-sci"; + status = "disabled"; + }; + }; + + sci12: sci12@8b300 { + compatible = "renesas,rx-sci"; + interrupts = <239 1>, <240 1>, <241 1>, <238 1>; + interrupt-names = "rxi", "txi", "tei", "eri"; + reg = <0x8B300 0x20>; + clocks = <&pclkb MSTPB 4>; + status = "disabled"; + channel = <12>; + + uart { + compatible = "renesas,rx-uart-sci"; + status = "disabled"; + }; + }; + + cmt: timer@88000 { + compatible = "renesas,rx-timer-cmt-start-control"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x00088000 0x02>; + clocks = <&pclkb MSTPA 15>; + reg-names = "CMSTR0"; + status = "okay"; + + cmt0: timer@88002 { + compatible = "renesas,rx-timer-cmt"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x00088002 0x02>, + <0x00088004 0x02>, + <0x00088006 0x02>; + reg-names = "CMCR", "CMCNT", "CMCOR"; + interrupts = <28 1>; + interrupt-names = "cmi"; + status = "okay"; + }; + + cmt1: timer@88008 { + compatible = "renesas,rx-timer-cmt"; + reg = <0x00088008 0x02>, + <0x0008800A 0x02>, + <0x0008800C 0x02>; + reg-names = "CMCR", "CMCNT", "CMCOR"; + interrupts = <29 1>; + interrupt-names = "cmi"; + status = "disabled"; + }; + + cmt2: timer@88012 { + compatible = "renesas,rx-timer-cmt"; + reg = <0x00088012 0x02>, + <0x00088014 0x02>, + <0x00088016 0x02>; + reg-names = "CMCR", "CMCNT", "CMCOR"; + interrupts = <30 1>; + interrupt-names = "cmi"; + status = "disabled"; + }; + + cmt3: timer@88018 { + compatible = "renesas,rx-timer-cmt"; + reg = <0x00088018 0x02>, + <0x0008801A 0x02>, + <0x0008801C 0x02>; + reg-names = "CMCR", "CMCNT", "CMCOR"; + interrupts = <31 1>; + interrupt-names = "cmi"; + status = "disabled"; + }; + + }; + + ofsm: ofsm@ffffff80 { + compatible = "zephyr,memory-region"; + reg = <0xFFFFFF80 0x0F>; + zephyr,memory-region = "OFSM"; + status = "okay"; + }; + }; +}; From c6bd9ba3a923a967b0ef0b5573c6fc0423f3af2f Mon Sep 17 00:00:00 2001 From: Phi Tran Date: Tue, 6 May 2025 13:59:23 +0700 Subject: [PATCH 06/10] drivers: clock control: Add support clock control for RX261 Add support clock control for RX261 Signed-off-by: Phi Tran --- dts/bindings/clock/renesas,rx-cgc-root-clock.yaml | 8 +++++++- include/zephyr/drivers/clock_control/renesas_rx_cgc.h | 10 ++++++++++ include/zephyr/dt-bindings/clock/rx_clock.h | 10 ++++++++++ 3 files changed, 27 insertions(+), 1 deletion(-) diff --git a/dts/bindings/clock/renesas,rx-cgc-root-clock.yaml b/dts/bindings/clock/renesas,rx-cgc-root-clock.yaml index e46d367d1017..447e8bb1f15b 100644 --- a/dts/bindings/clock/renesas,rx-cgc-root-clock.yaml +++ b/dts/bindings/clock/renesas,rx-cgc-root-clock.yaml @@ -43,7 +43,13 @@ properties: enum: - 0 - 1 + - 2 + - 3 + - 4 description: | Drive Capacity Control (for Sub-Clock Oscillator only) 0: Drive capacity for standard CL. - 1: Drive capacity for low CL. + 1: Drive capacity for low CL. (in case of rx261, not choose this) + 2: High-drive output for the low CL. + 3: Middle-drive output for the low CL + 4: Low-drive output for the low CL diff --git a/include/zephyr/drivers/clock_control/renesas_rx_cgc.h b/include/zephyr/drivers/clock_control/renesas_rx_cgc.h index 19f196b6d65d..e513f374e82c 100644 --- a/include/zephyr/drivers/clock_control/renesas_rx_cgc.h +++ b/include/zephyr/drivers/clock_control/renesas_rx_cgc.h @@ -17,6 +17,16 @@ (UTIL_CAT(RX_CLOCKS_SOURCE_, DT_NODE_FULL_NAME_UPPER_TOKEN(node_id))), \ (RX_CLOCKS_CLOCK_DISABLED)) +#define RX_IF_CLK_SRC(node_id)\ + COND_CODE_1(DT_NODE_HAS_STATUS(node_id, okay),\ + (UTIL_CAT(RX_IF_CLOCKS_SOURCE_, DT_NODE_FULL_NAME_UPPER_TOKEN(node_id))),\ + (RX_CLOCKS_CLOCK_DISABLED)) + +#define RX_LPT_CLK_SRC(node_id)\ + COND_CODE_1(DT_NODE_HAS_STATUS(node_id, okay),\ + (UTIL_CAT(RX_LPT_CLOCKS_SOURCE_, DT_NODE_FULL_NAME_UPPER_TOKEN(node_id))),\ + (RX_LPT_CLOCKS_NON_USE)) + struct clock_control_rx_pclk_cfg { const struct device *clock_src_dev; uint32_t clk_div; diff --git a/include/zephyr/dt-bindings/clock/rx_clock.h b/include/zephyr/dt-bindings/clock/rx_clock.h index cab40d575fd5..90b63c98b92a 100644 --- a/include/zephyr/dt-bindings/clock/rx_clock.h +++ b/include/zephyr/dt-bindings/clock/rx_clock.h @@ -14,6 +14,16 @@ #define RX_CLOCKS_SOURCE_PLL 4 #define RX_CLOCKS_SOURCE_CLOCK_DISABLE 0xff +#define RX_IF_CLOCKS_SOURCE_CLOCK_HOCO 0 +#define RX_IF_CLOCKS_SOURCE_CLOCK_LOCO 2 +#define RX_IF_CLOCKS_SOURCE_PLL 5 +#define RX_IF_CLOCKS_SOURCE_PLL2 6 + +#define RX_LPT_CLOCKS_SOURCE_CLOCK_SUBCLOCK 0 +#define RX_LPT_CLOCKS_SOURCE_CLOCK_IWDT_LOW_SPEED 1 +#define RX_LPT_CLOCKS_NON_USE 2 +#define RX_LPT_CLOCKS_SOURCE_CLOCK_LOCO 3 + #define RX_PLL_MUL_4 7 #define RX_PLL_MUL_4_5 8 #define RX_PLL_MUL_5 9 From 9ab1e4c6502a0072bd4d54147fb9acb80b9ce17f Mon Sep 17 00:00:00 2001 From: Phi Tran Date: Tue, 6 May 2025 14:01:52 +0700 Subject: [PATCH 07/10] drivers: gpio: Update gpio and pinctrl driver for support RX261 Update gpio driver and pinctrl driver for support RX261 Signed-off-by: Phi Tran --- drivers/pinctrl/renesas/rx/pinctrl_renesas_rx.c | 7 ++++++- .../zephyr/dt-bindings/pinctrl/renesas/pinctrl-rx.h | 12 ++++++++---- 2 files changed, 14 insertions(+), 5 deletions(-) diff --git a/drivers/pinctrl/renesas/rx/pinctrl_renesas_rx.c b/drivers/pinctrl/renesas/rx/pinctrl_renesas_rx.c index 20b7b09cd0a3..9a738215dc90 100644 --- a/drivers/pinctrl/renesas/rx/pinctrl_renesas_rx.c +++ b/drivers/pinctrl/renesas/rx/pinctrl_renesas_rx.c @@ -16,7 +16,9 @@ extern const uint8_t g_gpio_open_drain_n_support[]; extern const uint8_t g_gpio_pull_up_support[]; +#ifndef CONFIG_SOC_SERIES_RX261 extern const uint8_t g_gpio_dscr_support[]; +#endif static bool gpio_pin_function_check(uint8_t const *check_array, uint8_t port_number, uint8_t pin_number) @@ -45,6 +47,7 @@ static int pinctrl_configure_pullup(const pinctrl_soc_pin_t *pin, uint32_t value return ret; } +#ifndef CONFIG_SOC_SERIES_RX261 static int pinctrl_configure_dscr(const pinctrl_soc_pin_t *pin, uint32_t value) { gpio_port_pin_t port_pin; @@ -61,6 +64,7 @@ static int pinctrl_configure_dscr(const pinctrl_soc_pin_t *pin, uint32_t value) return ret; } +#endif static int pinctrl_configure_opendrain(const pinctrl_soc_pin_t *pin, uint32_t value) { @@ -133,13 +137,14 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintp if (ret != 0) { return -EINVAL; } - +#ifndef CONFIG_SOC_SERIES_RX261 /* Set drive-strength */ ret = pinctrl_configure_dscr(pin, pin->cfg.drive_strength); if (ret != 0) { return -EINVAL; } +#endif /* Set pin function */ pconfig.analog_enable = pin->cfg.analog_enable; diff --git a/include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-rx.h b/include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-rx.h index 35547c608f6e..e3a5e28f38ff 100644 --- a/include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-rx.h +++ b/include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-rx.h @@ -16,10 +16,14 @@ #define RX_PSEL_MASK 0x1f #define RX_PSEL_POS 9 -#define RX_PSEL_SCI_1 0xA -#define RX_PSEL_SCI_6 0xB -#define RX_PSEL_TMR 0x5 -#define RX_PSEL_POE 0x7 +#define RX_PSEL_RSCI 0xA +#define RX_PSEL_RSCI_TXDB 0xC +#define RX_PSEL_SCI_1 0xA +#define RX_PSEL_SCI_5 0xA +#define RX_PSEL_SCI_6 0xB +#define RX_PSEL_SCI_12 0xC +#define RX_PSEL_TMR 0x5 +#define RX_PSEL_POE 0x7 /* P0nPFS */ #define RX_PSEL_P0nPFS_HIZ 0x0 From 9cf3fbe41039350fc27ec9cce81dca8f624c0654 Mon Sep 17 00:00:00 2001 From: Phi Tran Date: Tue, 6 May 2025 14:22:03 +0700 Subject: [PATCH 08/10] drivers: uart: Update sci uart for support RX261 This commit to update sci uart for support RX261 Signed-off-by: Phi Tran --- drivers/serial/uart_renesas_rx_sci.c | 30 +++++++++++++++------------- 1 file changed, 16 insertions(+), 14 deletions(-) diff --git a/drivers/serial/uart_renesas_rx_sci.c b/drivers/serial/uart_renesas_rx_sci.c index d8ac3b926ee1..ced7b471652c 100644 --- a/drivers/serial/uart_renesas_rx_sci.c +++ b/drivers/serial/uart_renesas_rx_sci.c @@ -14,9 +14,12 @@ #include #include "r_sci_rx_if.h" +#include "iodefine_sci.h" #if CONFIG_SOC_SERIES_RX130 #include "r_sci_rx130_private.h" +#elif CONFIG_SOC_SERIES_RX261 +#include "r_sci_rx261_private.h" #else #error Unknown SOC, not (yet) supported. #endif @@ -68,7 +71,7 @@ struct uart_rx_sci_data { static int uart_rx_sci_poll_in(const struct device *dev, unsigned char *c) { - volatile struct st_sci0 *sci = (struct st_sci0 *)DEV_BASE(dev); + volatile struct st_sci *sci = (struct st_sci *)DEV_BASE(dev); if (IS_ENABLED(CONFIG_UART_ASYNC_API) && sci->SCR.BIT.RIE) { return -EBUSY; @@ -86,7 +89,7 @@ static int uart_rx_sci_poll_in(const struct device *dev, unsigned char *c) static void uart_rx_sci_poll_out(const struct device *dev, unsigned char c) { - volatile struct st_sci0 *sci = (struct st_sci0 *)DEV_BASE(dev); + volatile struct st_sci *sci = (struct st_sci *)DEV_BASE(dev); while (sci->SSR.BIT.TEND == 0U) { } @@ -96,7 +99,7 @@ static void uart_rx_sci_poll_out(const struct device *dev, unsigned char c) static int uart_rx_err_check(const struct device *dev) { - volatile struct st_sci0 *sci = (struct st_sci0 *)DEV_BASE(dev); + volatile struct st_sci *sci = (struct st_sci *)DEV_BASE(dev); const uint32_t status = sci->SSR.BYTE; int errors = 0; @@ -227,7 +230,7 @@ static int uart_rx_config_get(const struct device *dev, struct uart_config *cfg) static int uart_rx_fifo_fill(const struct device *dev, const uint8_t *tx_data, int size) { - volatile struct st_sci0 *sci = (struct st_sci0 *)DEV_BASE(dev); + volatile struct st_sci *sci = (struct st_sci *)DEV_BASE(dev); uint8_t num_tx = 0U; if (size > 0 && sci->SSR.BIT.TDRE) { @@ -240,7 +243,7 @@ static int uart_rx_fifo_fill(const struct device *dev, const uint8_t *tx_data, i static int uart_rx_fifo_read(const struct device *dev, uint8_t *rx_data, const int size) { - volatile struct st_sci0 *sci = (struct st_sci0 *)DEV_BASE(dev); + volatile struct st_sci *sci = (struct st_sci *)DEV_BASE(dev); uint8_t num_rx = 0U; if (size > 0 && sci->SSR.BIT.RDRF) { @@ -254,7 +257,7 @@ static int uart_rx_fifo_read(const struct device *dev, uint8_t *rx_data, const i static void uart_rx_irq_tx_enable(const struct device *dev) { struct uart_rx_sci_data *data = dev->data; - volatile struct st_sci0 *sci = (struct st_sci0 *)DEV_BASE(dev); + volatile struct st_sci *sci = (struct st_sci *)DEV_BASE(dev); sci->SCR.BYTE |= (BIT(R_SCI_SCR_TIE_Pos) | BIT(R_SCI_SCR_TEIE_Pos)); irq_enable(data->tei_irq); @@ -274,7 +277,7 @@ static void uart_rx_irq_tx_enable(const struct device *dev) static void uart_rx_irq_tx_disable(const struct device *dev) { struct uart_rx_sci_data *data = dev->data; - volatile struct st_sci0 *sci = (struct st_sci0 *)DEV_BASE(dev); + volatile struct st_sci *sci = (struct st_sci *)DEV_BASE(dev); sci->SCR.BYTE &= ~(BIT(R_SCI_SCR_TIE_Pos) | BIT(R_SCI_SCR_TEIE_Pos)); irq_disable(data->tei_irq); @@ -282,7 +285,7 @@ static void uart_rx_irq_tx_disable(const struct device *dev) static int uart_rx_irq_tx_ready(const struct device *dev) { - volatile struct st_sci0 *sci = (struct st_sci0 *)DEV_BASE(dev); + volatile struct st_sci *sci = (struct st_sci *)DEV_BASE(dev); return (sci->SCR.BIT.TIE == 1U) && (sci->SSR.BYTE & (BIT(R_SCI_SSR_TDRE_Pos) | BIT(R_SCI_SSR_TEND_Pos))); @@ -290,28 +293,28 @@ static int uart_rx_irq_tx_ready(const struct device *dev) static int uart_rx_irq_tx_complete(const struct device *dev) { - volatile struct st_sci0 *sci = (struct st_sci0 *)DEV_BASE(dev); + volatile struct st_sci *sci = (struct st_sci *)DEV_BASE(dev); return (sci->SCR.BIT.TEIE == 1U) && (sci->SSR.BYTE & BIT(R_SCI_SSR_TEND_Pos)); } static void uart_rx_irq_rx_enable(const struct device *dev) { - volatile struct st_sci0 *sci = (struct st_sci0 *)DEV_BASE(dev); + volatile struct st_sci *sci = (struct st_sci *)DEV_BASE(dev); sci->SCR.BIT.RIE = 1U; } static void uart_rx_irq_rx_disable(const struct device *dev) { - volatile struct st_sci0 *sci = (struct st_sci0 *)DEV_BASE(dev); + volatile struct st_sci *sci = (struct st_sci *)DEV_BASE(dev); sci->SCR.BIT.RIE = 0U; } static int uart_rx_irq_rx_ready(const struct device *dev) { - volatile struct st_sci0 *sci = (struct st_sci0 *)DEV_BASE(dev); + volatile struct st_sci *sci = (struct st_sci *)DEV_BASE(dev); return (sci->SCR.BIT.RIE == 1U) && ((sci->SSR.BYTE & BIT(R_SCI_SSR_RDRF_Pos))); } @@ -332,7 +335,7 @@ static void uart_rx_irq_err_disable(const struct device *dev) static int uart_rx_irq_is_pending(const struct device *dev) { - volatile struct st_sci0 *sci = (struct st_sci0 *)DEV_BASE(dev); + volatile struct st_sci *sci = (struct st_sci *)DEV_BASE(dev); bool tx_pending = false; bool rx_pending = false; @@ -483,7 +486,6 @@ static void uart_rx_sci_eri_isr(const struct device *dev) #define UART_RX_SCI_IRQ_INIT(index) #endif - #define UART_RX_INIT(index) \ PINCTRL_DT_DEFINE(DT_INST_PARENT(index)); \ \ From da4f26f1de3079c0632cc68f3ea7b02ae23bbb40 Mon Sep 17 00:00:00 2001 From: Phi Tran Date: Thu, 8 May 2025 11:49:32 +0700 Subject: [PATCH 09/10] boards: renesas: rx: Initial support for FPB-RX261 board Initial support for board FPB-RX261 Signed-off-by: Phi Tran --- boards/renesas/fpb_rx261/Kconfig.fpb_rx261 | 5 ++ boards/renesas/fpb_rx261/board.cmake | 9 ++ boards/renesas/fpb_rx261/board.yml | 6 ++ .../renesas/fpb_rx261/fpb_rx261-pinctrl.dtsi | 14 +++ boards/renesas/fpb_rx261/fpb_rx261.dts | 86 +++++++++++++++++++ boards/renesas/fpb_rx261/fpb_rx261.yaml | 17 ++++ boards/renesas/fpb_rx261/fpb_rx261_defconfig | 13 +++ 7 files changed, 150 insertions(+) create mode 100644 boards/renesas/fpb_rx261/Kconfig.fpb_rx261 create mode 100644 boards/renesas/fpb_rx261/board.cmake create mode 100644 boards/renesas/fpb_rx261/board.yml create mode 100644 boards/renesas/fpb_rx261/fpb_rx261-pinctrl.dtsi create mode 100644 boards/renesas/fpb_rx261/fpb_rx261.dts create mode 100644 boards/renesas/fpb_rx261/fpb_rx261.yaml create mode 100644 boards/renesas/fpb_rx261/fpb_rx261_defconfig diff --git a/boards/renesas/fpb_rx261/Kconfig.fpb_rx261 b/boards/renesas/fpb_rx261/Kconfig.fpb_rx261 new file mode 100644 index 000000000000..3689a86dcb48 --- /dev/null +++ b/boards/renesas/fpb_rx261/Kconfig.fpb_rx261 @@ -0,0 +1,5 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_FPB_RX261 + select SOC_R5F52618BGFP diff --git a/boards/renesas/fpb_rx261/board.cmake b/boards/renesas/fpb_rx261/board.cmake new file mode 100644 index 000000000000..e7d620c25576 --- /dev/null +++ b/boards/renesas/fpb_rx261/board.cmake @@ -0,0 +1,9 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +# options after "--tool-opt=" are directly passed to the tool. So instead of "--iface=JTAG" you could also write "--tool-opt=-if JTAG" +board_runner_args(jlink "--device=R5F52618" "--iface=FINE" "--speed=1000" "--tool-opt=-jtagconf -1,-1 -autoconnect 1" ) +board_runner_args(rfp "--device=RX200" "--tool=e2l" "--interface=fine" "--erase") + +include(${ZEPHYR_BASE}/boards/common/rfp.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/renesas/fpb_rx261/board.yml b/boards/renesas/fpb_rx261/board.yml new file mode 100644 index 000000000000..ffd674c70690 --- /dev/null +++ b/boards/renesas/fpb_rx261/board.yml @@ -0,0 +1,6 @@ +board: + name: fpb_rx261 + full_name: RX261 Fast Prototyping Board + vendor: renesas + socs: + - name: r5f52618bgfp diff --git a/boards/renesas/fpb_rx261/fpb_rx261-pinctrl.dtsi b/boards/renesas/fpb_rx261/fpb_rx261-pinctrl.dtsi new file mode 100644 index 000000000000..e00377a7d4b3 --- /dev/null +++ b/boards/renesas/fpb_rx261/fpb_rx261-pinctrl.dtsi @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + sci5_default: sci5_default { + group1 { + psels = , /* TX */ + ; /* RX */ + }; + }; +}; diff --git a/boards/renesas/fpb_rx261/fpb_rx261.dts b/boards/renesas/fpb_rx261/fpb_rx261.dts new file mode 100644 index 000000000000..df1e4f2203dd --- /dev/null +++ b/boards/renesas/fpb_rx261/fpb_rx261.dts @@ -0,0 +1,86 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include "fpb_rx261-pinctrl.dtsi" + +/ { + model = "Renesas FPB-RX261"; + compatible = "renesas,fpb_rx261","renesas,rxv3"; + + chosen { + zephyr,sram = &sram0; + zephyr,flash = &code_flash; + zephyr,console = &uart5; + zephyr,shell-uart = &uart5; + }; + + leds { + compatible = "gpio-leds"; + + led1: led1 { + gpios = <&ioportj 1 GPIO_ACTIVE_LOW>; + label = "LED1"; + }; + + led2: led2 { + gpios = <&ioportc 5 GPIO_ACTIVE_LOW>; + label = "LED2"; + }; + }; + + aliases { + led0 = &led1; + led1 = &led2; + }; +}; + +&subclk { + status = "okay"; +}; + +&cmt { + clock-frequency = <4000000>; + status = "okay"; +}; + +&pclkblock { + clocks = <&hoco>; +}; + +&clkout { + clocks = <&hoco>; +}; + +&uclk { + clocks = <&hoco>; +}; + +&ioport3 { + status = "okay"; +}; + +&ioportc { + status = "okay"; +}; + +&ioportj { + status = "okay"; +}; + +&sci5 { + pinctrl-0 = <&sci5_default>; + pinctrl-names = "default"; + status = "okay"; + + uart5: uart { + current-speed = <115200>; + status = "okay"; + }; +}; diff --git a/boards/renesas/fpb_rx261/fpb_rx261.yaml b/boards/renesas/fpb_rx261/fpb_rx261.yaml new file mode 100644 index 000000000000..0f182d6d0289 --- /dev/null +++ b/boards/renesas/fpb_rx261/fpb_rx261.yaml @@ -0,0 +1,17 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +identifier: fpb_rx261 +name: Renesas RX261 Fast Prototyping Board +type: mcu +arch: rx +toolchain: + - cross-compile +supported: + - gpio + - serial + - timer +ram: 128 +flash: 512 +testing: + timeout_multiplier: 5 diff --git a/boards/renesas/fpb_rx261/fpb_rx261_defconfig b/boards/renesas/fpb_rx261/fpb_rx261_defconfig new file mode 100644 index 000000000000..c23cdd58f2a0 --- /dev/null +++ b/boards/renesas/fpb_rx261/fpb_rx261_defconfig @@ -0,0 +1,13 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +# Enable GPIO +CONFIG_GPIO=y + +# Enable UART driver +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y From 7fd0a108ff0763a05eeaa3d3a588f6dbd72f99ba Mon Sep 17 00:00:00 2001 From: Hau Ho Date: Wed, 12 Mar 2025 13:52:34 +0700 Subject: [PATCH 10/10] boards: renesas: Initial commit to support for EK-RX261 board Initial support for EK-RX261 board using RX261 SOC Singed-off-by: Quy Tran Signed-off-by: Hau Ho --- boards/renesas/ek_rx261/Kconfig.ek_rx261 | 5 + boards/renesas/ek_rx261/board.cmake | 9 ++ boards/renesas/ek_rx261/board.yml | 6 ++ boards/renesas/ek_rx261/ek_rx261-pinctrl.dtsi | 14 +++ boards/renesas/ek_rx261/ek_rx261.dts | 98 +++++++++++++++++++ boards/renesas/ek_rx261/ek_rx261.yaml | 17 ++++ boards/renesas/ek_rx261/ek_rx261_defconfig | 13 +++ 7 files changed, 162 insertions(+) create mode 100644 boards/renesas/ek_rx261/Kconfig.ek_rx261 create mode 100644 boards/renesas/ek_rx261/board.cmake create mode 100644 boards/renesas/ek_rx261/board.yml create mode 100644 boards/renesas/ek_rx261/ek_rx261-pinctrl.dtsi create mode 100644 boards/renesas/ek_rx261/ek_rx261.dts create mode 100644 boards/renesas/ek_rx261/ek_rx261.yaml create mode 100644 boards/renesas/ek_rx261/ek_rx261_defconfig diff --git a/boards/renesas/ek_rx261/Kconfig.ek_rx261 b/boards/renesas/ek_rx261/Kconfig.ek_rx261 new file mode 100644 index 000000000000..1398477e9bab --- /dev/null +++ b/boards/renesas/ek_rx261/Kconfig.ek_rx261 @@ -0,0 +1,5 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_EK_RX261 + select SOC_R5F52618BGFP diff --git a/boards/renesas/ek_rx261/board.cmake b/boards/renesas/ek_rx261/board.cmake new file mode 100644 index 000000000000..5a5399d5f2fb --- /dev/null +++ b/boards/renesas/ek_rx261/board.cmake @@ -0,0 +1,9 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +# options after "--tool-opt=" are directly passed to the tool. So instead of "--iface=JTAG" you could also write "--tool-opt=-if JTAG" +board_runner_args(jlink "--device=R5F52618" "--iface=FINE" "--speed=1000" "--tool-opt=-jtagconf -1,-1 -autoconnect 1" ) +board_runner_args(rfp "--device=RX200" "--tool=e2l" "--interface=fine" "--erase") + +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +include(${ZEPHYR_BASE}/boards/common/rfp.board.cmake) diff --git a/boards/renesas/ek_rx261/board.yml b/boards/renesas/ek_rx261/board.yml new file mode 100644 index 000000000000..3b120fa6c6b1 --- /dev/null +++ b/boards/renesas/ek_rx261/board.yml @@ -0,0 +1,6 @@ +board: + name: ek_rx261 + full_name: RX261 Evaluation Kit + vendor: renesas + socs: + - name: r5f52618bgfp diff --git a/boards/renesas/ek_rx261/ek_rx261-pinctrl.dtsi b/boards/renesas/ek_rx261/ek_rx261-pinctrl.dtsi new file mode 100644 index 000000000000..4b893daead41 --- /dev/null +++ b/boards/renesas/ek_rx261/ek_rx261-pinctrl.dtsi @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + sci6_default: sci6_default { + group1 { + psels = , /* TX */ + ; /* RX */ + }; + }; +}; diff --git a/boards/renesas/ek_rx261/ek_rx261.dts b/boards/renesas/ek_rx261/ek_rx261.dts new file mode 100644 index 000000000000..77db364b60b6 --- /dev/null +++ b/boards/renesas/ek_rx261/ek_rx261.dts @@ -0,0 +1,98 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include "ek_rx261-pinctrl.dtsi" + +/ { + model = "Renesas EK-RX261 KIT"; + compatible = "renesas,ek_rx261","renesas,rxv3"; + + chosen { + zephyr,sram = &sram0; + zephyr,flash = &code_flash; + zephyr,console = &uart6; + zephyr,shell-uart = &uart6; + }; + + leds { + compatible = "gpio-leds"; + + led1: led1 { + gpios = <&ioportj 1 GPIO_ACTIVE_LOW>; + label = "LED1"; + }; + + led2: led2 { + gpios = <&ioportc 5 GPIO_ACTIVE_LOW>; + label = "LED2"; + }; + + led3: led3 { + gpios = <&ioporta 3 GPIO_ACTIVE_LOW>; + label = "LED3"; + }; + + }; + + aliases { + led0 = &led1; + led1 = &led2; + led2 = &led3; + }; +}; + +&xtal { + clock-frequency = ; + mosel = <0>; + #clock-cells = <0>; + status = "okay"; +}; + +&pll { + div = <1>; + mul = ; + status = "okay"; +}; + +&cmt { + clock-frequency = <4000000>; + status = "okay"; +}; + +&ioport3 { + status = "okay"; +}; + +&ioporta { + status = "okay"; +}; + +&ioportc { + status = "okay"; +}; + +&ioportd { + status = "okay"; +}; + +&ioportj { + status = "okay"; +}; + +&sci6 { + pinctrl-0 = <&sci6_default>; + pinctrl-names = "default"; + status = "okay"; + + uart6: uart { + current-speed = <115200>; + status = "okay"; + }; +}; diff --git a/boards/renesas/ek_rx261/ek_rx261.yaml b/boards/renesas/ek_rx261/ek_rx261.yaml new file mode 100644 index 000000000000..aa807dbe4ce9 --- /dev/null +++ b/boards/renesas/ek_rx261/ek_rx261.yaml @@ -0,0 +1,17 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +identifier: ek_rx261 +name: Renesas EK-RX261 +type: mcu +arch: rx +toolchain: + - cross-compile +supported: + - gpio + - serial + - timer +ram: 128 +flash: 512 +testing: + timeout_multiplier: 5 diff --git a/boards/renesas/ek_rx261/ek_rx261_defconfig b/boards/renesas/ek_rx261/ek_rx261_defconfig new file mode 100644 index 000000000000..c23cdd58f2a0 --- /dev/null +++ b/boards/renesas/ek_rx261/ek_rx261_defconfig @@ -0,0 +1,13 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +# Enable GPIO +CONFIG_GPIO=y + +# Enable UART driver +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y