diff --git a/drivers/clock_control/clock_control_nrf_auxpll.c b/drivers/clock_control/clock_control_nrf_auxpll.c
index 19dee8c44938..9c98905bf4ad 100644
--- a/drivers/clock_control/clock_control_nrf_auxpll.c
+++ b/drivers/clock_control/clock_control_nrf_auxpll.c
@@ -17,6 +17,16 @@
 #include <zephyr/toolchain.h>
 
 #include <hal/nrf_auxpll.h>
+#include <zephyr/dt-bindings/clock/nrf-auxpll.h>
+
+/* Check dt-bindings match MDK frequency division definitions*/
+BUILD_ASSERT(                                                             \
+	NRF_AUXPLL_FREQ_DIV_MIN     	== NRF_AUXPLL_FREQUENCY_DIV_MIN   	&&    \
+	NRF_AUXPLL_FREQ_DIV_AUDIO_44K1  == NRF_AUXPLL_FREQUENCY_AUDIO_44K1 	&&    \
+	NRF_AUXPLL_FREQ_DIV_USB24M      == NRF_AUXPLL_FREQUENCY_USB_24M   	&&    \
+	NRF_AUXPLL_FREQ_DIV_AUDIO_48K   == NRF_AUXPLL_FREQUENCY_AUDIO_48K 	&&    \
+	NRF_AUXPLL_FREQ_DIV_MAX         == NRF_AUXPLL_FREQUENCY_DIV_MAX,          \
+	"Different AUXPLL frequency definitions in MDK and devicetree bindings");
 
 /* maximum lock time in ms, >10x time observed experimentally */
 #define AUXPLL_LOCK_TIME_MAX_MS  20
@@ -28,7 +38,7 @@ struct clock_control_nrf_auxpll_config {
 	uint32_t ref_clk_hz;
 	uint32_t ficr_ctune;
 	nrf_auxpll_config_t cfg;
-	uint16_t frequency;
+	nrf_auxpll_freq_div_ratio_t frequency;
 	nrf_auxpll_ctrl_outsel_t out_div;
 };
 
@@ -124,6 +134,13 @@ static int clock_control_nrf_auxpll_init(const struct device *dev)
 }
 
 #define CLOCK_CONTROL_NRF_AUXPLL_DEFINE(n)                                                         \
+	BUILD_ASSERT(                                                                            \
+		DT_INST_PROP(n, nordic_frequency) == NRF_AUXPLL_FREQUENCY_DIV_MIN   ||          \
+		DT_INST_PROP(n, nordic_frequency) == NRF_AUXPLL_FREQUENCY_AUDIO_44K1||          \
+		DT_INST_PROP(n, nordic_frequency) == NRF_AUXPLL_FREQUENCY_USB_24M   ||          \
+		DT_INST_PROP(n, nordic_frequency) == NRF_AUXPLL_FREQUENCY_AUDIO_48K ||          \
+		DT_INST_PROP(n, nordic_frequency) == NRF_AUXPLL_FREQUENCY_DIV_MAX,              \
+		"Invalid nordic,frequency value in DeviceTree for AUXPLL instance " #n);      \
 	static const struct clock_control_nrf_auxpll_config config##n = {                          \
 		.auxpll = (NRF_AUXPLL_Type *)DT_INST_REG_ADDR(n),                                  \
 		.ref_clk_hz = DT_PROP(DT_INST_CLOCKS_CTLR(n), clock_frequency),                    \
diff --git a/dts/bindings/clock/nordic,nrf-auxpll.yaml b/dts/bindings/clock/nordic,nrf-auxpll.yaml
index 6eec285f39eb..9555995f0b4d 100644
--- a/dts/bindings/clock/nordic,nrf-auxpll.yaml
+++ b/dts/bindings/clock/nordic,nrf-auxpll.yaml
@@ -43,7 +43,7 @@ properties:
     required: true
     description: |
       Value used to set the fractional PLL divider ratio (can be set between
-      divider ratios 4 to 5). Valid values range from 0 to 65535.
+      divider ratios 4 to 5). Valid values shown in dt-bindings/clock/nrf-auxpll.h.
 
   nordic,out-div:
     type: int
diff --git a/dts/vendor/nordic/nrf54h20.dtsi b/dts/vendor/nordic/nrf54h20.dtsi
index 8339a67229cf..aea8de03ccb6 100644
--- a/dts/vendor/nordic/nrf54h20.dtsi
+++ b/dts/vendor/nordic/nrf54h20.dtsi
@@ -9,6 +9,7 @@
 
 #include <zephyr/dt-bindings/adc/nrf-saadc-haltium.h>
 #include <zephyr/dt-bindings/clock/nrfs-audiopll.h>
+#include <zephyr/dt-bindings/clock/nrf-auxpll.h>
 #include <zephyr/dt-bindings/misc/nordic-nrf-ficr-nrf54h20.h>
 #include <zephyr/dt-bindings/misc/nordic-domain-id-nrf54h20.h>
 #include <zephyr/dt-bindings/misc/nordic-owner-id-nrf54h20.h>
@@ -558,7 +559,7 @@
 				clocks = <&hfxo>;
 				#clock-cells = <0>;
 				nordic,ficrs = <&ficr NRF_FICR_TRIM_GLOBAL_CANPLL_TRIM_CTUNE>;
-				nordic,frequency = <0>;
+				nordic,frequency = <NRF_AUXPLL_FREQ_MIN>;
 				nordic,out-div = <2>;
 				nordic,out-drive = <0>;
 				nordic,current-tune = <6>;
diff --git a/include/zephyr/dt-bindings/clock/nrf-auxpll.h b/include/zephyr/dt-bindings/clock/nrf-auxpll.h
new file mode 100644
index 000000000000..a07c96997597
--- /dev/null
+++ b/include/zephyr/dt-bindings/clock/nrf-auxpll.h
@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_NRF_AUXPLL_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_NRF_AUXPLL_H_
+
+#define NRF_AUXPLL_FREQ_DIV_MIN        0
+#define NRF_AUXPLL_FREQ_DIV_AUDIO_44K1 15309
+#define NRF_AUXPLL_FREQ_DIV_USB24M     32768
+#define NRF_AUXPLL_FREQ_DIV_AUDIO_48K  39845
+#define NRF_AUXPLL_FREQ_DIV_MAX        65535
+
+#endif /* #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_NRF_AUXPLL_H_ */