diff --git a/boards/st/stm32mp257f_ev1/Kconfig.stm32mp257f_ev1 b/boards/st/stm32mp257f_ev1/Kconfig.stm32mp257f_ev1 new file mode 100644 index 000000000000..5184ef6636ed --- /dev/null +++ b/boards/st/stm32mp257f_ev1/Kconfig.stm32mp257f_ev1 @@ -0,0 +1,5 @@ +# Copyright (C) 2025 Savoir-faire Linux, Inc. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_STM32MP257F_EV1 + select SOC_STM32MP2X_M33 if BOARD_STM32MP257F_EV1_STM32MP257FXX_M33 diff --git a/boards/st/stm32mp257f_ev1/board.cmake b/boards/st/stm32mp257f_ev1/board.cmake new file mode 100644 index 000000000000..eb52f9981fef --- /dev/null +++ b/boards/st/stm32mp257f_ev1/board.cmake @@ -0,0 +1,9 @@ +# Copyright (C) 2025 Savoir-faire Linux, Inc. +# SPDX-License-Identifier: Apache-2.0 + +if(CONFIG_BOARD_STM32MP257F_EV1_STM32MP257FXX_M33) + board_runner_args(openocd "--config=${BOARD_DIR}/support/openocd_stm32mp257f_ev1_m33.cfg") + board_runner_args(openocd "--gdb-init=target extended-remote :3334") +endif() + +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/st/stm32mp257f_ev1/board.yml b/boards/st/stm32mp257f_ev1/board.yml new file mode 100644 index 000000000000..81cdba090642 --- /dev/null +++ b/boards/st/stm32mp257f_ev1/board.yml @@ -0,0 +1,6 @@ +board: + name: stm32mp257f_ev1 + full_name: STM32MP257F-EV1 Evaluation Board + vendor: st + socs: + - name: stm32mp257fxx diff --git a/boards/st/stm32mp257f_ev1/doc/img/stm32mp257f_ev1.webp b/boards/st/stm32mp257f_ev1/doc/img/stm32mp257f_ev1.webp new file mode 100644 index 000000000000..ad2c6e8dd776 Binary files /dev/null and b/boards/st/stm32mp257f_ev1/doc/img/stm32mp257f_ev1.webp differ diff --git a/boards/st/stm32mp257f_ev1/doc/index.rst b/boards/st/stm32mp257f_ev1/doc/index.rst new file mode 100644 index 000000000000..15145e73735e --- /dev/null +++ b/boards/st/stm32mp257f_ev1/doc/index.rst @@ -0,0 +1,250 @@ +.. zephyr:board:: stm32mp257f_ev1 + +Overview +******** + +The STM32MP257F-EV1 Evaluation board is designed as a complete demonstration +and development platform for the STMicroelectronics STM32MP257F microprocessor +based on Arm |reg| dual-core Cortex |reg|-A35 (1.5 GHz) and Cortex |reg|-M33 +(400 MHz), and the STPMIC25APQR companion chip. +Zephyr OS is ported to run on the Cortex |reg|-M33 core, as a coprocessor of +the Cortex |reg|-A35 core. + +Features: +========= + +- STM32MP257FAI3 microprocessor featuring dual-core Arm |reg| Cortex |reg|-A35, + a Cortex |reg|-M33 and a Cortex |reg|-M0+ in a TFBGA436 package +- ST power management STPMIC25APQR +- Two 16-Gbit DDR4 DRAMs +- 512-Mbit (64 Mbytes) S-NOR flash memory +- 32-Gbit (4 Gbytes) eMMC v5.0 +- Three 1-Gbit/s Ethernet (RGMII) with TSN switch compliant with IEEE-802.3ab +- High-speed USB Host 2-port hub +- High-speed USB Type-C |reg| DRP +- Four user LEDs +- Two user, one tamper, and one reset push-buttons +- One wake-up button +- Four boot pin switches +- Board connectors: + + - Three Ethernet RJ45 + - Two USB Host Type-A + - USB Type-C |reg| + - microSD |trade| card holder + - Mini PCIe + - Dual-lane MIPI CSI-2 |reg| camera module expansion connector + - Two CAN FD + - LVDS + - MIPI10 + - GPIO expansion connector + - mikroBUS |trade| expansion connector + - VBAT for power backup + +- On-board STLINK-V3EC debugger/programmer with USB re-enumeration capability + Two Virtual COM ports (VCPs), and debug ports (JTAG/SWD) +- Mainlined open-source Linux |reg| STM32 MPU OpenSTLinux Distribution and + STM32CubeMP2 software with examples +- Linux |reg| Yocto project, Buildroot, and STM32CubeIDE as + development environments + +More information about the board can be found at the +`STM32MP257F-EV1 website`_. + +Hardware +******** + +Cores: +====== + +- 64-bit dual-core Arm |reg| Cortex |reg|-A35 with 1.5 GHz max frequency + - 32-Kbyte I + 32-Kbyte D level 1 cache for each Cortex |reg|-A35 core + - 512-Kbyte unified level 2 cache + - Arm |reg| NEON |trade| and Arm |reg| TrustZone |reg| +- 32-bit Arm |reg| Cortex |reg|-M33 with FPU/MPU, Arm |reg| TrustZone |reg|, + and 400 MHz max frequency + - L1 16-Kbyte ICache / 16-Kbyte DCache for Cortex |reg|-M33 +- 32-bit Arm |reg| Cortex |reg|-M0+ in SmartRun domain with 200 MHz max + frequency (up to 16 MHz in autonomous mode) + +Memories: +========= + +- External DDR memory up to 4 Gbytes + - Up to DDR3L-2133 16/32-bit + - Up to DDR4-2400 16/32-bit + - Up to LPDDR4-2400 16/32-bit +- 808-Kbyte internal SRAM: 256-Kbyte AXI SYSRAM, 128-Kbyte AXI video RAM or + SYSRAM extension, 256-Kbyte AHB SRAM, 128-Kbyte AHB SRAM with ECC in backup + domain, 8-Kbyte SRAM with ECC in backup domain, 32 Kbytes in SmartRun domain +- Two Octo-SPI memory interfaces +- Flexible external memory controller with up to 16-bit data bus: parallel + interface to connect external ICs, and SLC NAND memories with up to 8-bit ECC + +Power +===== + +- STPMIC25 for voltage regulation (multiple buck/LDO regulators) +- USB-C or 5V DC jack power input +- VBAT backup battery connector (RTC, backup SRAM) + +Clock management +================ + +- External oscillators: + - 32.768 kHz LSE crystal + - 40 MHz HSE crystal +- Internal oscillators: + - 64 MHz HSI oscillator + - 4 MHz CSI oscillator + - 32 kHz LSI oscillator + - Five separate PLLs with integer and fractional mode + +Security/Safety +=============== + +- Secure boot, TrustZone |reg| peripherals, active tamper, environmental + monitors, display secure layers, hardware accelerators +- Complete resource isolation framework + +Connectivity +============ + +- 3x Gigabit Ethernet (RGMII, TSN switch capable) +- 2x CAN FD +- USB 2.0 High-Speed Host (dual-port) +- USB Type-C |reg| DRP +- mikroBUS |trade| expansion +- GPIO expansion connector + +Display & Camera +================ + +- DSI interface (4-lane) +- LVDS interface (4-lane) +- Camera CSI-2 interface (2-lane) + +Debug +===== + +- STLINK-V3EC (onboard debugger with VCP, JTAG and SWD) + +More information about STM32MP257F can be found here: + +- `STM32MP257F on www.st.com`_ + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +Connections and IOs +=================== + +STM32MP257F-EV1 Evaluation Board schematic is available here: +`STM32MP257F-EV1 Evaluation board schematics`_ + +System Clock +============ + +Cortex |reg|-A35 +---------------- + +Not yet supported in Zephyr. + +Cortex |reg|-M33 +---------------- + +The Cortex |reg|-M33 Core is configured to run at a 400 MHz clock speed. + +Programming and Debugging +************************* + +.. zephyr:board-supported-runners:: + +Prerequisite +============ + +Before you can run Zephyr on the STM32MP257F-EV1 Evaluation board, you need to +set up the Cortex |reg|-A35 core with a Linux |reg| environment. The Cortex +|reg|-M33 core runs Zephyr as a coprocessor, and it requires the Cortex +|reg|-A35 to load and start the firmware using remoteproc. + +One way to set up the Linux environment is to use the official ST +OpenSTLinux distribution, following the `Starter Package`_. (more information +about the procedure can be found in the `STM32MPU Wiki`_) + +Loading the firmware +==================== + +Once the OpenSTLinux distribution is installed on the board, the Cortex |reg| +-A35 is responsible (in the current distribution) for loading the Zephyr +firmware image in DDR and/or SRAM and starting the Cortex |reg| -M33 core. The +application can be built using west, taking the :zephyr:code-sample:`blinky` as +an example. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: stm32mp257f_ev1/stm32mp257fxx/m33 + :goals: build + +The firmware can be copied to the board file system and started with the Linux +remoteproc framework. (more information about the procedure can be found in the +`STM32MP257F boot Cortex-M33 firmware`_) + +Debugging +========= +Applications can be debugged using OpenOCD and GDB. The OpenOCD files can be +found at `device-stm-openocd`_. +The firmware must first be started by the Cortex |reg|-A35. The debugger can +then be attached to the running Zephyr firmware using OpenOCD. + +- Build the sample: + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: stm32mp257f_ev1/stm32mp257fxx/m33 + :goals: build + +- Copy the firmware to the board, load it and start it with remoteproc + (`STM32MP257F boot Cortex-M33 firmware`_). The orange LED should be blinking. +- Attach to the target: + +.. code-block:: console + + $ west attach + +References +========== + +.. target-notes:: + +.. _STM32MP257F-EV1 website: + https://www.st.com/en/evaluation-tools/stm32mp257f-ev1.html#overview + +.. _STM32MP257F-EV1 Evaluation board User Manual: + https://www.st.com/resource/en/user_manual/um3359-evaluation-board-with-stm32mp257f-mpu-stmicroelectronics.pdf + +.. _STM32MP257F-EV1 Evaluation board schematics: + https://www.st.com/resource/en/schematic_pack/mb1936-mp257f-x-d01-schematic.pdf + +.. _STM32MP25xC/F Evaluation board datasheet: + https://www.st.com/resource/en/datasheet/stm32mp257c.pdf + +.. _STM32MP257F on www.st.com: + https://www.st.com/en/microcontrollers-microprocessors/stm32mp257f.html + +.. _STM32MP257F reference manual: + https://www.st.com/resource/en/reference_manual/rm0457-stm32mp25xx-advanced-armbased-3264bit-mpus-stmicroelectronics.pdf + +.. _STM32MP257F boot Cortex-M33 firmware: + https://wiki.st.com/stm32mpu/wiki/Linux_remoteproc_framework_overview#Remote_processor_boot_through_sysfs + +.. _Starter Package: + https://wiki.st.com/stm32mpu/wiki/STM32MP25_Evaluation_boards_-_Starter_Package + +.. _STM32MPU Wiki: + https://wiki.st.com/stm32mpu/wiki/Main_Page + +.. _device-stm-openocd: + https://github.com/STMicroelectronics/device-stm-openocd/tree/main diff --git a/boards/st/stm32mp257f_ev1/stm32mp257f_ev1_stm32mp257fxx_m33.dts b/boards/st/stm32mp257f_ev1/stm32mp257f_ev1_stm32mp257fxx_m33.dts new file mode 100644 index 000000000000..61f83448a953 --- /dev/null +++ b/boards/st/stm32mp257f_ev1/stm32mp257f_ev1_stm32mp257fxx_m33.dts @@ -0,0 +1,56 @@ +/* + * Copyright (C) 2025 Savoir-faire Linux, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include +#include + +/ { + model = "STMicroelectronics STM32MP257F-EV1 board"; + compatible = "st,stm32mp257f-ev1", "st,stm32mp25"; + + chosen { + zephyr,flash = &ddr_code; + zephyr,sram = &ddr_sys; + }; + + leds { + compatible = "gpio-leds"; + + orange_led_3: led_3 { + gpios = <&gpioj 6 GPIO_ACTIVE_HIGH>; + label = "LD3"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + + button_user2: button2 { + label = "User 2"; + gpios = <&gpiog 8 GPIO_ACTIVE_LOW>; + zephyr,code = ; + }; + }; + + aliases { + led0 = &orange_led_3; + sw0 = &button_user2; + }; +}; + +&rcc { + clock-frequency = ; +}; + +&gpiog { + status = "okay"; +}; + +&gpioj { + status = "okay"; +}; diff --git a/boards/st/stm32mp257f_ev1/stm32mp257f_ev1_stm32mp257fxx_m33.yaml b/boards/st/stm32mp257f_ev1/stm32mp257f_ev1_stm32mp257fxx_m33.yaml new file mode 100644 index 000000000000..127e2f85d8b3 --- /dev/null +++ b/boards/st/stm32mp257f_ev1/stm32mp257f_ev1_stm32mp257fxx_m33.yaml @@ -0,0 +1,24 @@ +identifier: stm32mp257f_ev1/stm32mp257fxx/m33 +name: STM32MP257F_EV1 +type: mcu +arch: arm +toolchain: + - zephyr + - gccarmemb +supported: + - LED + - gpio +testing: + ignore_tags: + - cmsis_rtos_v2 + - net + - mpu + - tinycrypt + - crypto + - aes + - cmm + - shell + - nfc +ram: 8192 +flash: 8192 +vendor: st diff --git a/boards/st/stm32mp257f_ev1/stm32mp257f_ev1_stm32mp257fxx_m33_defconfig b/boards/st/stm32mp257f_ev1/stm32mp257f_ev1_stm32mp257fxx_m33_defconfig new file mode 100644 index 000000000000..ba770561fbe1 --- /dev/null +++ b/boards/st/stm32mp257f_ev1/stm32mp257f_ev1_stm32mp257fxx_m33_defconfig @@ -0,0 +1,11 @@ +# Copyright (C) 2025 Savoir-faire Linux, Inc. +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable GPIO +CONFIG_GPIO=y + +# Enable HW stack protection +CONFIG_HW_STACK_PROTECTION=y diff --git a/boards/st/stm32mp257f_ev1/support/openocd_stm32mp257f_ev1_m33.cfg b/boards/st/stm32mp257f_ev1/support/openocd_stm32mp257f_ev1_m33.cfg new file mode 100644 index 000000000000..a690cfa54995 --- /dev/null +++ b/boards/st/stm32mp257f_ev1/support/openocd_stm32mp257f_ev1_m33.cfg @@ -0,0 +1,10 @@ +# Only enable the Cortex-M33 debugger +set EN_CA35_0 0 +set EN_CA35_1 0 +set EN_CM33 1 +set EN_CM0P 0 + +source [find board/stm32mp25x_dk.cfg] + +# Set active target to Cortex-M33 +targets stm32mp25x.m33 diff --git a/drivers/clock_control/CMakeLists.txt b/drivers/clock_control/CMakeLists.txt index 886c92b63578..677eccd9e8ba 100644 --- a/drivers/clock_control/CMakeLists.txt +++ b/drivers/clock_control/CMakeLists.txt @@ -70,6 +70,8 @@ if(CONFIG_SOC_SERIES_STM32MP1X) zephyr_library_sources(clock_stm32_ll_mp1.c) elseif(CONFIG_SOC_SERIES_STM32MP13X) zephyr_library_sources(clock_stm32_ll_mp13.c) +elseif(CONFIG_SOC_SERIES_STM32MP2X) + zephyr_library_sources(clock_stm32_ll_mp2.c) elseif(CONFIG_SOC_SERIES_STM32H7X) zephyr_library_sources(clock_stm32_ll_h7.c) elseif(CONFIG_SOC_SERIES_STM32H7RSX) diff --git a/drivers/clock_control/Kconfig.stm32 b/drivers/clock_control/Kconfig.stm32 index d1b41416fdb1..0815e149de68 100644 --- a/drivers/clock_control/Kconfig.stm32 +++ b/drivers/clock_control/Kconfig.stm32 @@ -2,6 +2,7 @@ # Copyright (c) 2017 Linaro # Copyright (c) 2017 RnDity Sp. z o.o. +# Copyright (C) 2025 Savoir-faire Linux, Inc. # SPDX-License-Identifier: Apache-2.0 menuconfig CLOCK_CONTROL_STM32_CUBE @@ -9,8 +10,9 @@ menuconfig CLOCK_CONTROL_STM32_CUBE depends on SOC_FAMILY_STM32 default y select USE_STM32_LL_UTILS - select USE_STM32_LL_RCC if (SOC_SERIES_STM32MP1X || SOC_SERIES_STM32MP13X || SOC_SERIES_STM32H7X || \ - SOC_SERIES_STM32H7RSX || SOC_SERIES_STM32F4X || SOC_SERIES_STM32F7X || \ + select USE_STM32_LL_RCC if (SOC_SERIES_STM32MP1X || SOC_SERIES_STM32MP13X || \ + SOC_SERIES_STM32MP2X || SOC_SERIES_STM32H7X || SOC_SERIES_STM32H7RSX || \ + SOC_SERIES_STM32F4X || SOC_SERIES_STM32F7X || \ SOC_SERIES_STM32N6X) select RUNTIME_NMI if ($(dt_nodelabel_enabled,clk_hse) && \ $(dt_nodelabel_bool_prop,clk_hse,css-enabled)) diff --git a/drivers/clock_control/clock_stm32_ll_mp2.c b/drivers/clock_control/clock_stm32_ll_mp2.c new file mode 100644 index 000000000000..0164c67a9e00 --- /dev/null +++ b/drivers/clock_control/clock_stm32_ll_mp2.c @@ -0,0 +1,72 @@ +/* + * Copyright (C) 2025 Savoir-faire Linux, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include +#include + +static int stm32_clock_control_on(const struct device *dev, clock_control_subsys_t sub_system) +{ + struct stm32_pclken *pclken = (struct stm32_pclken *) sub_system; + + ARG_UNUSED(dev); + + if (!IN_RANGE(pclken->bus, STM32_CLOCK_PERIPH_MIN, STM32_CLOCK_PERIPH_MAX)) { + /* Attempt to change a wrong periph clock bit */ + return -ENOTSUP; + } + + sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus, pclken->enr); + + return 0; +} + +static int stm32_clock_control_off(const struct device *dev, clock_control_subsys_t sub_system) +{ + struct stm32_pclken *pclken = (struct stm32_pclken *) sub_system; + + ARG_UNUSED(dev); + + if (!IN_RANGE(pclken->bus, STM32_CLOCK_PERIPH_MIN, STM32_CLOCK_PERIPH_MAX)) { + /* Attempt to toggle a wrong periph clock bit */ + return -ENOTSUP; + } + + sys_clear_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus, pclken->enr); + + return 0; +} + +static int stm32_clock_control_get_subsys_rate(const struct device *dev, + clock_control_subsys_t sub_system, uint32_t *rate) +{ + ARG_UNUSED(dev); + ARG_UNUSED(sub_system); + ARG_UNUSED(rate); + return -ENOTSUP; +} + +static DEVICE_API(clock_control, stm32_clock_control_api) = { + .on = stm32_clock_control_on, + .off = stm32_clock_control_off, + .get_rate = stm32_clock_control_get_subsys_rate, +}; + +static int stm32_clock_control_init(const struct device *dev) +{ + ARG_UNUSED(dev); + return 0; +} + +/** + * @brief RCC device, note that priority is intentionally set to 1 so + * that the device init runs just after SOC init + */ +DEVICE_DT_DEFINE(DT_NODELABEL(rcc), stm32_clock_control_init, NULL, NULL, NULL, PRE_KERNEL_1, + CONFIG_CLOCK_CONTROL_INIT_PRIORITY, &stm32_clock_control_api); diff --git a/drivers/gpio/Kconfig.stm32 b/drivers/gpio/Kconfig.stm32 index d414cfae4e5f..d05baf9c4ce1 100644 --- a/drivers/gpio/Kconfig.stm32 +++ b/drivers/gpio/Kconfig.stm32 @@ -1,11 +1,12 @@ # STM32 GPIO configuration # Copyright (c) 2016 Open-RnD Sp. z o.o. +# Copyright (C) 2025 Savoir-faire Linux, Inc. # SPDX-License-Identifier: Apache-2.0 config GPIO_STM32 bool "GPIO Driver for STM32 family of MCUs" default y - depends on DT_HAS_ST_STM32_GPIO_ENABLED + depends on DT_HAS_ST_STM32_GPIO_ENABLED || DT_HAS_ST_STM32MP2_GPIO_ENABLED help Enable GPIO driver for STM32 line of MCUs diff --git a/drivers/gpio/gpio_stm32.c b/drivers/gpio/gpio_stm32.c index b5fa7aeec943..3da32fdc7216 100644 --- a/drivers/gpio/gpio_stm32.c +++ b/drivers/gpio/gpio_stm32.c @@ -1,5 +1,6 @@ /* * Copyright (c) 2016 Open-RnD Sp. z o.o. + * Copyright (C) 2025 Savoir-faire Linux, Inc. * * SPDX-License-Identifier: Apache-2.0 */ @@ -708,7 +709,7 @@ static int gpio_stm32_pm_action(const struct device *dev, * * @return 0 */ -static int gpio_stm32_init(const struct device *dev) +__maybe_unused static int gpio_stm32_init(const struct device *dev) { struct gpio_stm32_data *data = dev->data; @@ -737,12 +738,16 @@ static int gpio_stm32_init(const struct device *dev) }, \ .base = (uint32_t *)__base_addr, \ .port = __port, \ - .pclken = { .bus = __bus, .enr = __cenr } \ + COND_CODE_1(DT_NODE_HAS_PROP(__node, clocks), \ + (.pclken = { .bus = __bus, .enr = __cenr },), \ + (/* Nothing if clocks not present */)) \ }; \ static struct gpio_stm32_data gpio_stm32_data_## __suffix; \ PM_DEVICE_DT_DEFINE(__node, gpio_stm32_pm_action); \ DEVICE_DT_DEFINE(__node, \ - gpio_stm32_init, \ + COND_CODE_1(DT_NODE_HAS_PROP(__node, clocks), \ + (gpio_stm32_init), \ + (NULL)), \ PM_DEVICE_DT_GET(__node), \ &gpio_stm32_data_## __suffix, \ &gpio_stm32_cfg_## __suffix, \ diff --git a/drivers/hwinfo/hwinfo_stm32.c b/drivers/hwinfo/hwinfo_stm32.c index 1d4a1fed0a0f..c29bb3a36da7 100644 --- a/drivers/hwinfo/hwinfo_stm32.c +++ b/drivers/hwinfo/hwinfo_stm32.c @@ -15,7 +15,8 @@ #include #include -#if defined(CONFIG_SOC_SERIES_STM32MP13X) +#if defined(CONFIG_SOC_SERIES_STM32MP13X) \ + || defined(CONFIG_SOC_SERIES_STM32MP2X) /* No ll_utils for the stm32mp13x series, instead use the HAL functions */ /* zephyr-keep-sorted-start */ @@ -32,7 +33,7 @@ #define STM32_UID_WORD_2 LL_GetUID_Word0() /* zephyr-keep-sorted-stop */ -#endif /* CONFIG_SOC_SERIES_STM32MP13X */ +#endif /* CONFIG_SOC_SERIES_STM32MP13X || CONFIG_SOC_SERIES_STM32MP2X */ struct stm32_uid { uint32_t id[3]; @@ -171,6 +172,10 @@ int z_impl_hwinfo_get_reset_cause(uint32_t *cause) if (LL_PWR_MPU_IsActiveFlag_SB()) { flags |= RESET_LOW_POWER_WAKE; } +#elif defined(CONFIG_SOC_SERIES_STM32MP2X) && defined(PWR_FLAG_SB) + if (LL_PWR_HasSystemBeenInStandby()) { + flags |= RESET_LOW_POWER_WAKE; + } #elif defined(CONFIG_SOC_SERIES_STM32WLX) || defined(CONFIG_SOC_SERIES_STM32WBX) if (LL_PWR_IsActiveFlag_C1SB()) { flags |= RESET_LOW_POWER_WAKE; @@ -200,6 +205,8 @@ int z_impl_hwinfo_clear_reset_cause(void) LL_PWR_ClearFlag_MCU(); #elif defined(CONFIG_SOC_SERIES_STM32MP13X) LL_PWR_ClearFlag_MPU(); +#elif defined(CONFIG_SOC_SERIES_STM32MP2X) && defined(PWR_FLAG_SB) + __HAL_PWR_CLEAR_FLAG(PWR_FLAG_SB); #elif defined(CONFIG_SOC_SERIES_STM32WLX) || defined(CONFIG_SOC_SERIES_STM32WBX) LL_PWR_ClearFlag_C1STOP_C1STB(); #elif defined(CONFIG_SOC_SERIES_STM32U0X) && defined(PWR_FLAG_SB) diff --git a/drivers/interrupt_controller/intc_exti_stm32.c b/drivers/interrupt_controller/intc_exti_stm32.c index f83fbf9b4e1b..bd6e4418bca2 100644 --- a/drivers/interrupt_controller/intc_exti_stm32.c +++ b/drivers/interrupt_controller/intc_exti_stm32.c @@ -2,6 +2,7 @@ * Copyright (c) 2016 Open-RnD Sp. z o.o. * Copyright (c) 2017 RnDity Sp. z o.o. * Copyright (c) 2019-23 Linaro Limited + * Copyright (C) 2025 Savoir-faire Linux, Inc. * * SPDX-License-Identifier: Apache-2.0 */ @@ -35,7 +36,7 @@ struct stm32_exti_range { uint8_t len; }; -#define NUM_EXTI_LINES DT_PROP(DT_NODELABEL(exti), num_lines) +#define NUM_EXTI_LINES DT_PROP(EXTI_NODE, num_lines) static IRQn_Type exti_irq_table[NUM_EXTI_LINES] = {[0 ... NUM_EXTI_LINES - 1] = 0xFF}; @@ -60,7 +61,8 @@ static inline uint32_t stm32_exti_linenum_to_src_cfg_line(gpio_pin_t linenum) #if defined(CONFIG_SOC_SERIES_STM32L0X) || \ defined(CONFIG_SOC_SERIES_STM32F0X) return ((linenum % 4 * 4) << 16) | (linenum / 4); -#elif DT_HAS_COMPAT_STATUS_OKAY(st_stm32g0_exti) +#elif DT_HAS_COMPAT_STATUS_OKAY(st_stm32g0_exti) || \ + defined(CONFIG_SOC_SERIES_STM32MP2X) return ((linenum & 0x3) << (16 + 3)) | (linenum >> 2); #elif DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7rs_exti) /* Gives the LL_SBS_EXTI_LINEn corresponding to the line number */ @@ -82,6 +84,9 @@ static inline int stm32_exti_is_pending(stm32_gpio_irq_line_t line) LL_EXTI_IsActiveFallingFlag_0_31(line)); #elif defined(CONFIG_SOC_SERIES_STM32H7X) && defined(CONFIG_CPU_CORTEX_M4) return LL_C2_EXTI_IsActiveFlag_0_31(line); +#elif defined(CONFIG_SOC_SERIES_STM32MP2X) + return LL_EXTI_IsActiveRisingFlag_0_31(EXTI2, line) || + LL_EXTI_IsActiveFallingFlag_0_31(EXTI2, line); #else return LL_EXTI_IsActiveFlag_0_31(line); #endif @@ -99,6 +104,9 @@ static inline void stm32_exti_clear_pending(stm32_gpio_irq_line_t line) LL_EXTI_ClearFallingFlag_0_31(line); #elif defined(CONFIG_SOC_SERIES_STM32H7X) && defined(CONFIG_CPU_CORTEX_M4) LL_C2_EXTI_ClearFlag_0_31(line); +#elif defined(CONFIG_SOC_SERIES_STM32MP2X) + LL_EXTI_ClearRisingFlag_0_31(EXTI2, line); + LL_EXTI_ClearFallingFlag_0_31(EXTI2, line); #else LL_EXTI_ClearFlag_0_31(line); #endif @@ -220,7 +228,7 @@ static int stm32_exti_init(const struct device *dev) { ARG_UNUSED(dev); - DT_FOREACH_PROP_ELEM(DT_NODELABEL(exti), + DT_FOREACH_PROP_ELEM(EXTI_NODE, interrupt_names, STM32_EXTI_INIT_LINE_RANGE); @@ -269,6 +277,8 @@ void stm32_gpio_intc_enable_line(stm32_gpio_irq_line_t line) /* Enable requested line interrupt */ #if defined(CONFIG_SOC_SERIES_STM32H7X) && defined(CONFIG_CPU_CORTEX_M4) LL_C2_EXTI_EnableIT_0_31(line); +#elif defined(CONFIG_SOC_SERIES_STM32MP2X) + LL_C2_EXTI_EnableIT_0_31(EXTI2, line); #else LL_EXTI_EnableIT_0_31(line); #endif @@ -281,6 +291,8 @@ void stm32_gpio_intc_disable_line(stm32_gpio_irq_line_t line) { #if defined(CONFIG_SOC_SERIES_STM32H7X) && defined(CONFIG_CPU_CORTEX_M4) LL_C2_EXTI_DisableIT_0_31(line); +#elif defined(CONFIG_SOC_SERIES_STM32MP2X) + LL_C2_EXTI_DisableIT_0_31(EXTI2, line); #else LL_EXTI_DisableIT_0_31(line); #endif @@ -291,6 +303,24 @@ void stm32_gpio_intc_select_line_trigger(stm32_gpio_irq_line_t line, uint32_t tr z_stm32_hsem_lock(CFG_HW_EXTI_SEMID, HSEM_LOCK_DEFAULT_RETRY); switch (trg) { +#if defined(CONFIG_SOC_SERIES_STM32MP2X) + case STM32_GPIO_IRQ_TRIG_NONE: + LL_EXTI_DisableRisingTrig_0_31(EXTI2, line); + LL_EXTI_DisableFallingTrig_0_31(EXTI2, line); + break; + case STM32_GPIO_IRQ_TRIG_RISING: + LL_EXTI_EnableRisingTrig_0_31(EXTI2, line); + LL_EXTI_DisableFallingTrig_0_31(EXTI2, line); + break; + case STM32_GPIO_IRQ_TRIG_FALLING: + LL_EXTI_EnableFallingTrig_0_31(EXTI2, line); + LL_EXTI_DisableRisingTrig_0_31(EXTI2, line); + break; + case STM32_GPIO_IRQ_TRIG_BOTH: + LL_EXTI_EnableRisingTrig_0_31(EXTI2, line); + LL_EXTI_EnableFallingTrig_0_31(EXTI2, line); + break; +#else /* CONFIG_SOC_SERIES_STM32MP2X */ case STM32_GPIO_IRQ_TRIG_NONE: LL_EXTI_DisableRisingTrig_0_31(line); LL_EXTI_DisableFallingTrig_0_31(line); @@ -307,6 +337,7 @@ void stm32_gpio_intc_select_line_trigger(stm32_gpio_irq_line_t line, uint32_t tr LL_EXTI_EnableRisingTrig_0_31(line); LL_EXTI_EnableFallingTrig_0_31(line); break; +#endif /* CONFIG_SOC_SERIES_STM32MP2X */ default: __ASSERT_NO_MSG(0); break; @@ -369,6 +400,8 @@ void stm32_exti_set_line_src_port(gpio_pin_t line, uint32_t port) LL_EXTI_SetEXTISource(port, ll_line); #elif DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7rs_exti) LL_SBS_SetEXTISource(port, ll_line); +#elif defined(CONFIG_SOC_SERIES_STM32MP2X) + LL_EXTI_SetEXTISource(EXTI2, port, ll_line); #else LL_SYSCFG_SetEXTISource(port, ll_line); #endif @@ -386,6 +419,8 @@ uint32_t stm32_exti_get_line_src_port(gpio_pin_t line) port = LL_EXTI_GetEXTISource(ll_line); #elif DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7rs_exti) port = LL_SBS_GetEXTISource(ll_line); +#elif defined(CONFIG_SOC_SERIES_STM32MP2X) + port = LL_EXTI_GetEXTISource(EXTI2, ll_line); #else port = LL_SYSCFG_GetEXTISource(ll_line); #endif diff --git a/dts/arm/st/mp2/stm32mp251_m33.dtsi b/dts/arm/st/mp2/stm32mp251_m33.dtsi new file mode 100644 index 000000000000..4aa157d50e76 --- /dev/null +++ b/dts/arm/st/mp2/stm32mp251_m33.dtsi @@ -0,0 +1,13 @@ +/* + * Copyright (C) 2025 Savoir-faire Linux, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +/ { + soc { + compatible = "st,stm32mp251", "st,stm32mp2", "simple-bus"; + }; +}; diff --git a/dts/arm/st/mp2/stm32mp253_m33.dtsi b/dts/arm/st/mp2/stm32mp253_m33.dtsi new file mode 100644 index 000000000000..710b68254962 --- /dev/null +++ b/dts/arm/st/mp2/stm32mp253_m33.dtsi @@ -0,0 +1,13 @@ +/* + * Copyright (C) 2025 Savoir-faire Linux, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +/ { + soc { + compatible = "st,stm32mp253", "st,stm32mp2", "simple-bus"; + }; +}; diff --git a/dts/arm/st/mp2/stm32mp255_m33.dtsi b/dts/arm/st/mp2/stm32mp255_m33.dtsi new file mode 100644 index 000000000000..65fc830c7dd3 --- /dev/null +++ b/dts/arm/st/mp2/stm32mp255_m33.dtsi @@ -0,0 +1,13 @@ +/* + * Copyright (C) 2025 Savoir-faire Linux, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +/ { + soc { + compatible = "st,stm32mp255", "st,stm32mp2", "simple-bus"; + }; +}; diff --git a/dts/arm/st/mp2/stm32mp257_m33.dtsi b/dts/arm/st/mp2/stm32mp257_m33.dtsi new file mode 100644 index 000000000000..95c729b1910e --- /dev/null +++ b/dts/arm/st/mp2/stm32mp257_m33.dtsi @@ -0,0 +1,21 @@ +/* + * Copyright (C) 2025 Savoir-faire Linux, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +/ { + ddr_code: memory0@80100000 { + reg = <0x80100000 DT_SIZE_M(8)>; + }; + + ddr_sys: memory1@80a00000 { + reg = <0x80a00000 DT_SIZE_M(8)>; + }; + + soc { + compatible = "st,stm32mp257", "st,stm32mp2", "simple-bus"; + }; +}; diff --git a/dts/arm/st/mp2/stm32mp2_m33.dtsi b/dts/arm/st/mp2/stm32mp2_m33.dtsi new file mode 100644 index 000000000000..9da9e1f12573 --- /dev/null +++ b/dts/arm/st/mp2/stm32mp2_m33.dtsi @@ -0,0 +1,161 @@ +/* + * Copyright (C) 2025 Savoir-faire Linux, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-m33"; + reg = <0>; + }; + }; + + ddr_code: memory0@80100000 { + compatible = "mmio-sram"; + }; + + ddr_sys: memory1@80a00000 { + compatible = "mmio-sram"; + }; + + soc { + rcc: rcc@44200000 { + compatible = "st,stm32mp2-rcc"; + clocks-controller; + #clock-cells = <2>; + reg = <0x44200000 DT_SIZE_K(64)>; + }; + + exti2: interrupt-controller@46230000 { + compatible = "st,stm32-exti"; + interrupt-controller; + #interrupt-cells = <1>; + #address-cells = <1>; + reg = <0x46230000 DT_SIZE_K(1)>; + num-lines = <16>; + interrupts = <17 0>, <18 0>, <19 0>, <20 0>, + <21 0>, <22 0>, <23 0>, <24 0>, + <25 0>, <26 0>, <27 0>, <28 0>, + <29 0>, <30 0>, <31 0>, <32 0>; + interrupt-names = "line0", "line1", "line2", "line3", + "line4", "line5", "line6", "line7", + "line8", "line9", "line10", "line11", + "line12", "line13", "line14", "line15"; + line-ranges = <0 1>, <1 1>, <2 1>, <3 1>, + <4 1>, <5 1>, <6 1>, <7 1>, + <8 1>, <9 1>, <10 1>, <11 1>, + <12 1>, <13 1>, <14 1>, <15 1>; + }; + + pinctrl: pin-controller@44240000 { + compatible = "st,stm32-pinctrl"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x44240000 0xb0000>; + + gpioa: gpio@44240000 { + compatible = "st,stm32mp2-gpio"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x44240000 DT_SIZE_K(1)>; + status = "disabled"; + }; + + gpiob: gpio@44250000 { + compatible = "st,stm32mp2-gpio"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x44250000 DT_SIZE_K(1)>; + status = "disabled"; + }; + + gpioc: gpio@44260000 { + compatible = "st,stm32mp2-gpio"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x44260000 DT_SIZE_K(1)>; + status = "disabled"; + }; + + gpiod: gpio@44270000 { + compatible = "st,stm32mp2-gpio"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x44270000 DT_SIZE_K(1)>; + status = "disabled"; + }; + + gpioe: gpio@44280000 { + compatible = "st,stm32mp2-gpio"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x44280000 DT_SIZE_K(1)>; + status = "disabled"; + }; + + gpiof: gpio@44290000 { + compatible = "st,stm32mp2-gpio"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x44290000 DT_SIZE_K(1)>; + status = "disabled"; + }; + + gpiog: gpio@442a0000 { + compatible = "st,stm32mp2-gpio"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x442a0000 DT_SIZE_K(1)>; + status = "disabled"; + }; + + gpioh: gpio@442b0000 { + compatible = "st,stm32mp2-gpio"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x442b0000 DT_SIZE_K(1)>; + status = "disabled"; + }; + + gpioi: gpio@442c0000 { + compatible = "st,stm32mp2-gpio"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x442c0000 DT_SIZE_K(1)>; + status = "disabled"; + }; + + gpioj: gpio@442d0000 { + compatible = "st,stm32mp2-gpio"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x442d0000 DT_SIZE_K(1)>; + status = "disabled"; + }; + + gpiok: gpio@442e0000 { + compatible = "st,stm32mp2-gpio"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x442e0000 DT_SIZE_K(1)>; + status = "disabled"; + }; + }; + }; +}; + +&nvic { + arm,num-irq-priority-bits = <4>; +}; diff --git a/dts/bindings/clock/st,stm32mp2-rcc.yaml b/dts/bindings/clock/st,stm32mp2-rcc.yaml new file mode 100644 index 000000000000..8bff60a5e332 --- /dev/null +++ b/dts/bindings/clock/st,stm32mp2-rcc.yaml @@ -0,0 +1,33 @@ +# Copyright (C) 2025 Savoir-faire Linux, Inc. +# SPDX-License-Identifier: Apache-2.0 + +description: | + STM32MP2 RCC (Reset and Clock controller). + + On STM32MP2 platforms, the clock tree is configured by the Cortex-A35 core. + As a consequence, the only property to be set in devicetree node is the + clock-frequency. + + As for the peripherals, the clocks are configured per peripheral in the + corresponding device tree node. The clock controller is responsible for + enabling/disabling the clocks for the peripherals, when allowed by the + Resource Isolation Framework(RIF) peripheral, configured by the cortex-A35 + core. + + To declare a peripheral "PERx" clock in the dtsi, you can follow the example + below: + PERx { + ... + clocks = <&rcc STM32_CLOCK(PERx, STM32_CLK)>; + ... + }; + +compatible: "st,stm32mp2-rcc" + +include: + - name: st,stm32-rcc.yaml + property-blocklist: + - ahb-prescaler + - apb1-prescaler + - apb2-prescaler + - undershoot-prevention diff --git a/dts/bindings/gpio/st,stm32mp2-gpio.yaml b/dts/bindings/gpio/st,stm32mp2-gpio.yaml new file mode 100644 index 000000000000..09b20ce063fb --- /dev/null +++ b/dts/bindings/gpio/st,stm32mp2-gpio.yaml @@ -0,0 +1,23 @@ +# Copyright (C) 2025 Savoir-faire Linux, Inc. +# SPDX-License-Identifier: Apache-2.0 + +description: STM32MP2 GPIO Controller + +compatible: "st,stm32mp2-gpio" + +include: + - name: st,stm32-gpio.yaml + property-blocklist: + - clocks + +properties: + clocks: + type: phandle-array + description: | + The clocks property is optional for STM32MP2 GPIO controllers. + This property is not required when the Cortex-A core is responsible for + GPIO initialization and acts as the resource manager, as defined by the + RIF (Resource Isolation Framework) peripheral. Adding the GPIO clocks + in that case would only trigger an IAC event. + If the Cortex-M core is designated as the resource manager, then the + clocks property must be defined and added to the device tree. diff --git a/include/zephyr/drivers/clock_control/stm32_clock_control.h b/include/zephyr/drivers/clock_control/stm32_clock_control.h index e654ac2860ea..8f242f4af828 100644 --- a/include/zephyr/drivers/clock_control/stm32_clock_control.h +++ b/include/zephyr/drivers/clock_control/stm32_clock_control.h @@ -41,6 +41,8 @@ #elif defined(CONFIG_SOC_SERIES_STM32L4X) || \ defined(CONFIG_SOC_SERIES_STM32L5X) #include +#elif defined(CONFIG_SOC_SERIES_STM32MP2X) +#include #elif defined(CONFIG_SOC_SERIES_STM32WBX) #include #elif defined(CONFIG_SOC_SERIES_STM32WB0X) diff --git a/include/zephyr/dt-bindings/clock/stm32mp2_clock.h b/include/zephyr/dt-bindings/clock/stm32mp2_clock.h new file mode 100644 index 000000000000..8ccffd5e2c70 --- /dev/null +++ b/include/zephyr/dt-bindings/clock/stm32mp2_clock.h @@ -0,0 +1,45 @@ +/* + * Copyright (C) 2025 Savoir-faire Linux, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32MP2_CLOCK_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32MP2_CLOCK_H_ + +#include "stm32_common_clocks.h" + +/* Undefine the common clocks macro */ +#undef STM32_CLOCK + +/** + * Pack RCC clock register offset and bit in two 32-bit values + * as expected for the Device Tree `clocks` property on STM32. + * + * @param per STM32 Peripheral name (expands to STM32_CLOCK_PERIPH_{PER}) + * @param bit Clock bit + */ +#define STM32_CLOCK(per, bit) (STM32_CLOCK_PERIPH_##per) (1 << bit) + +/* Clock reg */ +#define STM32_CLK 1U +#define STM32_LP_CLK 2U + +/* GPIO Peripheral */ +#define STM32_CLOCK_PERIPH_GPIOA 0x52C +#define STM32_CLOCK_PERIPH_GPIOB 0x530 +#define STM32_CLOCK_PERIPH_GPIOC 0x534 +#define STM32_CLOCK_PERIPH_GPIOD 0x538 +#define STM32_CLOCK_PERIPH_GPIOE 0x53C +#define STM32_CLOCK_PERIPH_GPIOF 0x540 +#define STM32_CLOCK_PERIPH_GPIOG 0x544 +#define STM32_CLOCK_PERIPH_GPIOH 0x548 +#define STM32_CLOCK_PERIPH_GPIOI 0x54C +#define STM32_CLOCK_PERIPH_GPIOJ 0x550 +#define STM32_CLOCK_PERIPH_GPIOK 0x554 +#define STM32_CLOCK_PERIPH_GPIOZ 0x558 + +#define STM32_CLOCK_PERIPH_MIN STM32_CLOCK_PERIPH_GPIOA +#define STM32_CLOCK_PERIPH_MAX STM32_CLOCK_PERIPH_GPIOZ + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32MP2_CLOCK_H_ */ diff --git a/soc/st/stm32/soc.yml b/soc/st/stm32/soc.yml index 705097b35782..a3f781c3beed 100644 --- a/soc/st/stm32/soc.yml +++ b/soc/st/stm32/soc.yml @@ -193,6 +193,11 @@ family: - name: stm32mp13x socs: - name: stm32mp135fxx + - name: stm32mp2x + socs: + - name: stm32mp257fxx + cpuclusters: + - name: m33 - name: stm32n6x socs: - name: stm32n657xx diff --git a/soc/st/stm32/stm32mp2x/CMakeLists.txt b/soc/st/stm32/stm32mp2x/CMakeLists.txt new file mode 100644 index 000000000000..fdfdc3244a73 --- /dev/null +++ b/soc/st/stm32/stm32mp2x/CMakeLists.txt @@ -0,0 +1,9 @@ +# Copyright (C) 2025 Savoir-faire Linux, Inc. +# +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) + +if(CONFIG_CPU_CORTEX_M33) + add_subdirectory(m33) +endif() diff --git a/soc/st/stm32/stm32mp2x/Kconfig b/soc/st/stm32/stm32mp2x/Kconfig new file mode 100644 index 000000000000..016ee4ad2072 --- /dev/null +++ b/soc/st/stm32/stm32mp2x/Kconfig @@ -0,0 +1,17 @@ +# STMicroelectronics STM32MP2 MPU series +# +# Copyright (C) 2025 Savoir-faire Linux, Inc. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_STM32MP2X + select ARM + select CPU_HAS_FPU + select HAS_STM32CUBE + +config SOC_STM32MP2X_M33 + select ARMV8_M_DSP + select ARM_TRUSTZONE_M + select CPU_CORTEX_M33 + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_ARM_MPU + select CPU_HAS_ARM_SAU diff --git a/soc/st/stm32/stm32mp2x/Kconfig.defconfig b/soc/st/stm32/stm32mp2x/Kconfig.defconfig new file mode 100644 index 000000000000..144368d8e1bd --- /dev/null +++ b/soc/st/stm32/stm32mp2x/Kconfig.defconfig @@ -0,0 +1,10 @@ +# STMicroelectronics STM32MP2 MPU series +# +# Copyright (C) 2025 Savoir-faire Linux, Inc. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_STM32MP2X + +rsource "Kconfig.defconfig.stm32mp2*" + +endif # SOC_SERIES_STM32MP2X diff --git a/soc/st/stm32/stm32mp2x/Kconfig.defconfig.stm32mp257fxx b/soc/st/stm32/stm32mp2x/Kconfig.defconfig.stm32mp257fxx new file mode 100644 index 000000000000..57a77780ee9b --- /dev/null +++ b/soc/st/stm32/stm32mp2x/Kconfig.defconfig.stm32mp257fxx @@ -0,0 +1,11 @@ +# STMicroelectronics STM32MP2 MPU series +# +# Copyright (C) 2025 Savoir-faire Linux, Inc. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_STM32MP2X_M33 + +config NUM_IRQS + default 320 + +endif # SOC_STM32MP2X_M33 diff --git a/soc/st/stm32/stm32mp2x/Kconfig.soc b/soc/st/stm32/stm32mp2x/Kconfig.soc new file mode 100644 index 000000000000..92825e7a0c56 --- /dev/null +++ b/soc/st/stm32/stm32mp2x/Kconfig.soc @@ -0,0 +1,18 @@ +# STMicroelectronics STM32MP2 MPU series +# +# Copyright (C) 2025 Savoir-faire Linux, Inc. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_STM32MP2X + bool + select SOC_FAMILY_STM32 + +config SOC_SERIES + default "stm32mp2x" if SOC_SERIES_STM32MP2X + +config SOC_STM32MP2X_M33 + bool + select SOC_SERIES_STM32MP2X + +config SOC + default "stm32mp257fxx" if SOC_STM32MP2X_M33 diff --git a/soc/st/stm32/stm32mp2x/m33/CMakeLists.txt b/soc/st/stm32/stm32mp2x/m33/CMakeLists.txt new file mode 100644 index 000000000000..1b3edbb52211 --- /dev/null +++ b/soc/st/stm32/stm32mp2x/m33/CMakeLists.txt @@ -0,0 +1,9 @@ +# Copyright (C) 2025 Savoir-faire Linux, Inc. +# +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(${ZEPHYR_BASE}/drivers) + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/st/stm32/stm32mp2x/m33/linker.ld b/soc/st/stm32/stm32mp2x/m33/linker.ld new file mode 100644 index 000000000000..6b963d31e93b --- /dev/null +++ b/soc/st/stm32/stm32mp2x/m33/linker.ld @@ -0,0 +1,21 @@ +/* linker.ld - Linker command/script file */ + +/* + * Copyright (C) 2025 Savoir-faire Linux, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#define rom_start .isr_vectors + +#include + +SECTIONS +{ + /* Standard Zephyr relocation section */ +#include + +#ifdef CONFIG_LLEXT +#include +#endif +} diff --git a/soc/st/stm32/stm32mp2x/m33/soc.h b/soc/st/stm32/stm32mp2x/m33/soc.h new file mode 100644 index 000000000000..c517d443c676 --- /dev/null +++ b/soc/st/stm32/stm32mp2x/m33/soc.h @@ -0,0 +1,25 @@ +/* + * Copyright (C) 2025 Savoir-faire Linux, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file SoC configuration macros for the STM32MP2 family processors. + * + * Based on reference manual: + * STM32MP23/25xx advanced ARM(r)-based 32/64-bit MPUs + * + * Chapter 2.4.2: Memory map and register boundary addresses + */ + +#ifndef _STM32MP2_M33_SOC_H_ +#define _STM32MP2_M33_SOC_H_ + +#ifndef _ASMLANGUAGE + +#include + +#endif /* !_ASMLANGUAGE */ + +#endif /* !_STM32MP2_M33_SOC_H_ */ diff --git a/west.yml b/west.yml index f043bcedf7e3..be90e69982d2 100644 --- a/west.yml +++ b/west.yml @@ -245,7 +245,7 @@ manifest: groups: - hal - name: hal_stm32 - revision: 5cbc642b1a79d4f373b1587f8c3027f31bf0d30c + revision: 468e5ad450a75d4baa3eed80e4f77a7700b71203 path: modules/hal/stm32 groups: - hal