diff --git a/boards/st/stm32mp135f_dk/stm32mp135f_dk.dts b/boards/st/stm32mp135f_dk/stm32mp135f_dk.dts
index 3c853de283151..b5814fca00a70 100644
--- a/boards/st/stm32mp135f_dk/stm32mp135f_dk.dts
+++ b/boards/st/stm32mp135f_dk/stm32mp135f_dk.dts
@@ -85,7 +85,7 @@
 	div-m = <2>;
 	mul-n = <83>;
 	div-p = <1>;
-	frac-v = <2730>;
+	fracn = <2730>;
 	status = "okay";
 };
 
diff --git a/drivers/clock_control/clock_stm32_ll_mp13.c b/drivers/clock_control/clock_stm32_ll_mp13.c
index 09f7fed1abcb1..b543ae195a613 100644
--- a/drivers/clock_control/clock_stm32_ll_mp13.c
+++ b/drivers/clock_control/clock_stm32_ll_mp13.c
@@ -17,6 +17,29 @@
 #include <zephyr/drivers/clock_control/stm32_clock_control.h>
 #include <zephyr/sys/util.h>
 
+/** @brief Verifies clock is part of active clock configuration */
+int enabled_clock(uint32_t src_clk)
+{
+	if ((src_clk == STM32_SRC_HSE && IS_ENABLED(STM32_HSE_ENABLED)) ||
+	    (src_clk == STM32_SRC_HSI && IS_ENABLED(STM32_HSI_ENABLED)) ||
+	    (src_clk == STM32_SRC_LSE && IS_ENABLED(STM32_LSE_ENABLED)) ||
+	    (src_clk == STM32_SRC_LSI && IS_ENABLED(STM32_LSI_ENABLED)) ||
+	    (src_clk == STM32_SRC_PLL1_P && IS_ENABLED(STM32_PLL_P_ENABLED)) ||
+	    (src_clk == STM32_SRC_PLL2_P && IS_ENABLED(STM32_PLL2_P_ENABLED)) ||
+	    (src_clk == STM32_SRC_PLL2_Q && IS_ENABLED(STM32_PLL2_Q_ENABLED)) ||
+	    (src_clk == STM32_SRC_PLL2_R && IS_ENABLED(STM32_PLL2_R_ENABLED)) ||
+	    (src_clk == STM32_SRC_PLL3_P && IS_ENABLED(STM32_PLL3_P_ENABLED)) ||
+	    (src_clk == STM32_SRC_PLL3_Q && IS_ENABLED(STM32_PLL3_Q_ENABLED)) ||
+	    (src_clk == STM32_SRC_PLL3_R && IS_ENABLED(STM32_PLL3_R_ENABLED)) ||
+	    (src_clk == STM32_SRC_PLL4_P && IS_ENABLED(STM32_PLL4_P_ENABLED)) ||
+	    (src_clk == STM32_SRC_PLL4_Q && IS_ENABLED(STM32_PLL4_Q_ENABLED)) ||
+	    (src_clk == STM32_SRC_PLL4_R && IS_ENABLED(STM32_PLL4_R_ENABLED))) {
+		return 0;
+	}
+
+	return -ENOTSUP;
+}
+
 static int stm32_clock_control_on(const struct device *dev, clock_control_subsys_t sub_system)
 {
 	struct stm32_pclken *pclken = (struct stm32_pclken *)sub_system;
@@ -57,6 +80,32 @@ static int stm32_clock_control_off(const struct device *dev, clock_control_subsy
 	return 0;
 }
 
+static int stm32_clock_control_configure(const struct device *dev,
+					 clock_control_subsys_t sub_system,
+					 void *data)
+{
+	struct stm32_pclken *pclken = (struct stm32_pclken *)(sub_system);
+	int err;
+
+	ARG_UNUSED(dev);
+	ARG_UNUSED(data);
+
+	err = enabled_clock(pclken->bus);
+	if (err < 0) {
+		/* Attempt to configure a src clock not available or not valid */
+		return err;
+	}
+
+	sys_clear_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_DT_CLKSEL_REG_GET(pclken->enr),
+		       STM32_DT_CLKSEL_MASK_GET(pclken->enr) <<
+			STM32_DT_CLKSEL_SHIFT_GET(pclken->enr));
+	sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_DT_CLKSEL_REG_GET(pclken->enr),
+		     STM32_DT_CLKSEL_VAL_GET(pclken->enr) <<
+			STM32_DT_CLKSEL_SHIFT_GET(pclken->enr));
+
+	return 0;
+}
+
 static int stm32_clock_control_get_subsys_rate(const struct device *dev,
 					       clock_control_subsys_t sub_system, uint32_t *rate)
 {
@@ -99,10 +148,37 @@ static int stm32_clock_control_get_subsys_rate(const struct device *dev,
 	return 0;
 }
 
+static enum clock_control_status stm32_clock_control_get_status(const struct device *dev,
+								clock_control_subsys_t sub_system)
+{
+	struct stm32_pclken *pclken = (struct stm32_pclken *)sub_system;
+
+	ARG_UNUSED(dev);
+
+	if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX)) {
+		/* Gated clocks */
+		if ((sys_read32(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus) & pclken->enr)
+		    == pclken->enr) {
+			return CLOCK_CONTROL_STATUS_ON;
+		} else {
+			return CLOCK_CONTROL_STATUS_OFF;
+		}
+	} else {
+		/* Domain clock sources */
+		if (enabled_clock(pclken->bus) == 0) {
+			return CLOCK_CONTROL_STATUS_ON;
+		} else {
+			return CLOCK_CONTROL_STATUS_OFF;
+		}
+	}
+}
+
 static DEVICE_API(clock_control, stm32_clock_control_api) = {
 	.on = stm32_clock_control_on,
 	.off = stm32_clock_control_off,
 	.get_rate = stm32_clock_control_get_subsys_rate,
+	.configure = stm32_clock_control_configure,
+	.get_status = stm32_clock_control_get_status,
 };
 
 static void set_up_fixed_clock_sources(void)
@@ -173,7 +249,7 @@ static int stm32_clock_control_init(const struct device *dev)
 	uint32_t pll1_n = DT_PROP(DT_NODELABEL(pll1), mul_n);
 	uint32_t pll1_m = DT_PROP(DT_NODELABEL(pll1), div_m);
 	uint32_t pll1_p = DT_PROP(DT_NODELABEL(pll1), div_p);
-	uint32_t pll1_v = DT_PROP(DT_NODELABEL(pll1), frac_v);
+	uint32_t pll1_fracn = DT_PROP(DT_NODELABEL(pll1), fracn);
 
 	LL_RCC_PLL1_SetN(pll1_n);
 	while (LL_RCC_PLL1_GetN() != pll1_n) {
@@ -184,8 +260,8 @@ static int stm32_clock_control_init(const struct device *dev)
 	LL_RCC_PLL1_SetP(pll1_p);
 	while (LL_RCC_PLL1_GetP() != pll1_p) {
 	}
-	LL_RCC_PLL1_SetFRACV(pll1_v);
-	while (LL_RCC_PLL1_GetFRACV() != pll1_v) {
+	LL_RCC_PLL1_SetFRACV(pll1_fracn);
+	while (LL_RCC_PLL1_GetFRACV() != pll1_fracn) {
 	}
 
 	LL_RCC_PLL1_Enable();
diff --git a/drivers/clock_control/clock_stm32_mco.c b/drivers/clock_control/clock_stm32_mco.c
index 1a524d74c59b2..e94c054e02f7f 100644
--- a/drivers/clock_control/clock_stm32_mco.c
+++ b/drivers/clock_control/clock_stm32_mco.c
@@ -49,6 +49,11 @@ static int stm32_mco_init(const struct device *dev)
 		STM32_DT_CLKSEL_VAL_GET(pclken->enr) <<
 			STM32_DT_CLKSEL_SHIFT_GET(pclken->enr));
 
+#if defined(MCOX_ON)
+	sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_DT_CLKSEL_REG_GET(pclken->enr),
+		     MCOX_ON);
+#endif
+
 #if defined(HAS_PRESCALER)
 	/* MCO prescaler */
 	sys_clear_bits(
diff --git a/dts/arm/st/mp13/stm32mp13.dtsi b/dts/arm/st/mp13/stm32mp13.dtsi
index 4955d034cf491..b700623723146 100644
--- a/dts/arm/st/mp13/stm32mp13.dtsi
+++ b/dts/arm/st/mp13/stm32mp13.dtsi
@@ -27,6 +27,18 @@
 		};
 	};
 
+	mcos {
+		mco1: mco1 {
+			compatible = "st,stm32-clock-mco";
+			status = "disabled";
+		};
+
+		mco2: mco2 {
+			compatible = "st,stm32-clock-mco";
+			status = "disabled";
+		};
+	};
+
 	soc {
 		interrupt-parent = <&gic>;
 
@@ -278,6 +290,24 @@
 			compatible = "st,stm32mp13-pll-clock";
 			status = "disabled";
 		};
+
+		pll2: pll2 {
+			#clock-cells = <0>;
+			compatible = "st,stm32mp13-pll-clock";
+			status = "disabled";
+		};
+
+		pll3: pll3 {
+			#clock-cells = <0>;
+			compatible = "st,stm32mp13-pll-clock";
+			status = "disabled";
+		};
+
+		pll4: pll4 {
+			#clock-cells = <0>;
+			compatible = "st,stm32mp13-pll-clock";
+			status = "disabled";
+		};
 	};
 
 	timer {
diff --git a/dts/bindings/clock/st,stm32mp13-pll-clock.yaml b/dts/bindings/clock/st,stm32mp13-pll-clock.yaml
index 5128ea05f0d8e..3ac441d662b99 100644
--- a/dts/bindings/clock/st,stm32mp13-pll-clock.yaml
+++ b/dts/bindings/clock/st,stm32mp13-pll-clock.yaml
@@ -28,6 +28,14 @@ description: |
   than 1000 MHz or program the mpuss_ck mux to use the MPUDIV
   (refer to the stm32mp13 reference manual for details)
 
+  div-m (aka DIVM1 + 1), div-p (aka DIVP + 1), div-q (aka DIVQ + 1),
+  div-r (aka DIVR + 1) have identical valid ranges for all 4 PLLs.
+  mul-n (aka DIVN + 1) valid range depends on the PLL
+    PLL1: 31 - 125
+    PLL2: 25 - 100
+    PLL3: 25 - 200
+    PLL4: 25 - 200
+
 compatible: "st,stm32mp13-pll-clock"
 
 include: [clock-controller.yaml, base.yaml]
@@ -44,25 +52,36 @@ properties:
     type: int
     required: true
     description: |
-        Prescaler for PLLx
-        input clock
+        PLLx division factor (aka DIVM1 + 1) of the input clock divider
         Valid range: 1 - 64
 
   mul-n:
     type: int
     required: true
     description: |
-        PLLx multiplication factor for VCO
-        Valid range: 31 - 125
+        PLLx multiplication factor (aka DIVN + 1) for VCO
+        Valid range: 25 - 200
 
   div-p:
     type: int
     description: |
-        PLLx DIVP division factor
+        PLLx_P division factor (aka DIVP + 1)
+        Valid range: 1 - 128
+
+  div-q:
+    type: int
+    description: |
+        PLLx_Q division factor (aka DIVQ + 1)
+        Valid range: 1 - 128
+
+  div-r:
+    type: int
+    description: |
+        PLLx_R division factor (aka DIVR + 1)
         Valid range: 1 - 128
 
-  frac-v:
+  fracn:
     type: int
     description: |
         PLLx FRACV fractional latch
-        Valid range: 1 - 8192
+        Valid range: 0 - 8191
diff --git a/include/zephyr/drivers/clock_control/stm32_clock_control.h b/include/zephyr/drivers/clock_control/stm32_clock_control.h
index 49c74d1922bf1..e654ac2860ea7 100644
--- a/include/zephyr/drivers/clock_control/stm32_clock_control.h
+++ b/include/zephyr/drivers/clock_control/stm32_clock_control.h
@@ -179,7 +179,8 @@
 	DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32wb_pll_clock, okay)  || \
 	DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32wba_pll_clock, okay) || \
 	DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32h7_pll_clock, okay) || \
-	DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32h7rs_pll_clock, okay)
+	DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32h7rs_pll_clock, okay) || \
+	DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32mp13_pll_clock, okay)
 #define STM32_PLL_ENABLED	1
 #define STM32_PLL_M_DIVISOR	DT_PROP(DT_NODELABEL(pll), div_m)
 #define STM32_PLL_N_MULTIPLIER	DT_PROP(DT_NODELABEL(pll), mul_n)
@@ -215,7 +216,8 @@
 
 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll2), st_stm32u5_pll_clock, okay) || \
 	DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll2), st_stm32h7_pll_clock, okay) || \
-	DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll2), st_stm32h7rs_pll_clock, okay)
+	DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll2), st_stm32h7rs_pll_clock, okay) || \
+	DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll2), st_stm32mp13_pll_clock, okay)
 #define STM32_PLL2_ENABLED	1
 #define STM32_PLL2_M_DIVISOR	DT_PROP(DT_NODELABEL(pll2), div_m)
 #define STM32_PLL2_N_MULTIPLIER	DT_PROP(DT_NODELABEL(pll2), mul_n)
@@ -235,7 +237,8 @@
 
 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll3), st_stm32h7_pll_clock, okay) || \
 	DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll3), st_stm32u5_pll_clock, okay) || \
-	DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll3), st_stm32h7rs_pll_clock, okay)
+	DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll3), st_stm32h7rs_pll_clock, okay) || \
+	DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll3), st_stm32mp13_pll_clock, okay)
 #define STM32_PLL3_ENABLED	1
 #define STM32_PLL3_M_DIVISOR	DT_PROP(DT_NODELABEL(pll3), div_m)
 #define STM32_PLL3_N_MULTIPLIER	DT_PROP(DT_NODELABEL(pll3), mul_n)
@@ -251,6 +254,20 @@
 #define STM32_PLL3_FRACN_VALUE	DT_PROP_OR(DT_NODELABEL(pll3), fracn, 1)
 #endif
 
+#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll4), st_stm32mp13_pll_clock, okay)
+#define STM32_PLL4_ENABLED	1
+#define STM32_PLL4_M_DIVISOR	DT_PROP(DT_NODELABEL(pll4), div_m)
+#define STM32_PLL4_N_MULTIPLIER	DT_PROP(DT_NODELABEL(pll4), mul_n)
+#define STM32_PLL4_P_ENABLED	DT_NODE_HAS_PROP(DT_NODELABEL(pll4), div_p)
+#define STM32_PLL4_P_DIVISOR	DT_PROP_OR(DT_NODELABEL(pll4), div_p, 1)
+#define STM32_PLL4_Q_ENABLED	DT_NODE_HAS_PROP(DT_NODELABEL(pll4), div_q)
+#define STM32_PLL4_Q_DIVISOR	DT_PROP_OR(DT_NODELABEL(pll4), div_q, 1)
+#define STM32_PLL4_R_ENABLED	DT_NODE_HAS_PROP(DT_NODELABEL(pll4), div_r)
+#define STM32_PLL4_R_DIVISOR	DT_PROP_OR(DT_NODELABEL(pll4), div_r, 1)
+#define STM32_PLL4_FRACN_ENABLED	DT_NODE_HAS_PROP(DT_NODELABEL(pll4), fracn)
+#define STM32_PLL4_FRACN_VALUE	DT_PROP_OR(DT_NODELABEL(pll4), fracn, 1)
+#endif
+
 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f1_pll_clock, okay)
 #define STM32_PLL_ENABLED	1
 #define STM32_PLL_XTPRE		DT_PROP(DT_NODELABEL(pll), xtpre)
diff --git a/include/zephyr/dt-bindings/clock/stm32mp13_clock.h b/include/zephyr/dt-bindings/clock/stm32mp13_clock.h
index 207b5793a055b..887436424f685 100644
--- a/include/zephyr/dt-bindings/clock/stm32mp13_clock.h
+++ b/include/zephyr/dt-bindings/clock/stm32mp13_clock.h
@@ -8,6 +8,24 @@
 
 #include "stm32_common_clocks.h"
 
+/** System clock */
+/* defined in stm32_common_clocks.h */
+/** Fixed clocks  */
+#define STM32_SRC_HSE		(STM32_SRC_LSI + 1)
+#define STM32_SRC_HSI		(STM32_SRC_HSE + 1)
+
+/** PLL outputs */
+#define STM32_SRC_PLL1_P	(STM32_SRC_HSI + 1)
+#define STM32_SRC_PLL2_P	(STM32_SRC_PLL1_P + 1)
+#define STM32_SRC_PLL2_Q	(STM32_SRC_PLL2_P + 1)
+#define STM32_SRC_PLL2_R	(STM32_SRC_PLL2_Q + 1)
+#define STM32_SRC_PLL3_P	(STM32_SRC_PLL2_R + 1)
+#define STM32_SRC_PLL3_Q	(STM32_SRC_PLL3_P + 1)
+#define STM32_SRC_PLL3_R	(STM32_SRC_PLL3_Q + 1)
+#define STM32_SRC_PLL4_P	(STM32_SRC_PLL3_R + 1)
+#define STM32_SRC_PLL4_Q	(STM32_SRC_PLL4_P + 1)
+#define STM32_SRC_PLL4_R	(STM32_SRC_PLL4_Q + 1)
+
 /** Bus clocks */
 #define STM32_CLOCK_BUS_APB1    0x700
 #define STM32_CLOCK_BUS_APB2    0x708
@@ -24,4 +42,113 @@
 #define STM32_PERIPH_BUS_MIN	STM32_CLOCK_BUS_APB1
 #define STM32_PERIPH_BUS_MAX	STM32_CLOCK_BUS_AHB6
 
+/** @brief Device domain clocks selection helpers */
+#define MCO1CFGR_REG		0x460
+#define MCO2CFGR_REG		0x464
+#define I2C12CKSELR_REG		0x600
+#define I2C345CKSELR_REG	0x604
+#define SPI2S1CKSELR_REG	0x608
+#define SPI2S23CKSELR_REG	0x60c
+#define SPI45CKSELR_REG		0x610
+#define UART12CKSELR_REG	0x614
+#define UART35CKSELR_REG	0x618
+#define UART4CKSELR_REG		0x61c
+#define UART6CKSELR_REG		0x620
+#define UART78CKSELR_REG	0x624
+#define LPTIM1CKSELR_REG	0x628
+#define LPTIM23CKSELR_REG	0x62c
+#define LPTIM45CKSELR_REG	0x630
+#define SAI1CKSELR_REG		0x634
+#define SAI2CKSELR_REG		0x638
+#define FDCANCKSELR_REG		0x63c
+#define SPDIFCKSELR_REG		0x640
+#define ADC12CKSELR_REG		0x644
+#define SDMMC12CKSELR_REG	0x648
+#define ETH12CKSELR_REG		0x64c
+#define USBCKSELR_REG		0x650
+#define QSPICKSELR_REG		0x654
+#define FMCCKSELR_REG		0x658
+#define RNG1CKSELR_REG		0x65c
+#define STGENCKSELR_REG		0x660
+#define DCMIPPCKSELR_REG	0x664
+#define SAESCKSELR_REG		0x668
+
+/** MCO1CFGR / MCO2CFGR devices */
+#define MCO1_SEL(val)		STM32_DT_CLOCK_SELECT((val), 0x7, 0, MCO1CFGR_REG)
+#define MCO1_PRE(val)		STM32_DT_CLOCK_SELECT((val), 0xf, 4, MCO1CFGR_REG)
+#define MCO2_SEL(val)		STM32_DT_CLOCK_SELECT((val), 0x7, 0, MCO2CFGR_REG)
+#define MCO2_PRE(val)		STM32_DT_CLOCK_SELECT((val), 0xf, 4, MCO2CFGR_REG)
+
+#define MCOX_ON	BIT(12)
+
+/* MCO1 source */
+#define MCO1_SEL_HSI	0
+#define MCO1_SEL_HSE	1
+#define MCO1_SEL_CSI	2
+#define MCO1_SEL_LSI	3
+#define MCO1_SEL_LSE	4
+
+/* MCO2 source */
+#define MCO2_SEL_MPU	0
+#define MCO2_SEL_AXI	1
+#define MCO2_SEL_MLAHB	2
+#define MCO2_SEL_PLL4	3
+#define MCO2_SEL_HSE	4
+#define MCO2_SEL_HSI	5
+
+/* MCO prescaler : division factor */
+#define MCO_PRE_DIV_1	0
+#define MCO_PRE_DIV_2	1
+#define MCO_PRE_DIV_3	2
+#define MCO_PRE_DIV_4	3
+#define MCO_PRE_DIV_5	4
+#define MCO_PRE_DIV_6	5
+#define MCO_PRE_DIV_7	6
+#define MCO_PRE_DIV_8	7
+#define MCO_PRE_DIV_9	8
+#define MCO_PRE_DIV_10	9
+#define MCO_PRE_DIV_11	10
+#define MCO_PRE_DIV_12	11
+#define MCO_PRE_DIV_13	12
+#define MCO_PRE_DIV_14	13
+#define MCO_PRE_DIV_15	14
+#define MCO_PRE_DIV_16	15
+
+#define I2C12_SEL(val)		STM32_DT_CLOCK_SELECT((val), 0x7, 0, I2C12CKSELR_REG)
+#define I2C3_SEL(val)		STM32_DT_CLOCK_SELECT((val), 0x7, 0, I2C345CKSELR_REG)
+#define I2C4_SEL(val)		STM32_DT_CLOCK_SELECT((val), 0x7, 3, I2C345CKSELR_REG)
+#define I2C5_SEL(val)		STM32_DT_CLOCK_SELECT((val), 0x7, 6, I2C345CKSELR_REG)
+#define SPI1_SEL(val)		STM32_DT_CLOCK_SELECT((val), 0x7, 0, SPI2S1CKSELR_REG)
+#define SPI23_SEL(val)		STM32_DT_CLOCK_SELECT((val), 0x7, 0, SPI2S23CKSELR_REG)
+#define SPI4_SEL(val)		STM32_DT_CLOCK_SELECT((val), 0x7, 0, SPI45CKSELR_REG)
+#define SPI5_SEL(val)		STM32_DT_CLOCK_SELECT((val), 0x7, 3, SPI45CKSELR_REG)
+#define UART1_SEL(val)		STM32_DT_CLOCK_SELECT((val), 0x7, 0, UART12CKSELR_REG)
+#define UART2_SEL(val)		STM32_DT_CLOCK_SELECT((val), 0x7, 3, UART12CKSELR_REG)
+#define UART35_SEL(val)		STM32_DT_CLOCK_SELECT((val), 0x7, 0, UART35CKSELR_REG)
+#define UART4_SEL(val)		STM32_DT_CLOCK_SELECT((val), 0x7, 0, UART4CKSELR_REG)
+#define UART6_SEL(val)		STM32_DT_CLOCK_SELECT((val), 0x7, 0, UART6CKSELR_REG)
+#define UART78_SEL(val)		STM32_DT_CLOCK_SELECT((val), 0x7, 0, UART78CKSELR_REG)
+#define LPTIME1_SEL(val)	STM32_DT_CLOCK_SELECT((val), 0x7, 0, LPTIM1CKSELR_REG)
+#define LPTIME2_SEL(val)	STM32_DT_CLOCK_SELECT((val), 0x7, 0, LPTIM23CKSELR_REG)
+#define LPTIME3_SEL(val)	STM32_DT_CLOCK_SELECT((val), 0x7, 3, LPTIM23CKSELR_REG)
+#define LPTIME45_SEL(val)	STM32_DT_CLOCK_SELECT((val), 0x7, 0, LPTIM45CKSELR_REG)
+#define SAI1_SEL(val)		STM32_DT_CLOCK_SELECT((val), 0x7, 0, SAI1CKSELR_REG)
+#define SAI2_SEL(val)		STM32_DT_CLOCK_SELECT((val), 0x7, 0, SAI2CKSELR_REG)
+#define FDCAN_SEL(val)		STM32_DT_CLOCK_SELECT((val), 0x3, 0, FDCANCKSELR_REG)
+#define SPDIF_SEL(val)		STM32_DT_CLOCK_SELECT((val), 0x3, 0, SPDIFCKSELR_REG)
+#define ADC1_SEL(val)		STM32_DT_CLOCK_SELECT((val), 0x3, 0, ADC12CKSELR_REG)
+#define ADC2_SEL(val)		STM32_DT_CLOCK_SELECT((val), 0x3, 2, ADC12CKSELR_REG)
+#define SDMMC1_SEL(val)		STM32_DT_CLOCK_SELECT((val), 0x7, 0, SDMMC12CKSELR_REG)
+#define SDMMC2_SEL(val)		STM32_DT_CLOCK_SELECT((val), 0x7, 3, SDMMC12CKSELR_REG)
+#define ETH1_SEL(val)		STM32_DT_CLOCK_SELECT((val), 0x3, 0, ETH12CKSELR_REG)
+#define ETH2_SEL(val)		STM32_DT_CLOCK_SELECT((val), 0x3, 8, ETH12CKSELR_REG)
+#define USBPHY_SEL(val)		STM32_DT_CLOCK_SELECT((val), 0x3, 0, USBCKSELR_REG)
+#define USBOTG_SEL(val)		STM32_DT_CLOCK_SELECT((val), 0x1, 4, USBCKSELR_REG)
+#define QSPI_SEL(val)		STM32_DT_CLOCK_SELECT((val), 0x3, 0, QSPICKSELR_REG)
+#define FMC_SEL(val)		STM32_DT_CLOCK_SELECT((val), 0x3, 0, FMCCKSELR_REG)
+#define RNG1_SEL(val)		STM32_DT_CLOCK_SELECT((val), 0x3, 0, RNG1CKSELR_REG)
+#define STGEN_SEL(val)		STM32_DT_CLOCK_SELECT((val), 0x3, 0, STGENCKSELR_REG)
+#define DCMIPP_SEL(val)		STM32_DT_CLOCK_SELECT((val), 0x3, 0, DCMIPPCKSELR_REG)
+#define SAES_SEL(val)		STM32_DT_CLOCK_SELECT((val), 0x3, 0, SAESCKSELR_REG)
+
 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32MP13_CLOCK_H_ */