From dab3769e2a8aa0aad8cdb77ff4671e1392f30034 Mon Sep 17 00:00:00 2001 From: Michael Hope Date: Sat, 26 Apr 2025 18:29:35 +0000 Subject: [PATCH] drivers: pinctrl: enable the AFIO clock on the CH32V003/20x/30x The Alternate Function IO (AFIO) block must have the clock enabled before configuring. Some remappings seem to work without, but some like EXTI do not. Fix. Signed-off-by: Michael Hope --- drivers/pinctrl/pinctrl_wch_20x_30x_afio.c | 13 +++++++++++++ drivers/pinctrl/pinctrl_wch_afio.c | 17 +++++++++++++---- dts/riscv/wch/ch32v0/ch32v003.dtsi | 1 + dts/riscv/wch/ch32v208/ch32v208.dtsi | 1 + 4 files changed, 28 insertions(+), 4 deletions(-) diff --git a/drivers/pinctrl/pinctrl_wch_20x_30x_afio.c b/drivers/pinctrl/pinctrl_wch_20x_30x_afio.c index ae22af8b648d..f7d216ceed1a 100644 --- a/drivers/pinctrl/pinctrl_wch_20x_30x_afio.c +++ b/drivers/pinctrl/pinctrl_wch_20x_30x_afio.c @@ -4,6 +4,9 @@ * SPDX-License-Identifier: Apache-2.0 */ +#define DT_DRV_COMPAT wch_20x_30x_afio + +#include #include #include @@ -87,3 +90,13 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintp return 0; } + +static int pinctrl_clock_init(void) +{ + const struct device *clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(0)); + uint8_t clock_id = DT_INST_CLOCKS_CELL(0, id); + + return clock_control_on(clock_dev, (clock_control_subsys_t *)(uintptr_t)clock_id); +} + +SYS_INIT(pinctrl_clock_init, PRE_KERNEL_1, 0); diff --git a/drivers/pinctrl/pinctrl_wch_afio.c b/drivers/pinctrl/pinctrl_wch_afio.c index 4a56787d5650..2d46cc42ad5b 100644 --- a/drivers/pinctrl/pinctrl_wch_afio.c +++ b/drivers/pinctrl/pinctrl_wch_afio.c @@ -4,6 +4,9 @@ * SPDX-License-Identifier: Apache-2.0 */ +#define DT_DRV_COMPAT wch_afio + +#include #include #include @@ -28,10 +31,6 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintp uint32_t pcfr1 = AFIO->PCFR1; uint8_t cfg = 0; - if (remap != 0) { - RCC->APB2PCENR |= RCC_AFIOEN; - } - if (pins->output_high || pins->output_low) { cfg |= (pins->slew_rate + 1); if (pins->drive_open_drain) { @@ -77,3 +76,13 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintp return 0; } + +static int pinctrl_clock_init(void) +{ + const struct device *clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(0)); + uint8_t clock_id = DT_INST_CLOCKS_CELL(0, id); + + return clock_control_on(clock_dev, (clock_control_subsys_t *)(uintptr_t)clock_id); +} + +SYS_INIT(pinctrl_clock_init, PRE_KERNEL_1, 0); diff --git a/dts/riscv/wch/ch32v0/ch32v003.dtsi b/dts/riscv/wch/ch32v0/ch32v003.dtsi index 12f5305ff53b..121d4d64d965 100644 --- a/dts/riscv/wch/ch32v0/ch32v003.dtsi +++ b/dts/riscv/wch/ch32v0/ch32v003.dtsi @@ -77,6 +77,7 @@ reg = <0x40010000 0x10>; #address-cells = <1>; #size-cells = <1>; + clocks = <&rcc CH32V00X_CLOCK_AFIO>; status = "okay"; gpioa: gpio@40010800 { diff --git a/dts/riscv/wch/ch32v208/ch32v208.dtsi b/dts/riscv/wch/ch32v208/ch32v208.dtsi index b1e03ecc147b..5ad9c971f36b 100644 --- a/dts/riscv/wch/ch32v208/ch32v208.dtsi +++ b/dts/riscv/wch/ch32v208/ch32v208.dtsi @@ -76,6 +76,7 @@ reg = <0x40010000 16>; #address-cells = <1>; #size-cells = <1>; + clocks = <&rcc CH32V20X_V30X_CLOCK_AFIO>; gpioa: gpio@40010800 { compatible = "wch,gpio";