From 0b16b757b582975e88536a9ae2a782b27e18e453 Mon Sep 17 00:00:00 2001 From: Emilio Benavente Date: Fri, 4 Apr 2025 09:38:25 -0500 Subject: [PATCH 1/3] Initial Idea, need to test with arduino sheild --- .../nxp/frdm_mcxw71/frdm_mcxw71-pinctrl.dtsi | 11 +++++++ boards/nxp/frdm_mcxw71/frdm_mcxw71.dts | 30 +++++++++++-------- .../clock_control/clock_control_mcux_scg_k4.c | 3 ++ dts/arm/nxp/nxp_mcxw7x_common.dtsi | 13 ++++++++ include/zephyr/dt-bindings/clock/scg_k4.h | 1 + soc/nxp/mcx/mcxw/soc.c | 6 ++++ 6 files changed, 52 insertions(+), 12 deletions(-) diff --git a/boards/nxp/frdm_mcxw71/frdm_mcxw71-pinctrl.dtsi b/boards/nxp/frdm_mcxw71/frdm_mcxw71-pinctrl.dtsi index e1b876ee0b094..a5e78d5f3c508 100644 --- a/boards/nxp/frdm_mcxw71/frdm_mcxw71-pinctrl.dtsi +++ b/boards/nxp/frdm_mcxw71/frdm_mcxw71-pinctrl.dtsi @@ -80,4 +80,15 @@ slew-rate = "fast"; }; }; + + pinmux_i3c: pinmux_i3c { + group0 { + pinmux = , + ; + input-enable; + bias-pull-up; + slew-rate = "slow"; + drive-strength = "low"; + }; + }; }; diff --git a/boards/nxp/frdm_mcxw71/frdm_mcxw71.dts b/boards/nxp/frdm_mcxw71/frdm_mcxw71.dts index 9948163023989..35ef4e86451c5 100644 --- a/boards/nxp/frdm_mcxw71/frdm_mcxw71.dts +++ b/boards/nxp/frdm_mcxw71/frdm_mcxw71.dts @@ -8,6 +8,7 @@ #include #include "frdm_mcxw71-pinctrl.dtsi" #include +#include / { model = "NXP FRDM-MCXW71 board"; @@ -18,6 +19,7 @@ blue-pwm-led = &blue_pwm_led; green-pwm-led = &green_pwm_led; red-pwm-led = &red_pwm_led; + ambient-temp0 = &p3t1755; }; chosen { @@ -90,18 +92,6 @@ pinctrl-names = "default"; }; -&lpi2c1 { - status = "okay"; - pinctrl-0 = <&pinmux_lpi2c1>; - pinctrl-names = "default"; - - accelerometer: accelerometer@19 { - status = "okay"; - compatible = "nxp,fxls8974"; - reg = <0x19>; - }; -}; - &lpspi1 { status = "okay"; pinctrl-0 = <&pinmux_lpspi1>; @@ -191,3 +181,19 @@ &rtc { status = "okay"; }; + +&i3c0 { + pinctrl-0 = <&pinmux_i3c>; + pinctrl-names = "default"; + status = "okay"; + + i2c-scl-hz = ; + i3c-scl-hz = ; + i3c-od-scl-hz = ; + + p3t1755: p3t1755@4800000236152a0090 { + compatible = "nxp,p3t1755"; + reg = <0x48 0x0236 0x152a0090>; + status = "okay"; + }; +}; diff --git a/drivers/clock_control/clock_control_mcux_scg_k4.c b/drivers/clock_control/clock_control_mcux_scg_k4.c index 57db831e86797..2817c8d85d3ea 100644 --- a/drivers/clock_control/clock_control_mcux_scg_k4.c +++ b/drivers/clock_control/clock_control_mcux_scg_k4.c @@ -64,6 +64,9 @@ static int mcux_scg_k4_get_rate(const struct device *dev, clock_control_subsys_t case SCG_K4_RTCOSC_CLK: clock_name = kCLOCK_RtcOscClk; break; + case SCG_K4_I3C_CLK: + *rate = CLOCK_GetIpFreq(kCLOCK_I3c0); + return 0; default: LOG_ERR("Unsupported clock name"); return -EINVAL; diff --git a/dts/arm/nxp/nxp_mcxw7x_common.dtsi b/dts/arm/nxp/nxp_mcxw7x_common.dtsi index 7e0a42c405726..ca578343811e7 100644 --- a/dts/arm/nxp/nxp_mcxw7x_common.dtsi +++ b/dts/arm/nxp/nxp_mcxw7x_common.dtsi @@ -343,6 +343,19 @@ clock-frequency = <32768>; prescaler = <32768>; }; + + i3c0: i3c@40035000 { + compatible = "nxp,mcux-i3c"; + reg = <0x40035000 0xFFF>; + interrupts = <41 0>; + clocks = <&scg SCG_K4_I3C_CLK 0xd4>; + clk-divider = <4>; + clk-divider-slow = <1>; + clk-divider-tc = <1>; + status = "disabled"; + #address-cells = <3>; + #size-cells = <0>; + }; }; &fast_peripheral0 { diff --git a/include/zephyr/dt-bindings/clock/scg_k4.h b/include/zephyr/dt-bindings/clock/scg_k4.h index 985629a1f6972..4471ac0c73087 100644 --- a/include/zephyr/dt-bindings/clock/scg_k4.h +++ b/include/zephyr/dt-bindings/clock/scg_k4.h @@ -12,3 +12,4 @@ #define SCG_K4_SIRC_CLK 6U #define SCG_K4_FIRC_CLK 7U #define SCG_K4_RTCOSC_CLK 8U +#define SCG_K4_I3C_CLK 9U diff --git a/soc/nxp/mcx/mcxw/soc.c b/soc/nxp/mcx/mcxw/soc.c index 94b22710234db..0cee40571e431 100644 --- a/soc/nxp/mcx/mcxw/soc.c +++ b/soc/nxp/mcx/mcxw/soc.c @@ -131,6 +131,8 @@ __weak void clock_init(void) CLOCK_SetIpSrc(kCLOCK_Lpspi1, kCLOCK_IpSrcFro192M); CLOCK_SetIpSrc(kCLOCK_Lpadc0, kCLOCK_IpSrcFro192M); CLOCK_SetIpSrcDiv(kCLOCK_Lpadc0, kSCG_SysClkDivBy10); + CLOCK_SetIpSrc(kCLOCK_I3c0, kCLOCK_IpSrcFro192M); + CLOCK_SetIpSrcDiv(kCLOCK_I3c0, kSCG_SysClkDivBy16); /* Ungate clocks if the peripheral is enabled in devicetree */ if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(gpioa), nxp_kinetis_gpio, okay)) { @@ -188,6 +190,10 @@ __weak void clock_init(void) if (DT_NODE_HAS_COMPAT_STATUS(adc0, nxp_lpadc, okay)) { CLOCK_EnableClock(kCLOCK_Lpadc0); } + + if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(i3c0), nxp_mcux_i3c, okay)) { + CLOCK_EnableClock(kCLOCK_I3c0); + } } static void vbat_init(void) From a965099dea2a1b121a69340be0022d50a1e078b9 Mon Sep 17 00:00:00 2001 From: Emilio Benavente Date: Mon, 14 Apr 2025 16:20:54 -0500 Subject: [PATCH 2/3] changes 2 --- boards/nxp/frdm_mcxw71/frdm_mcxw71-pinctrl.dtsi | 4 ++-- boards/nxp/frdm_mcxw71/frdm_mcxw71.yaml | 1 + dts/arm/nxp/nxp_mcxw7x_common.dtsi | 2 +- 3 files changed, 4 insertions(+), 3 deletions(-) diff --git a/boards/nxp/frdm_mcxw71/frdm_mcxw71-pinctrl.dtsi b/boards/nxp/frdm_mcxw71/frdm_mcxw71-pinctrl.dtsi index a5e78d5f3c508..b9ae421a10385 100644 --- a/boards/nxp/frdm_mcxw71/frdm_mcxw71-pinctrl.dtsi +++ b/boards/nxp/frdm_mcxw71/frdm_mcxw71-pinctrl.dtsi @@ -85,10 +85,10 @@ group0 { pinmux = , ; + slew-rate = "fast"; + drive-strength = "low"; input-enable; bias-pull-up; - slew-rate = "slow"; - drive-strength = "low"; }; }; }; diff --git a/boards/nxp/frdm_mcxw71/frdm_mcxw71.yaml b/boards/nxp/frdm_mcxw71/frdm_mcxw71.yaml index 24b5be8c10f1a..c723c374ef89f 100644 --- a/boards/nxp/frdm_mcxw71/frdm_mcxw71.yaml +++ b/boards/nxp/frdm_mcxw71/frdm_mcxw71.yaml @@ -14,6 +14,7 @@ supported: - flash - gpio - i2c + - i3c - pinctrl - pwm - regulator diff --git a/dts/arm/nxp/nxp_mcxw7x_common.dtsi b/dts/arm/nxp/nxp_mcxw7x_common.dtsi index ca578343811e7..bd54f9b7c769a 100644 --- a/dts/arm/nxp/nxp_mcxw7x_common.dtsi +++ b/dts/arm/nxp/nxp_mcxw7x_common.dtsi @@ -349,7 +349,7 @@ reg = <0x40035000 0xFFF>; interrupts = <41 0>; clocks = <&scg SCG_K4_I3C_CLK 0xd4>; - clk-divider = <4>; + clk-divider = <6>; clk-divider-slow = <1>; clk-divider-tc = <1>; status = "disabled"; From 474a2279b6c38dc2ee05e2e4aebf0f5298e42864 Mon Sep 17 00:00:00 2001 From: Emilio Benavente Date: Sun, 20 Apr 2025 10:12:42 -0500 Subject: [PATCH 3/3] attempt to change peripheral clock freq to pass sample --- .../nxp/frdm_mcxw71/frdm_mcxw71-pinctrl.dtsi | 6 +++++ boards/nxp/frdm_mcxw71/frdm_mcxw71.dts | 13 ++------- .../boards/frdm_mcxw71.overlay | 27 +++++++++++++++++++ dts/arm/nxp/nxp_mcxw7x_common.dtsi | 2 +- samples/sensor/thermometer/sample.yaml | 1 + soc/nxp/mcx/mcxw/soc.c | 2 +- 6 files changed, 38 insertions(+), 13 deletions(-) create mode 100644 boards/shields/p3t1755dp_ard_i3c/boards/frdm_mcxw71.overlay diff --git a/boards/nxp/frdm_mcxw71/frdm_mcxw71-pinctrl.dtsi b/boards/nxp/frdm_mcxw71/frdm_mcxw71-pinctrl.dtsi index b9ae421a10385..9cc0c225688c6 100644 --- a/boards/nxp/frdm_mcxw71/frdm_mcxw71-pinctrl.dtsi +++ b/boards/nxp/frdm_mcxw71/frdm_mcxw71-pinctrl.dtsi @@ -90,5 +90,11 @@ input-enable; bias-pull-up; }; + group1 { + pinmux = ; + slew-rate = "fast"; + drive-strength = "low"; + input-enable; + }; }; }; diff --git a/boards/nxp/frdm_mcxw71/frdm_mcxw71.dts b/boards/nxp/frdm_mcxw71/frdm_mcxw71.dts index 35ef4e86451c5..062b4b155d511 100644 --- a/boards/nxp/frdm_mcxw71/frdm_mcxw71.dts +++ b/boards/nxp/frdm_mcxw71/frdm_mcxw71.dts @@ -185,15 +185,6 @@ &i3c0 { pinctrl-0 = <&pinmux_i3c>; pinctrl-names = "default"; - status = "okay"; - - i2c-scl-hz = ; - i3c-scl-hz = ; - i3c-od-scl-hz = ; - - p3t1755: p3t1755@4800000236152a0090 { - compatible = "nxp,p3t1755"; - reg = <0x48 0x0236 0x152a0090>; - status = "okay"; - }; }; + +p3t1755dp_ard_i3c_interface: &i3c0 {}; diff --git a/boards/shields/p3t1755dp_ard_i3c/boards/frdm_mcxw71.overlay b/boards/shields/p3t1755dp_ard_i3c/boards/frdm_mcxw71.overlay new file mode 100644 index 0000000000000..4c91e72680abf --- /dev/null +++ b/boards/shields/p3t1755dp_ard_i3c/boards/frdm_mcxw71.overlay @@ -0,0 +1,27 @@ +/* + * Copyright 2025 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* + * The p3t1755 shield board is plugged into the arduino interface on + * the FRDM-MCXW71 board, and the J13 on the shield board is connected + * to the J22 on the MCXW71 referred below. + * J13-1 -> J22-8; J13-2 -> J22-6; + * J13-3 -> J22-1; J13-4 -> J22-10; + */ + +#include + +&i3c0 { + status = "okay"; + + i2c-scl-hz = ; + i3c-scl-hz = ; + i3c-od-scl-hz = ; +}; + +&lpi2c1 { + status = "disabled"; +}; diff --git a/dts/arm/nxp/nxp_mcxw7x_common.dtsi b/dts/arm/nxp/nxp_mcxw7x_common.dtsi index bd54f9b7c769a..16c75e71119b1 100644 --- a/dts/arm/nxp/nxp_mcxw7x_common.dtsi +++ b/dts/arm/nxp/nxp_mcxw7x_common.dtsi @@ -349,7 +349,7 @@ reg = <0x40035000 0xFFF>; interrupts = <41 0>; clocks = <&scg SCG_K4_I3C_CLK 0xd4>; - clk-divider = <6>; + clk-divider = <15>; clk-divider-slow = <1>; clk-divider-tc = <1>; status = "disabled"; diff --git a/samples/sensor/thermometer/sample.yaml b/samples/sensor/thermometer/sample.yaml index c482ee6dc34ae..3a782885db8c0 100644 --- a/samples/sensor/thermometer/sample.yaml +++ b/samples/sensor/thermometer/sample.yaml @@ -42,3 +42,4 @@ tests: - platform:mimxrt1180_evk/mimxrt1189/cm33:SHIELD=p3t1755dp_ard_i3c - platform:mimxrt1180_evk/mimxrt1189/cm7:SHIELD=p3t1755dp_ard_i3c - platform:frdm_mcxn236/mcxn236:SHIELD=p3t1755dp_ard_i3c + - platform:frdm_mcxw71:SHIELD=p3t1755dp_ard_i3c diff --git a/soc/nxp/mcx/mcxw/soc.c b/soc/nxp/mcx/mcxw/soc.c index 0cee40571e431..402423e732e44 100644 --- a/soc/nxp/mcx/mcxw/soc.c +++ b/soc/nxp/mcx/mcxw/soc.c @@ -132,7 +132,7 @@ __weak void clock_init(void) CLOCK_SetIpSrc(kCLOCK_Lpadc0, kCLOCK_IpSrcFro192M); CLOCK_SetIpSrcDiv(kCLOCK_Lpadc0, kSCG_SysClkDivBy10); CLOCK_SetIpSrc(kCLOCK_I3c0, kCLOCK_IpSrcFro192M); - CLOCK_SetIpSrcDiv(kCLOCK_I3c0, kSCG_SysClkDivBy16); + CLOCK_SetIpSrcDiv(kCLOCK_I3c0, DT_PROP(DT_NODELABEL(i3c0), clk_divider)); /* Ungate clocks if the peripheral is enabled in devicetree */ if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(gpioa), nxp_kinetis_gpio, okay)) {