From 197adf4348ec441cdbdc5a60f0623b011a8db4da Mon Sep 17 00:00:00 2001 From: Duy Vo Date: Mon, 17 Mar 2025 13:06:39 +0700 Subject: [PATCH 1/9] drivers: crc: initial support for CRC driver - Implement CRC syscall. - Add CRC driver API. - Introduce support for the CRC driver. Co-authored-by: Zoe Kaute Signed-off-by: Duy Vo --- MAINTAINERS.yml | 13 ++ doc/hardware/peripherals/crc.rst | 23 +++ doc/hardware/peripherals/index.rst | 1 + drivers/CMakeLists.txt | 1 + drivers/Kconfig | 1 + drivers/crc/CMakeLists.txt | 8 + drivers/crc/Kconfig | 100 ++++++++++ drivers/crc/Kconfig.renesas_ra | 20 ++ drivers/crc/crc_renesas_ra.c | 283 +++++++++++++++++++++++++++ dts/bindings/crc/renesas,ra-crc.yaml | 15 ++ include/zephyr/drivers/crc.h | 176 +++++++++++++++++ modules/Kconfig.renesas | 5 + 12 files changed, 646 insertions(+) create mode 100644 doc/hardware/peripherals/crc.rst create mode 100644 drivers/crc/CMakeLists.txt create mode 100644 drivers/crc/Kconfig create mode 100644 drivers/crc/Kconfig.renesas_ra create mode 100644 drivers/crc/crc_renesas_ra.c create mode 100644 dts/bindings/crc/renesas,ra-crc.yaml create mode 100644 include/zephyr/drivers/crc.h diff --git a/MAINTAINERS.yml b/MAINTAINERS.yml index 86fbc7cd783c5..1c1b769e9f50f 100644 --- a/MAINTAINERS.yml +++ b/MAINTAINERS.yml @@ -1304,6 +1304,19 @@ Release Notes: tests: - crypto +"Drivers: CRC": + status: maintained + maintainers: + - thenguyenyf + files: + - drivers/crc/ + - dts/bindings/crc/ + - include/zephyr/drivers/crc.h + - samples/drivers/crc/ + - tests/drivers/crc/ + labels: + - "area: CRC" + "Drivers: DAC": status: maintained maintainers: diff --git a/doc/hardware/peripherals/crc.rst b/doc/hardware/peripherals/crc.rst new file mode 100644 index 0000000000000..13525c87861c5 --- /dev/null +++ b/doc/hardware/peripherals/crc.rst @@ -0,0 +1,23 @@ +.. _crc_api: + +Cyclic Redundancy Check (CRC) +############################# + +Overview +******** + +The Cyclic Redundancy Check (CRC) API provides functions for configuring and +computing CRC values on hardware. + +Configuration Options +********************* + +Related configuration options: + +* :kconfig:option:`CRC_HW` +* :kconfig:option:`CRC_INIT_PRIORITY` + +API Reference +************* + +.. doxygengroup:: crc_interface diff --git a/doc/hardware/peripherals/index.rst b/doc/hardware/peripherals/index.rst index 9a4d7e9edfeee..ee64d0a7110e9 100644 --- a/doc/hardware/peripherals/index.rst +++ b/doc/hardware/peripherals/index.rst @@ -21,6 +21,7 @@ Peripherals comparator.rst coredump.rst counter.rst + crc.rst dac.rst dma.rst display/index.rst diff --git a/drivers/CMakeLists.txt b/drivers/CMakeLists.txt index 6838f74642605..c2d90adf82e9e 100644 --- a/drivers/CMakeLists.txt +++ b/drivers/CMakeLists.txt @@ -28,6 +28,7 @@ add_subdirectory_ifdef(CONFIG_COMPARATOR comparator) add_subdirectory_ifdef(CONFIG_CONSOLE console) add_subdirectory_ifdef(CONFIG_COREDUMP_DEVICE coredump) add_subdirectory_ifdef(CONFIG_COUNTER counter) +add_subdirectory_ifdef(CONFIG_CRC_DRIVER crc) add_subdirectory_ifdef(CONFIG_CRYPTO crypto) add_subdirectory_ifdef(CONFIG_DAC dac) add_subdirectory_ifdef(CONFIG_DAI dai) diff --git a/drivers/Kconfig b/drivers/Kconfig index 2e71fecfb5fcc..e8c12e4111b17 100644 --- a/drivers/Kconfig +++ b/drivers/Kconfig @@ -20,6 +20,7 @@ source "drivers/comparator/Kconfig" source "drivers/console/Kconfig" source "drivers/coredump/Kconfig" source "drivers/counter/Kconfig" +source "drivers/crc/Kconfig" source "drivers/crypto/Kconfig" source "drivers/dac/Kconfig" source "drivers/dai/Kconfig" diff --git a/drivers/crc/CMakeLists.txt b/drivers/crc/CMakeLists.txt new file mode 100644 index 0000000000000..86a26f6bcfa2b --- /dev/null +++ b/drivers/crc/CMakeLists.txt @@ -0,0 +1,8 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +zephyr_syscall_header(${ZEPHYR_BASE}/include/zephyr/drivers/crc.h) + +zephyr_library() + +zephyr_library_sources_ifdef(CONFIG_CRC_DRIVER_RENESAS_RA crc_renesas_ra.c) diff --git a/drivers/crc/Kconfig b/drivers/crc/Kconfig new file mode 100644 index 0000000000000..c57d376ca26e9 --- /dev/null +++ b/drivers/crc/Kconfig @@ -0,0 +1,100 @@ +# Copyright (c) 2024 Brill Power Ltd. +# SPDX-License-Identifier: Apache-2.0 + +menuconfig CRC_DRIVER + bool "CRC device drivers" + help + Enable support for CRC device driver. + +if CRC_DRIVER + +module = CRC_DRIVER +module-str = CRC_DRIVER + +source "subsys/logging/Kconfig.template.log_config" + +config CRC_DRIVER_INIT_PRIORITY + int "CRC init priority" + default KERNEL_INIT_PRIORITY_DEVICE + help + CRC driver device initialization priority. + +source "drivers/crc/Kconfig.renesas_ra" + +config CRC_DRIVER_HAS_CRC4 + bool + help + CRC driver has CRC4 computation + +config CRC_DRIVER_HAS_CRC4_TI + bool + help + CRC driver has CRC4 TI computation + +config CRC_DRIVER_HAS_CRC7_BE + bool + help + CRC driver has CRC7 BE computation + +config CRC_DRIVER_HAS_CRC8 + bool + help + CRC driver has CRC8 computation + +config CRC_DRIVER_HAS_CRC8_CCITT + bool + help + CRC driver has CRC8 CCITT computation + +config CRC_DRIVER_HAS_CRC8_ROHC + bool + help + CRC driver has CRC8 ROHC computation + +config CRC_DRIVER_HAS_CRC16 + bool + help + CRC driver has CRC16 computation + +config CRC_DRIVER_HAS_CRC16_CCITT + bool + help + CRC driver has CRC16 CCITT computation + +config CRC_DRIVER_HAS_CRC16_ITU_T + bool + help + CRC driver has CRC16 ITU-T computation + +config CRC_DRIVER_HAS_CRC16_ANSI + bool + depends on CRC_DRIVER_HAS_CRC16_REFLECT + help + CRC driver has CRC16 Ansi computation + +config CRC_DRIVER_HAS_CRC16_REFLECT + bool + help + CRC driver has CRC16 reflect computation + +config CRC_DRIVER_HAS_CRC24_PGP + bool + help + CRC driver has CRC24 PGP computation + +config CRC_DRIVER_HAS_CRC32_C + bool + help + CRC driver has CRC32C computation + +config CRC_DRIVER_HAS_CRC32_IEEE + bool + help + CRC driver has CRC32 IEEE computation + +config CRC_DRIVER_HAS_CRC32_K_4_2 + bool + help + CRC driver has CRC32K/4.2 computation + +endif # CRC_DEVICE diff --git a/drivers/crc/Kconfig.renesas_ra b/drivers/crc/Kconfig.renesas_ra new file mode 100644 index 0000000000000..0568b6fb542b1 --- /dev/null +++ b/drivers/crc/Kconfig.renesas_ra @@ -0,0 +1,20 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config CRC_DRIVER_RENESAS_RA + bool + depends on DT_HAS_RENESAS_RA_CRC_ENABLED + default y + select CRC_DRIVER_HAS_CRC8 + select CRC_DRIVER_HAS_CRC8_ROHC + select CRC_DRIVER_HAS_CRC8_CCITT + select CRC_DRIVER_HAS_CRC16 + select CRC_DRIVER_HAS_CRC16_CCITT + select CRC_DRIVER_HAS_CRC16_ANSI + select CRC_DRIVER_HAS_CRC16_ITU_T + select CRC_DRIVER_HAS_CRC16_REFLECT + select CRC_DRIVER_HAS_CRC32_C + select CRC_DRIVER_HAS_CRC32_IEEE + select USE_RA_FSP_CRC + help + Enable the driver implementation for Renesas RA microcontrollers diff --git a/drivers/crc/crc_renesas_ra.c b/drivers/crc/crc_renesas_ra.c new file mode 100644 index 0000000000000..fb5453ab305bc --- /dev/null +++ b/drivers/crc/crc_renesas_ra.c @@ -0,0 +1,283 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +LOG_MODULE_REGISTER(renesas_ra_crc, CONFIG_CRC_LOG_LEVEL); + +#include +#include + +#include +#include "r_crc.h" +#include "rp_crc.h" + +#define DT_DRV_COMPAT renesas_ra_crc +#define DEFAULT_NUM_BYTES (4U) +#define DEFAULT_SEED_VALUE (0x00000000) + +struct crc_renesas_ra_cfg { + const struct device *clock_dev; + const struct clock_control_ra_subsys_cfg clock_id; +}; + +struct crc_renesas_ra_data { + struct st_crc_instance_ctrl ctrl; + struct st_crc_input_t input_data; + struct st_crc_cfg crc_config; + struct k_sem sem; + bool flag_crc_updated; +}; + +static void crc_lock(const struct device *dev) +{ + struct crc_renesas_ra_data *data = dev->data; + + k_sem_take(&data->sem, K_FOREVER); +} + +static void crc_unlock(const struct device *dev) +{ + struct crc_renesas_ra_data *data = dev->data; + + k_sem_give(&data->sem); +} + +static int crc_set_config(const struct device *dev, struct crc_ctx *ctx) +{ + fsp_err_t err; + struct crc_renesas_ra_data *data = dev->data; + crc_cfg_t const *const crc_cfg = &data->crc_config; + + data->crc_config.bit_order = (ctx->reversed & CRC_FLAG_REVERSE_OUTPUT) + ? CRC_BIT_ORDER_LMS_LSB + : CRC_BIT_ORDER_LMS_MSB; + + switch (ctx->type) { + case CRC8: { + if ((ctx->polynomial != CRC8_POLY) && (ctx->polynomial != CRC8_REFLECT_POLY)) { + return -EINVAL; + } + + data->crc_config.polynomial = CRC_POLYNOMIAL_CRC_8; + break; + } + case CRC16: { + if (ctx->polynomial != CRC16_POLY) { + return -EINVAL; + } + + data->crc_config.polynomial = CRC_POLYNOMIAL_CRC_16; + break; + } + case CRC16_CCITT: { + if (ctx->polynomial != CRC16_CCITT_POLY) { + return -EINVAL; + } + + data->crc_config.polynomial = CRC_POLYNOMIAL_CRC_CCITT; + break; + } + case CRC32_C: { + if (ctx->polynomial != CRC32C_POLY) { + return -EINVAL; + } + + data->crc_config.polynomial = CRC_POLYNOMIAL_CRC_32C; + break; + } + case CRC32_IEEE: { + if (ctx->polynomial != CRC32_IEEE_POLY) { + return -EINVAL; + } + + data->crc_config.polynomial = CRC_POLYNOMIAL_CRC_32; + break; + } + default: + return -ENOTSUP; + } + + err = RP_CRC_Reconfigure(&data->ctrl, crc_cfg); + + if (err != FSP_SUCCESS) { + ctx->state = CRC_STATE_IDLE; + crc_unlock(dev); + return -EINVAL; + } + + return 0; +} + +static int crc_renesas_ra_begin(const struct device *dev, struct crc_ctx *ctx) +{ + int ret; + + crc_lock(dev); + + ret = crc_set_config(dev, ctx); + if (ret != 0) { + crc_unlock(dev); + return ret; + } + + ctx->state = CRC_STATE_IN_PROGRESS; + + return 0; +} + +static int crc_renesas_ra_update(const struct device *dev, struct crc_ctx *ctx, const void *buffer, + size_t bufsize) +{ + struct crc_renesas_ra_data *data = dev->data; + fsp_err_t err; + uint32_t init_val; + + /* Ensure CRC calculation has been initialized by crc_begin() */ + if (ctx->state == CRC_STATE_IDLE) { + return -EINVAL; + } + + switch (ctx->type) { + case CRC8: + __fallthrough; + case CRC16: + __fallthrough; + case CRC16_CCITT: { + if (ctx->type == CRC8) { + init_val = (data->flag_crc_updated ? ctx->result : ctx->seed) & 0xFF; + } else { + init_val = (data->flag_crc_updated ? ctx->result : ctx->seed) & 0xFFFF; + } + + data->input_data.num_bytes = bufsize; + data->input_data.crc_seed = init_val; + data->input_data.p_input_buffer = (uint8_t *)buffer; + + err = R_CRC_Calculate(&data->ctrl, &data->input_data, &ctx->result); + if (err != FSP_SUCCESS) { + ctx->state = CRC_STATE_IDLE; + crc_unlock(dev); + return -EINVAL; + } + break; + } + default: { + init_val = (data->flag_crc_updated ? ctx->result : ctx->seed) & 0xFFFFFFFF; + + if ((bufsize % 4) != 0) { + ctx->state = CRC_STATE_IDLE; + crc_unlock(dev); + return -ENOTSUP; + } + + data->input_data.num_bytes = bufsize; + data->input_data.crc_seed = init_val; + data->input_data.p_input_buffer = (uint8_t *)buffer; + + err = R_CRC_Calculate(&data->ctrl, &data->input_data, &ctx->result); + if (err != FSP_SUCCESS) { + ctx->state = CRC_STATE_IDLE; + crc_unlock(dev); + return -EINVAL; + } + + if (ctx->type == CRC32_IEEE) { + ctx->result = (crc_result_t)~ctx->result; + } + break; + } + } + + data->flag_crc_updated = true; + + return 0; +} + +static int crc_renesas_ra_finish(const struct device *dev, struct crc_ctx *ctx) +{ + struct crc_renesas_ra_data *data = dev->data; + + if (ctx->state == CRC_STATE_IDLE) { + return -EINVAL; + } + + ctx->state = CRC_STATE_IDLE; + + data->flag_crc_updated = false; + + crc_unlock(dev); + + return 0; +} + +static int crc_ra_init(const struct device *dev) +{ + int ret; + fsp_err_t err; + const struct crc_renesas_ra_cfg *cfg = dev->config; + struct crc_renesas_ra_data *data = dev->data; + crc_cfg_t const *const crc_cfg = &data->crc_config; + + if (!device_is_ready(cfg->clock_dev)) { + LOG_ERR("CRC: Clock control device not ready"); + return -ENODEV; + } + + ret = clock_control_on(cfg->clock_dev, (clock_control_subsys_t)&cfg->clock_id); + if (ret < 0) { + LOG_ERR("CRC: Clock control device could not initialize"); + return -EIO; + } + + err = R_CRC_Open(&data->ctrl, crc_cfg); + if (err != FSP_SUCCESS) { + return -EINVAL; + } + + k_sem_init(&data->sem, 1, 1); + + return 0; +} + +static DEVICE_API(crc, crc_renesas_ra_driver_api) = { + .begin = crc_renesas_ra_begin, + .update = crc_renesas_ra_update, + .finish = crc_renesas_ra_finish, +}; + +#define CRC_RA_INIT_CFG(idx) \ + static const struct crc_renesas_ra_cfg crc_renesas_ra_cfg_##idx = { \ + .clock_dev = DEVICE_DT_GET(DT_CLOCKS_CTLR(DT_DRV_INST(idx))), \ + .clock_id = \ + { \ + .mstp = DT_CLOCKS_CELL_BY_IDX(DT_DRV_INST(idx), 0, mstp), \ + .stop_bit = DT_CLOCKS_CELL_BY_IDX(DT_DRV_INST(idx), 0, stop_bit), \ + }, \ + }; + +#define CRC_RA_INIT(idx) \ + CRC_RA_INIT_CFG(idx); \ + \ + static struct crc_renesas_ra_data crc_renesas_ra_data_##idx = { \ + .input_data = \ + { \ + .num_bytes = DEFAULT_NUM_BYTES, \ + .crc_seed = DEFAULT_SEED_VALUE, \ + .p_input_buffer = NULL, \ + }, \ + .crc_config = \ + { \ + .bit_order = CRC_BIT_ORDER_LMS_LSB, \ + .polynomial = CRC_POLYNOMIAL_CRC_32, \ + }, \ + .flag_crc_updated = false, \ + }; \ + \ + DEVICE_DT_INST_DEFINE(idx, crc_ra_init, NULL, &crc_renesas_ra_data_##idx, \ + &crc_renesas_ra_cfg_##idx, POST_KERNEL, \ + CONFIG_CRC_DRIVER_INIT_PRIORITY, &crc_renesas_ra_driver_api); + +DT_INST_FOREACH_STATUS_OKAY(CRC_RA_INIT) diff --git a/dts/bindings/crc/renesas,ra-crc.yaml b/dts/bindings/crc/renesas,ra-crc.yaml new file mode 100644 index 0000000000000..67ad3049993fe --- /dev/null +++ b/dts/bindings/crc/renesas,ra-crc.yaml @@ -0,0 +1,15 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +description: Renesas RA Cyclic Redundancy Check Driver (crc) + +compatible: "renesas,ra-crc" + +include: [base.yaml] + +properties: + reg: + required: true + + clocks: + required: true diff --git a/include/zephyr/drivers/crc.h b/include/zephyr/drivers/crc.h new file mode 100644 index 0000000000000..06597a3ab0f70 --- /dev/null +++ b/include/zephyr/drivers/crc.h @@ -0,0 +1,176 @@ +/* + * Copyright (c) 2024 Brill Power Ltd. + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief CRC public API header file. + */ + +#ifndef ZEPHYR_INCLUDE_DRIVERS_CRC_H +#define ZEPHYR_INCLUDE_DRIVERS_CRC_H + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief CRC driver APIs + * @defgroup crc_interface CRC driver APIs + * @ingroup io_interfaces + * @{ + */ +#define CRC_FLAG_REVERSE_INPUT BIT(0) +#define CRC_FLAG_REVERSE_OUTPUT BIT(1) +#define CRC_FLAG_NO_REVERSE_INPUT BIT(2) +#define CRC_FLAG_NO_REVERSE_OUTPUT BIT(3) + +#define CRC4_INIT_VAL 0x0 +#define CRC4_TI_INIT_VAL 0x0 +#define CRC7_BE_INIT_VAL 0x0 +#define CRC8_INIT_VAL 0x0 +#define CRC8_CCITT_INIT_VAL 0xFF +#define CRC8_ROHC_INIT_VAL 0xFF +#define CRC16_INIT_VAL 0x0 +#define CRC16_ANSI_INIT_VAL 0x0 +#define CRC16_CCITT_INIT_VAL 0x0000 +#define CRC16_ITU_T_INIT_VAL 0x0000 +#define CRC24_PGP_INIT_VALUE 0x00B704CEU +#define CRC32_IEEE_INIT_VAL 0xFFFFFFFFU +#define CRC32_C_INIT_VAL 0xFFFFFFFFU + +#define CRC32C_XOR_OUT 0xFFFFFFFFUL + +/* Define polynomial for CRC */ +#define CRC4_POLY 0x3 +#define CRC4_REFLECT_POLY 0xC +#define CRC7_BE_POLY 0x09 +#define CRC8_POLY 0x07 +#define CRC8_REFLECT_POLY 0xE0 +#define CRC16_POLY 0x8005 +#define CRC16_REFLECT_POLY 0xA001 +#define CRC16_CCITT_POLY 0x1021 +#define CRC24_PGP_POLY 0x01864CFBU +#define CRC32_IEEE_POLY 0x04C11DB7U +#define CRC32C_POLY 0x1EDC6F41U +#define CRC32K_4_2_POLY 0x93A409EBU + +/** + * @brief CRC state enumeration + */ + +enum crc_state { + CRC_STATE_IDLE = 0, + CRC_STATE_IN_PROGRESS +}; + +typedef uint32_t crc_init_val_t; +typedef uint32_t crc_poly_t; +typedef uint32_t crc_result_t; + +/** + * @brief CRC context structure + */ + +struct crc_ctx { + enum crc_type type; + enum crc_state state; + uint32_t reversed; + crc_poly_t polynomial; + crc_init_val_t seed; + crc_result_t result; +}; + +typedef int (*crc_api_begin)(const struct device *dev, struct crc_ctx *ctx); +typedef int (*crc_api_update)(const struct device *dev, struct crc_ctx *ctx, const void *buffer, + size_t bufsize); +typedef int (*crc_api_finish)(const struct device *dev, struct crc_ctx *ctx); + +/** + * @brief CRC driver API structure + */ + +__subsystem struct crc_driver_api { + crc_api_begin begin; + crc_api_update update; + crc_api_finish finish; +}; + +/** + * @brief Configure CRC unit for calculation + * @param dev Pointer to the device structure + * @param ctx Pointer to the CRC context structure + * @retval 0 if successful, negative errno code on failure + */ +__syscall int crc_begin(const struct device *dev, struct crc_ctx *ctx); +static inline int z_impl_crc_begin(const struct device *dev, struct crc_ctx *ctx) +{ + const struct crc_driver_api *api = (const struct crc_driver_api *)dev->api; + + return api->begin(dev, ctx); +} + +/** + * @brief Perform CRC calculation on the provided data buffer and retrieve + * result + * @param dev Pointer to the device structure + * @param ctx Pointer to the CRC context structure + * @param buffer Pointer to input data buffer + * @param bufsize Number of bytes in *buffer + * @retval 0 if successful, negative errno code on failure + */ +__syscall int crc_update(const struct device *dev, struct crc_ctx *ctx, const void *buffer, + size_t bufsize); +static inline int z_impl_crc_update(const struct device *dev, struct crc_ctx *ctx, + const void *buffer, size_t bufsize) +{ + const struct crc_driver_api *api = (const struct crc_driver_api *)dev->api; + + return api->update(dev, ctx, buffer, bufsize); +} + +/** + * @brief Finalize CRC calculation + * @param dev Pointer to the device structure + * @param ctx Pointer to the CRC context structure + * @retval 0 if successful, negative errno code on failure + */ +__syscall int crc_finish(const struct device *dev, struct crc_ctx *ctx); +static inline int z_impl_crc_finish(const struct device *dev, struct crc_ctx *ctx) +{ + const struct crc_driver_api *api = (const struct crc_driver_api *)dev->api; + + return api->finish(dev, ctx); +} + +static inline int crc_verify(struct crc_ctx *ctx, crc_result_t expected) +{ + if (ctx->state == CRC_STATE_IN_PROGRESS) { + return -EBUSY; + } + + crc_result_t res = ctx->result; + + if (expected != res) { + return -EINVAL; + } + return 0; +} +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#include + +#endif /* ZEPHYR_INCLUDE_DRIVERS_CRC_H */ diff --git a/modules/Kconfig.renesas b/modules/Kconfig.renesas index 12a898e2d8e8c..fa8e6f705b7bc 100644 --- a/modules/Kconfig.renesas +++ b/modules/Kconfig.renesas @@ -159,6 +159,11 @@ config USE_RA_FSP_SDHI help Enable RA FSP SDHI driver +config USE_RA_FSP_CRC + bool + help + Enable RA FSP CRC driver + config USE_RA_FSP_DAC bool help From e0ee0e1641d2617b241316d47999e2285a79e870 Mon Sep 17 00:00:00 2001 From: Duy Vo Date: Tue, 11 Mar 2025 15:58:06 +0700 Subject: [PATCH 2/9] dts: arm: renesas: add device tree node for CRC driver Add device tree node for CRC driver on all Renesas MCU Signed-off-by: Duy Vo --- dts/arm/renesas/ra/ra2/ra2l1.dtsi | 7 +++++++ dts/arm/renesas/ra/ra2/ra2xx.dtsi | 7 +++++++ dts/arm/renesas/ra/ra4/r7fa4l1bx.dtsi | 7 +++++++ dts/arm/renesas/ra/ra4/ra4-cm33-common.dtsi | 7 +++++++ dts/arm/renesas/ra/ra4/ra4-cm4-common.dtsi | 7 +++++++ dts/arm/renesas/ra/ra6/ra6-cm33-common.dtsi | 7 +++++++ dts/arm/renesas/ra/ra6/ra6-cm4-common.dtsi | 7 +++++++ dts/arm/renesas/ra/ra8/ra8x1.dtsi | 7 +++++++ 8 files changed, 56 insertions(+) diff --git a/dts/arm/renesas/ra/ra2/ra2l1.dtsi b/dts/arm/renesas/ra/ra2/ra2l1.dtsi index 23bb39e78524b..e5bffa3a35317 100644 --- a/dts/arm/renesas/ra/ra2/ra2l1.dtsi +++ b/dts/arm/renesas/ra/ra2/ra2l1.dtsi @@ -75,6 +75,13 @@ }; }; + crc: crc@40074000{ + compatible = "renesas,ra-crc"; + reg = <0x40074000 0x1000>; + clocks = <&pclkb MSTPC 1>; + status = "disabled"; + }; + ioport0: gpio@40040000 { compatible = "renesas,ra-gpio-ioport"; reg = <0x40040000 0x20>; diff --git a/dts/arm/renesas/ra/ra2/ra2xx.dtsi b/dts/arm/renesas/ra/ra2/ra2xx.dtsi index 2924b028e198f..61364460b3ed8 100644 --- a/dts/arm/renesas/ra/ra2/ra2xx.dtsi +++ b/dts/arm/renesas/ra/ra2/ra2xx.dtsi @@ -285,6 +285,13 @@ }; }; + crc: crc@40074000{ + compatible = "renesas,ra-crc"; + reg = <0x40074000 0x1000>; + clocks = <&pclkb MSTPC 1>; + status = "disabled"; + }; + id_code: id_code@1010018 { compatible = "zephyr,memory-region"; reg = <0x01010018 0x20>; diff --git a/dts/arm/renesas/ra/ra4/r7fa4l1bx.dtsi b/dts/arm/renesas/ra/ra4/r7fa4l1bx.dtsi index dc6725c443afb..113a6d3e39ae1 100644 --- a/dts/arm/renesas/ra/ra4/r7fa4l1bx.dtsi +++ b/dts/arm/renesas/ra/ra4/r7fa4l1bx.dtsi @@ -279,6 +279,13 @@ }; }; + crc: crc@40108000 { + compatible = "renesas,ra-crc"; + reg = <0x40108000 0x1000>; + clocks = <&pclka MSTPC 1>; + status = "disabled"; + }; + iic0: iic0@4009f000 { compatible = "renesas,ra-iic"; channel = <0>; diff --git a/dts/arm/renesas/ra/ra4/ra4-cm33-common.dtsi b/dts/arm/renesas/ra/ra4/ra4-cm33-common.dtsi index c2512d9c76cd3..b05945bd1214d 100644 --- a/dts/arm/renesas/ra/ra4/ra4-cm33-common.dtsi +++ b/dts/arm/renesas/ra/ra4/ra4-cm33-common.dtsi @@ -290,6 +290,13 @@ status = "disabled"; }; + crc: crc@40108000{ + compatible = "renesas,ra-crc"; + reg = <0x40108000 0x1000>; + clocks = <&pclka MSTPC 1>; + status = "disabled"; + }; + dac_global: dac_global@40171000 { compatible = "renesas,ra-dac-global"; reg = <0x40171000 0x10c4>; diff --git a/dts/arm/renesas/ra/ra4/ra4-cm4-common.dtsi b/dts/arm/renesas/ra/ra4/ra4-cm4-common.dtsi index 7319a75f79f6f..74010b0930158 100644 --- a/dts/arm/renesas/ra/ra4/ra4-cm4-common.dtsi +++ b/dts/arm/renesas/ra/ra4/ra4-cm4-common.dtsi @@ -241,6 +241,13 @@ }; }; + crc: crc@40074000{ + compatible = "renesas,ra-crc"; + reg = <0x40074000 0x1000>; + clocks = <&pclka MSTPC 1>; + status = "disabled"; + }; + iic0: iic0@40053000 { compatible = "renesas,ra-iic"; channel = <0>; diff --git a/dts/arm/renesas/ra/ra6/ra6-cm33-common.dtsi b/dts/arm/renesas/ra/ra6/ra6-cm33-common.dtsi index 9625343ec278a..066aca5325da8 100644 --- a/dts/arm/renesas/ra/ra6/ra6-cm33-common.dtsi +++ b/dts/arm/renesas/ra/ra6/ra6-cm33-common.dtsi @@ -287,6 +287,13 @@ status = "disabled"; }; + crc: crc@40108000{ + compatible = "renesas,ra-crc"; + reg = <0x40108000 0x1000>; + clocks = <&pclka MSTPC 1>; + status = "disabled"; + }; + dac_global: dac_global@40171000 { compatible = "renesas,ra-dac-global"; reg = <0x40171000 0x10c4>; diff --git a/dts/arm/renesas/ra/ra6/ra6-cm4-common.dtsi b/dts/arm/renesas/ra/ra6/ra6-cm4-common.dtsi index dd2c9cacddff7..e6ebc88d8512b 100644 --- a/dts/arm/renesas/ra/ra6/ra6-cm4-common.dtsi +++ b/dts/arm/renesas/ra/ra6/ra6-cm4-common.dtsi @@ -306,6 +306,13 @@ status = "disabled"; }; + crc: crc@40074000{ + compatible = "renesas,ra-crc"; + reg = <0x40074000 0x1000>; + clocks = <&pclka MSTPC 1>; + status = "disabled"; + }; + dac_global: dac_global@4005e000 { compatible = "renesas,ra-dac-global"; reg = <0x4005e000 0x10c4>; diff --git a/dts/arm/renesas/ra/ra8/ra8x1.dtsi b/dts/arm/renesas/ra/ra8/ra8x1.dtsi index a6436cbffb83f..9f534cf7a4713 100644 --- a/dts/arm/renesas/ra/ra8/ra8x1.dtsi +++ b/dts/arm/renesas/ra/ra8/ra8x1.dtsi @@ -697,6 +697,13 @@ }; }; + crc: crc@40310000 { + compatible = "renesas,ra-crc"; + reg = <0x40310000 0x100>; + clocks = <&pclka MSTPC 1>; + status = "disabled"; + }; + eth: ethernet@40354100 { compatible = "renesas,ra-ethernet"; reg = <0x40354100 0xfc>; From d8d3f4a148f711998f00c2ad9880d4bcc457a98f Mon Sep 17 00:00:00 2001 From: Duy Vo Date: Tue, 11 Mar 2025 16:00:06 +0700 Subject: [PATCH 3/9] boards: renesas: add CRC dts node for board support Enable and add CRC node to aliases, chosen for all Renesas MCU Signed-off-by: Duy Vo --- boards/renesas/ek_ra2a1/ek_ra2a1.dts | 5 +++++ boards/renesas/ek_ra2a1/ek_ra2a1.yaml | 1 + boards/renesas/ek_ra2l1/ek_ra2l1.dts | 5 +++++ boards/renesas/ek_ra2l1/ek_ra2l1.yaml | 1 + boards/renesas/ek_ra4e2/ek_ra4e2.dts | 5 +++++ boards/renesas/ek_ra4e2/ek_ra4e2.yaml | 1 + boards/renesas/ek_ra4l1/ek_ra4l1.dts | 5 +++++ boards/renesas/ek_ra4l1/ek_ra4l1.yaml | 1 + boards/renesas/ek_ra4m1/ek_ra4m1.dts | 5 +++++ boards/renesas/ek_ra4m1/ek_ra4m1.yaml | 1 + boards/renesas/ek_ra4m2/ek_ra4m2.dts | 5 +++++ boards/renesas/ek_ra4m2/ek_ra4m2.yaml | 1 + boards/renesas/ek_ra4m3/ek_ra4m3.dts | 5 +++++ boards/renesas/ek_ra4m3/ek_ra4m3.yaml | 1 + boards/renesas/ek_ra4w1/ek_ra4w1.dts | 5 +++++ boards/renesas/ek_ra4w1/ek_ra4w1.yaml | 1 + boards/renesas/ek_ra6e2/ek_ra6e2.dts | 5 +++++ boards/renesas/ek_ra6e2/ek_ra6e2.yaml | 1 + boards/renesas/ek_ra6m1/ek_ra6m1.dts | 5 +++++ boards/renesas/ek_ra6m1/ek_ra6m1.yaml | 1 + boards/renesas/ek_ra6m2/ek_ra6m2.dts | 5 +++++ boards/renesas/ek_ra6m2/ek_ra6m2.yaml | 1 + boards/renesas/ek_ra6m3/ek_ra6m3.dts | 5 +++++ boards/renesas/ek_ra6m3/ek_ra6m3.yaml | 1 + boards/renesas/ek_ra6m4/ek_ra6m4.dts | 5 +++++ boards/renesas/ek_ra6m4/ek_ra6m4.yaml | 1 + boards/renesas/ek_ra6m5/ek_ra6m5.dts | 5 +++++ boards/renesas/ek_ra6m5/ek_ra6m5.yaml | 1 + boards/renesas/ek_ra8d1/ek_ra8d1.dts | 5 +++++ boards/renesas/ek_ra8d1/ek_ra8d1.yaml | 1 + boards/renesas/ek_ra8m1/ek_ra8m1.dts | 5 +++++ boards/renesas/ek_ra8m1/ek_ra8m1.yaml | 1 + boards/renesas/fpb_ra4e1/fpb_ra4e1.dts | 5 +++++ boards/renesas/fpb_ra4e1/fpb_ra4e1.yaml | 1 + boards/renesas/fpb_ra6e1/fpb_ra6e1.dts | 5 +++++ boards/renesas/fpb_ra6e1/fpb_ra6e1.yaml | 1 + boards/renesas/fpb_ra6e2/fpb_ra6e2.dts | 5 +++++ boards/renesas/fpb_ra6e2/fpb_ra6e2.yaml | 1 + boards/renesas/mck_ra8t1/mck_ra8t1.dts | 5 +++++ boards/renesas/mck_ra8t1/mck_ra8t1.yaml | 1 + boards/renesas/voice_ra4e1/voice_ra4e1.dts | 5 +++++ boards/renesas/voice_ra4e1/voice_ra4e1.yaml | 1 + 42 files changed, 126 insertions(+) diff --git a/boards/renesas/ek_ra2a1/ek_ra2a1.dts b/boards/renesas/ek_ra2a1/ek_ra2a1.dts index 39d5d372cd96c..a4a60bd2b1153 100644 --- a/boards/renesas/ek_ra2a1/ek_ra2a1.dts +++ b/boards/renesas/ek_ra2a1/ek_ra2a1.dts @@ -21,6 +21,7 @@ zephyr,console = &uart0; zephyr,shell-uart = &uart0; zephyr,entropy = &trng; + zephyr,crc = &crc; }; leds { @@ -120,3 +121,7 @@ &wdt { status = "okay"; }; + +&crc { + status = "okay"; +}; diff --git a/boards/renesas/ek_ra2a1/ek_ra2a1.yaml b/boards/renesas/ek_ra2a1/ek_ra2a1.yaml index 8d0e59f9c7043..fc6a33639a4c6 100644 --- a/boards/renesas/ek_ra2a1/ek_ra2a1.yaml +++ b/boards/renesas/ek_ra2a1/ek_ra2a1.yaml @@ -12,4 +12,5 @@ supported: - uart - watchdog - counter + - crc vendor: renesas diff --git a/boards/renesas/ek_ra2l1/ek_ra2l1.dts b/boards/renesas/ek_ra2l1/ek_ra2l1.dts index af8a217ea40eb..2821bae5c8b6a 100644 --- a/boards/renesas/ek_ra2l1/ek_ra2l1.dts +++ b/boards/renesas/ek_ra2l1/ek_ra2l1.dts @@ -28,6 +28,7 @@ zephyr,console = &uart0; zephyr,shell-uart = &uart0; zephyr,entropy = &trng; + zephyr,crc = &crc; }; leds { @@ -113,3 +114,7 @@ interrupts = <15 1>; status = "okay"; }; + +&crc { + status = "okay"; +}; diff --git a/boards/renesas/ek_ra2l1/ek_ra2l1.yaml b/boards/renesas/ek_ra2l1/ek_ra2l1.yaml index 47e0e079bf2ac..fdd9ba40771bc 100644 --- a/boards/renesas/ek_ra2l1/ek_ra2l1.yaml +++ b/boards/renesas/ek_ra2l1/ek_ra2l1.yaml @@ -11,6 +11,7 @@ supported: - flash - watchdog - counter + - crc vendor: renesas testing: ignore_tags: diff --git a/boards/renesas/ek_ra4e2/ek_ra4e2.dts b/boards/renesas/ek_ra4e2/ek_ra4e2.dts index 6723f22e3315f..820e4b803a23d 100644 --- a/boards/renesas/ek_ra4e2/ek_ra4e2.dts +++ b/boards/renesas/ek_ra4e2/ek_ra4e2.dts @@ -23,6 +23,7 @@ zephyr,shell-uart = &uart0; zephyr,canbus = &canfd0; zephyr,entropy = &trng; + zephyr,crc = &crc; }; leds { @@ -213,3 +214,7 @@ &wdt { status = "okay"; }; + +&crc { + status = "okay"; +}; diff --git a/boards/renesas/ek_ra4e2/ek_ra4e2.yaml b/boards/renesas/ek_ra4e2/ek_ra4e2.yaml index b8f7c201c5719..8d7b490792b7a 100644 --- a/boards/renesas/ek_ra4e2/ek_ra4e2.yaml +++ b/boards/renesas/ek_ra4e2/ek_ra4e2.yaml @@ -13,4 +13,5 @@ supported: - watchdog - counter - i3c + - crc vendor: renesas diff --git a/boards/renesas/ek_ra4l1/ek_ra4l1.dts b/boards/renesas/ek_ra4l1/ek_ra4l1.dts index 3f7e15acd91a4..348c360c8d86e 100644 --- a/boards/renesas/ek_ra4l1/ek_ra4l1.dts +++ b/boards/renesas/ek_ra4l1/ek_ra4l1.dts @@ -22,6 +22,7 @@ zephyr,console = &uart5; zephyr,shell-uart = &uart5; zephyr,canbus = &canfd0; + zephyr,crc = &crc; }; leds { @@ -225,3 +226,7 @@ }; }; }; + +&crc { + status = "okay"; +}; diff --git a/boards/renesas/ek_ra4l1/ek_ra4l1.yaml b/boards/renesas/ek_ra4l1/ek_ra4l1.yaml index c31f23d486924..fa2bb604f85f9 100644 --- a/boards/renesas/ek_ra4l1/ek_ra4l1.yaml +++ b/boards/renesas/ek_ra4l1/ek_ra4l1.yaml @@ -14,4 +14,5 @@ supported: - counter - i2s - i3c + - crc vendor: renesas diff --git a/boards/renesas/ek_ra4m1/ek_ra4m1.dts b/boards/renesas/ek_ra4m1/ek_ra4m1.dts index 054adf4c92517..c19d82e5623ed 100644 --- a/boards/renesas/ek_ra4m1/ek_ra4m1.dts +++ b/boards/renesas/ek_ra4m1/ek_ra4m1.dts @@ -21,6 +21,7 @@ zephyr,console = &uart1; zephyr,shell-uart = &uart1; zephyr,entropy = &trng; + zephyr,crc = &crc; }; leds { @@ -139,3 +140,7 @@ &wdt { status = "okay"; }; + +&crc { + status = "okay"; +}; diff --git a/boards/renesas/ek_ra4m1/ek_ra4m1.yaml b/boards/renesas/ek_ra4m1/ek_ra4m1.yaml index af2564df95f7b..94bb33605d4f6 100644 --- a/boards/renesas/ek_ra4m1/ek_ra4m1.yaml +++ b/boards/renesas/ek_ra4m1/ek_ra4m1.yaml @@ -12,4 +12,5 @@ supported: - uart - watchdog - counter + - crc vendor: renesas diff --git a/boards/renesas/ek_ra4m2/ek_ra4m2.dts b/boards/renesas/ek_ra4m2/ek_ra4m2.dts index a3ade121275a5..4162a9da9a4bc 100644 --- a/boards/renesas/ek_ra4m2/ek_ra4m2.dts +++ b/boards/renesas/ek_ra4m2/ek_ra4m2.dts @@ -22,6 +22,7 @@ zephyr,console = &uart0; zephyr,shell-uart = &uart0; zephyr,entropy = &trng; + zephyr,crc = &crc; }; leds { @@ -188,3 +189,7 @@ &wdt { status = "okay"; }; + +&crc { + status = "okay"; +}; diff --git a/boards/renesas/ek_ra4m2/ek_ra4m2.yaml b/boards/renesas/ek_ra4m2/ek_ra4m2.yaml index 4b36f431cd11d..5159c67cdb6fe 100644 --- a/boards/renesas/ek_ra4m2/ek_ra4m2.yaml +++ b/boards/renesas/ek_ra4m2/ek_ra4m2.yaml @@ -13,4 +13,5 @@ supported: - usbd - watchdog - counter + - crc vendor: renesas diff --git a/boards/renesas/ek_ra4m3/ek_ra4m3.dts b/boards/renesas/ek_ra4m3/ek_ra4m3.dts index 384da60afca1b..a8a7fec8bcddf 100644 --- a/boards/renesas/ek_ra4m3/ek_ra4m3.dts +++ b/boards/renesas/ek_ra4m3/ek_ra4m3.dts @@ -22,6 +22,7 @@ zephyr,console = &uart0; zephyr,shell-uart = &uart0; zephyr,entropy = &trng; + zephyr,crc = &crc; }; leds { @@ -188,3 +189,7 @@ &wdt { status = "okay"; }; + +&crc { + status = "okay"; +}; diff --git a/boards/renesas/ek_ra4m3/ek_ra4m3.yaml b/boards/renesas/ek_ra4m3/ek_ra4m3.yaml index 5baf4a4bfe696..855006315785c 100644 --- a/boards/renesas/ek_ra4m3/ek_ra4m3.yaml +++ b/boards/renesas/ek_ra4m3/ek_ra4m3.yaml @@ -13,4 +13,5 @@ supported: - usbd - watchdog - counter + - crc vendor: renesas diff --git a/boards/renesas/ek_ra4w1/ek_ra4w1.dts b/boards/renesas/ek_ra4w1/ek_ra4w1.dts index 7ab31de3e89eb..9a4c3742de6e0 100644 --- a/boards/renesas/ek_ra4w1/ek_ra4w1.dts +++ b/boards/renesas/ek_ra4w1/ek_ra4w1.dts @@ -21,6 +21,7 @@ zephyr,console = &uart0; zephyr,shell-uart = &uart0; zephyr,entropy = &trng; + zephyr,crc = &crc; }; leds { @@ -123,3 +124,7 @@ &wdt { status = "okay"; }; + +&crc { + status = "okay"; +}; diff --git a/boards/renesas/ek_ra4w1/ek_ra4w1.yaml b/boards/renesas/ek_ra4w1/ek_ra4w1.yaml index f986a9f8d449b..0beed446ef857 100644 --- a/boards/renesas/ek_ra4w1/ek_ra4w1.yaml +++ b/boards/renesas/ek_ra4w1/ek_ra4w1.yaml @@ -12,4 +12,5 @@ supported: - uart - watchdog - counter + - crc vendor: renesas diff --git a/boards/renesas/ek_ra6e2/ek_ra6e2.dts b/boards/renesas/ek_ra6e2/ek_ra6e2.dts index 7d4911bb9da2a..45ef1fd803831 100644 --- a/boards/renesas/ek_ra6e2/ek_ra6e2.dts +++ b/boards/renesas/ek_ra6e2/ek_ra6e2.dts @@ -24,6 +24,7 @@ zephyr,shell-uart = &uart0; zephyr,canbus = &canfd0; zephyr,entropy = &trng; + zephyr,crc = &crc; }; leds { @@ -189,3 +190,7 @@ &wdt { status = "okay"; }; + +&crc { + status = "okay"; +}; diff --git a/boards/renesas/ek_ra6e2/ek_ra6e2.yaml b/boards/renesas/ek_ra6e2/ek_ra6e2.yaml index ef63f298700d6..3df8faebb90ed 100644 --- a/boards/renesas/ek_ra6e2/ek_ra6e2.yaml +++ b/boards/renesas/ek_ra6e2/ek_ra6e2.yaml @@ -11,4 +11,5 @@ supported: - gpio - watchdog - counter + - crc vendor: renesas diff --git a/boards/renesas/ek_ra6m1/ek_ra6m1.dts b/boards/renesas/ek_ra6m1/ek_ra6m1.dts index 00fd4ff32677c..69a641ed3ac57 100644 --- a/boards/renesas/ek_ra6m1/ek_ra6m1.dts +++ b/boards/renesas/ek_ra6m1/ek_ra6m1.dts @@ -23,6 +23,7 @@ zephyr,console = &uart8; zephyr,shell-uart = &uart8; zephyr,entropy = &trng; + zephyr,crc = &crc; }; leds { @@ -163,3 +164,7 @@ &wdt { status = "okay"; }; + +&crc { + status = "okay"; +}; diff --git a/boards/renesas/ek_ra6m1/ek_ra6m1.yaml b/boards/renesas/ek_ra6m1/ek_ra6m1.yaml index 29b29a4efb83b..0750507650619 100644 --- a/boards/renesas/ek_ra6m1/ek_ra6m1.yaml +++ b/boards/renesas/ek_ra6m1/ek_ra6m1.yaml @@ -13,4 +13,5 @@ supported: - usbd - watchdog - counter + - crc vendor: renesas diff --git a/boards/renesas/ek_ra6m2/ek_ra6m2.dts b/boards/renesas/ek_ra6m2/ek_ra6m2.dts index 46fcc3ad44281..88630e21cc194 100644 --- a/boards/renesas/ek_ra6m2/ek_ra6m2.dts +++ b/boards/renesas/ek_ra6m2/ek_ra6m2.dts @@ -23,6 +23,7 @@ zephyr,console = &uart7; zephyr,shell-uart = &uart7; zephyr,entropy = &trng; + zephyr,crc = &crc; }; leds { @@ -159,3 +160,7 @@ &wdt { status = "okay"; }; + +&crc { + status = "okay"; +}; diff --git a/boards/renesas/ek_ra6m2/ek_ra6m2.yaml b/boards/renesas/ek_ra6m2/ek_ra6m2.yaml index c5af184f2118c..920437c06bc93 100644 --- a/boards/renesas/ek_ra6m2/ek_ra6m2.yaml +++ b/boards/renesas/ek_ra6m2/ek_ra6m2.yaml @@ -12,4 +12,5 @@ supported: - usbd - watchdog - counter + - crc vendor: renesas diff --git a/boards/renesas/ek_ra6m3/ek_ra6m3.dts b/boards/renesas/ek_ra6m3/ek_ra6m3.dts index 409f0549ff30b..834237f5ef08c 100644 --- a/boards/renesas/ek_ra6m3/ek_ra6m3.dts +++ b/boards/renesas/ek_ra6m3/ek_ra6m3.dts @@ -23,6 +23,7 @@ zephyr,flash-controller = &flash1; zephyr,flash = &flash0; zephyr,entropy = &trng; + zephyr,crc = &crc; }; leds { @@ -214,3 +215,7 @@ status = "okay"; }; }; + +&crc { + status = "okay"; +}; diff --git a/boards/renesas/ek_ra6m3/ek_ra6m3.yaml b/boards/renesas/ek_ra6m3/ek_ra6m3.yaml index 7ea82509fc2b5..1be42ec173f84 100644 --- a/boards/renesas/ek_ra6m3/ek_ra6m3.yaml +++ b/boards/renesas/ek_ra6m3/ek_ra6m3.yaml @@ -10,6 +10,7 @@ toolchain: supported: - gpio - usbd + - crc - watchdog - counter vendor: renesas diff --git a/boards/renesas/ek_ra6m4/ek_ra6m4.dts b/boards/renesas/ek_ra6m4/ek_ra6m4.dts index c6ed4cbcff021..deb2daafdfe6f 100644 --- a/boards/renesas/ek_ra6m4/ek_ra6m4.dts +++ b/boards/renesas/ek_ra6m4/ek_ra6m4.dts @@ -24,6 +24,7 @@ zephyr,console = &uart0; zephyr,shell-uart = &uart0; zephyr,entropy = &trng; + zephyr,crc = &crc; }; leds { @@ -290,3 +291,7 @@ arduino_spi: &spi0 {}; &wdt { status = "okay"; }; + +&crc { + status = "okay"; +}; diff --git a/boards/renesas/ek_ra6m4/ek_ra6m4.yaml b/boards/renesas/ek_ra6m4/ek_ra6m4.yaml index 85317151ba31a..370040af35968 100644 --- a/boards/renesas/ek_ra6m4/ek_ra6m4.yaml +++ b/boards/renesas/ek_ra6m4/ek_ra6m4.yaml @@ -10,6 +10,7 @@ toolchain: supported: - gpio - usbd + - crc - watchdog - counter vendor: renesas diff --git a/boards/renesas/ek_ra6m5/ek_ra6m5.dts b/boards/renesas/ek_ra6m5/ek_ra6m5.dts index 47cfc8fcb485d..afe219829bb9d 100644 --- a/boards/renesas/ek_ra6m5/ek_ra6m5.dts +++ b/boards/renesas/ek_ra6m5/ek_ra6m5.dts @@ -23,6 +23,7 @@ zephyr,console = &uart0; zephyr,shell-uart = &uart0; zephyr,entropy = &trng; + zephyr,crc = &crc; }; leds { @@ -195,3 +196,7 @@ &wdt { status = "okay"; }; + +&crc { + status = "okay"; +}; diff --git a/boards/renesas/ek_ra6m5/ek_ra6m5.yaml b/boards/renesas/ek_ra6m5/ek_ra6m5.yaml index 8db264944a319..57cbbf46a3685 100644 --- a/boards/renesas/ek_ra6m5/ek_ra6m5.yaml +++ b/boards/renesas/ek_ra6m5/ek_ra6m5.yaml @@ -10,6 +10,7 @@ toolchain: supported: - gpio - usbd + - crc - watchdog - counter vendor: renesas diff --git a/boards/renesas/ek_ra8d1/ek_ra8d1.dts b/boards/renesas/ek_ra8d1/ek_ra8d1.dts index f91c2fa91c709..bf4539112e29a 100644 --- a/boards/renesas/ek_ra8d1/ek_ra8d1.dts +++ b/boards/renesas/ek_ra8d1/ek_ra8d1.dts @@ -26,6 +26,7 @@ zephyr,entropy = &trng; zephyr,flash-controller = &flash1; zephyr,canbus = &canfd0; + zephyr,crc = &crc; }; leds { @@ -436,3 +437,7 @@ pmod_sd_shield: &sdhc1 {}; }; }; }; + +&crc { + status = "okay"; +}; diff --git a/boards/renesas/ek_ra8d1/ek_ra8d1.yaml b/boards/renesas/ek_ra8d1/ek_ra8d1.yaml index 11d214225c732..6a94c0a9f2096 100644 --- a/boards/renesas/ek_ra8d1/ek_ra8d1.yaml +++ b/boards/renesas/ek_ra8d1/ek_ra8d1.yaml @@ -16,4 +16,5 @@ supported: - counter - i2s - i3c + - crc vendor: renesas diff --git a/boards/renesas/ek_ra8m1/ek_ra8m1.dts b/boards/renesas/ek_ra8m1/ek_ra8m1.dts index d4378c2708753..6062b5805a39f 100644 --- a/boards/renesas/ek_ra8m1/ek_ra8m1.dts +++ b/boards/renesas/ek_ra8m1/ek_ra8m1.dts @@ -24,6 +24,7 @@ zephyr,shell-uart = &uart9; zephyr,entropy = &trng; zephyr,canbus = &canfd0; + zephyr,crc = &crc; }; leds { @@ -494,3 +495,7 @@ pmod_sd_shield: &sdhc0 {}; }; }; }; + +&crc{ + status = "okay"; +}; diff --git a/boards/renesas/ek_ra8m1/ek_ra8m1.yaml b/boards/renesas/ek_ra8m1/ek_ra8m1.yaml index 1dffeb2effb71..f9a5074829427 100644 --- a/boards/renesas/ek_ra8m1/ek_ra8m1.yaml +++ b/boards/renesas/ek_ra8m1/ek_ra8m1.yaml @@ -15,4 +15,5 @@ supported: - counter - i2s - i3c + - crc vendor: renesas diff --git a/boards/renesas/fpb_ra4e1/fpb_ra4e1.dts b/boards/renesas/fpb_ra4e1/fpb_ra4e1.dts index 7a8396753b8aa..c85c1829741f0 100644 --- a/boards/renesas/fpb_ra4e1/fpb_ra4e1.dts +++ b/boards/renesas/fpb_ra4e1/fpb_ra4e1.dts @@ -22,6 +22,7 @@ zephyr,console = &uart0; zephyr,shell-uart = &uart0; zephyr,entropy = &trng; + zephyr,crc = &crc; }; leds { @@ -159,3 +160,7 @@ &wdt { status = "okay"; }; + +&crc { + status = "okay"; +}; diff --git a/boards/renesas/fpb_ra4e1/fpb_ra4e1.yaml b/boards/renesas/fpb_ra4e1/fpb_ra4e1.yaml index ccd914832ed2e..b038874a2c9b7 100644 --- a/boards/renesas/fpb_ra4e1/fpb_ra4e1.yaml +++ b/boards/renesas/fpb_ra4e1/fpb_ra4e1.yaml @@ -10,6 +10,7 @@ toolchain: supported: - gpio - uart + - crc - watchdog - counter vendor: renesas diff --git a/boards/renesas/fpb_ra6e1/fpb_ra6e1.dts b/boards/renesas/fpb_ra6e1/fpb_ra6e1.dts index 7b64e4422785e..95c2d32d2bbfa 100644 --- a/boards/renesas/fpb_ra6e1/fpb_ra6e1.dts +++ b/boards/renesas/fpb_ra6e1/fpb_ra6e1.dts @@ -23,6 +23,7 @@ zephyr,console = &uart0; zephyr,shell-uart = &uart0; zephyr,entropy = &trng; + zephyr,crc = &crc; }; leds { @@ -144,3 +145,7 @@ &wdt { status = "okay"; }; + +&crc { + status = "okay"; +}; diff --git a/boards/renesas/fpb_ra6e1/fpb_ra6e1.yaml b/boards/renesas/fpb_ra6e1/fpb_ra6e1.yaml index ad3884548a920..0ee6b917ea647 100644 --- a/boards/renesas/fpb_ra6e1/fpb_ra6e1.yaml +++ b/boards/renesas/fpb_ra6e1/fpb_ra6e1.yaml @@ -9,6 +9,7 @@ toolchain: - gnuarmemb supported: - gpio + - crc - watchdog - counter vendor: renesas diff --git a/boards/renesas/fpb_ra6e2/fpb_ra6e2.dts b/boards/renesas/fpb_ra6e2/fpb_ra6e2.dts index 60323b043e6aa..bf5c5ed93fbfe 100644 --- a/boards/renesas/fpb_ra6e2/fpb_ra6e2.dts +++ b/boards/renesas/fpb_ra6e2/fpb_ra6e2.dts @@ -22,6 +22,7 @@ zephyr,console = &uart0; zephyr,shell-uart = &uart0; zephyr,entropy = &trng; + zephyr,crc = &crc; }; leds { @@ -134,3 +135,7 @@ &wdt { status = "okay"; }; + +&crc { + status = "okay"; +}; diff --git a/boards/renesas/fpb_ra6e2/fpb_ra6e2.yaml b/boards/renesas/fpb_ra6e2/fpb_ra6e2.yaml index ae8bee39ffbca..1e9be5cb66bff 100644 --- a/boards/renesas/fpb_ra6e2/fpb_ra6e2.yaml +++ b/boards/renesas/fpb_ra6e2/fpb_ra6e2.yaml @@ -9,6 +9,7 @@ toolchain: - gnuarmemb supported: - gpio + - crc - watchdog - counter vendor: renesas diff --git a/boards/renesas/mck_ra8t1/mck_ra8t1.dts b/boards/renesas/mck_ra8t1/mck_ra8t1.dts index dd56259d90985..b1e34d6e31738 100644 --- a/boards/renesas/mck_ra8t1/mck_ra8t1.dts +++ b/boards/renesas/mck_ra8t1/mck_ra8t1.dts @@ -22,6 +22,7 @@ zephyr,entropy = &trng; zephyr,flash-controller = &flash1; zephyr,canbus = &canfd1; + zephyr,crc = &crc; }; leds { @@ -268,3 +269,7 @@ status = "okay"; }; }; + +&crc { + status = "okay"; +}; diff --git a/boards/renesas/mck_ra8t1/mck_ra8t1.yaml b/boards/renesas/mck_ra8t1/mck_ra8t1.yaml index c1f389fdaa8d5..9b24d42bedb28 100644 --- a/boards/renesas/mck_ra8t1/mck_ra8t1.yaml +++ b/boards/renesas/mck_ra8t1/mck_ra8t1.yaml @@ -14,4 +14,5 @@ supported: - usbd - counter - i3c + - crc vendor: renesas diff --git a/boards/renesas/voice_ra4e1/voice_ra4e1.dts b/boards/renesas/voice_ra4e1/voice_ra4e1.dts index 7cf9ec82e0142..88becd3565ba2 100644 --- a/boards/renesas/voice_ra4e1/voice_ra4e1.dts +++ b/boards/renesas/voice_ra4e1/voice_ra4e1.dts @@ -22,6 +22,7 @@ zephyr,console = &uart3; zephyr,shell-uart = &uart3; zephyr,entropy = &trng; + zephyr,crc = &crc; }; leds { @@ -144,3 +145,7 @@ pinctrl-names = "default"; status = "okay"; }; + +&crc { + status = "okay"; +}; diff --git a/boards/renesas/voice_ra4e1/voice_ra4e1.yaml b/boards/renesas/voice_ra4e1/voice_ra4e1.yaml index bd744cc553dd3..becde6a531e62 100644 --- a/boards/renesas/voice_ra4e1/voice_ra4e1.yaml +++ b/boards/renesas/voice_ra4e1/voice_ra4e1.yaml @@ -11,5 +11,6 @@ supported: - gpio - uart - usbd + - crc - watchdog vendor: renesas From b2c3c42e3463601669f91ade41eab8d736e10d22 Mon Sep 17 00:00:00 2001 From: Duy Vo Date: Tue, 11 Mar 2025 16:01:26 +0700 Subject: [PATCH 4/9] crc: initial support for CRC subsystem Migrate support from crc library to new crc subsystem Add hardware acclerator backend for crc subsystem Signed-off-by: Duy Vo --- MAINTAINERS.yml | 12 +- lib/CMakeLists.txt | 1 - lib/Kconfig | 2 - lib/crc/CMakeLists.txt | 13 - lib/crc/Kconfig | 23 -- subsys/CMakeLists.txt | 1 + subsys/Kconfig | 1 + subsys/crc/CMakeLists.txt | 15 ++ subsys/crc/Kconfig | 163 ++++++++++++ {lib => subsys}/crc/crc16_sw.c | 11 +- {lib => subsys}/crc/crc24_sw.c | 4 +- {lib => subsys}/crc/crc32_sw.c | 9 +- {lib => subsys}/crc/crc32c_sw.c | 15 +- {lib => subsys}/crc/crc32k_4_2_sw.c | 2 +- {lib => subsys}/crc/crc4_sw.c | 10 +- {lib => subsys}/crc/crc7_sw.c | 2 +- {lib => subsys}/crc/crc8_sw.c | 12 +- subsys/crc/crc_hardware.c | 378 ++++++++++++++++++++++++++++ {lib => subsys}/crc/crc_shell.c | 0 19 files changed, 599 insertions(+), 75 deletions(-) delete mode 100644 lib/crc/CMakeLists.txt delete mode 100644 lib/crc/Kconfig create mode 100644 subsys/crc/CMakeLists.txt create mode 100644 subsys/crc/Kconfig rename {lib => subsys}/crc/crc16_sw.c (75%) rename {lib => subsys}/crc/crc24_sw.c (77%) rename {lib => subsys}/crc/crc32_sw.c (63%) rename {lib => subsys}/crc/crc32c_sw.c (65%) rename {lib => subsys}/crc/crc32k_4_2_sw.c (97%) rename {lib => subsys}/crc/crc4_sw.c (69%) rename {lib => subsys}/crc/crc7_sw.c (78%) rename {lib => subsys}/crc/crc8_sw.c (77%) create mode 100644 subsys/crc/crc_hardware.c rename {lib => subsys}/crc/crc_shell.c (100%) diff --git a/MAINTAINERS.yml b/MAINTAINERS.yml index 1c1b769e9f50f..9f8e2c67df435 100644 --- a/MAINTAINERS.yml +++ b/MAINTAINERS.yml @@ -857,6 +857,17 @@ Console: tests: - sample.console +CRC: + status: maintained + maintainers: + - thenguyenyf + files: + - include/zephyr/sys/crc.h + - subsys/crc/ + - tests/subsys/crc/ + labels: + - "area: CRC" + Debug: status: maintained maintainers: @@ -2605,7 +2616,6 @@ Utilities: - dcpleung - peter-mitsis files: - - lib/crc/ - lib/utils/ - tests/unit/timeutil/ - tests/unit/time_units/ diff --git a/lib/CMakeLists.txt b/lib/CMakeLists.txt index 9fb963de4154a..cada1b678f01f 100644 --- a/lib/CMakeLists.txt +++ b/lib/CMakeLists.txt @@ -3,7 +3,6 @@ # FIXME: SHADOW_VARS: Remove this once we have enabled -Wshadow globally. add_compile_options($) -add_subdirectory(crc) if(NOT CONFIG_EXTERNAL_LIBC) add_subdirectory(libc) endif() diff --git a/lib/Kconfig b/lib/Kconfig index 626bec379dde8..ada7fe79ff92b 100644 --- a/lib/Kconfig +++ b/lib/Kconfig @@ -7,8 +7,6 @@ source "lib/libc/Kconfig" source "lib/cpp/Kconfig" -source "lib/crc/Kconfig" - menu "Additional libraries" source "lib/hash/Kconfig" diff --git a/lib/crc/CMakeLists.txt b/lib/crc/CMakeLists.txt deleted file mode 100644 index 6a6b35ea18ad1..0000000000000 --- a/lib/crc/CMakeLists.txt +++ /dev/null @@ -1,13 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_sources_ifdef(CONFIG_CRC - crc32k_4_2_sw.c - crc32c_sw.c - crc32_sw.c - crc24_sw.c - crc16_sw.c - crc8_sw.c - crc7_sw.c - crc4_sw.c - ) -zephyr_sources_ifdef(CONFIG_CRC_SHELL crc_shell.c) diff --git a/lib/crc/Kconfig b/lib/crc/Kconfig deleted file mode 100644 index eb2ced63db26e..0000000000000 --- a/lib/crc/Kconfig +++ /dev/null @@ -1,23 +0,0 @@ -# Copyright (c) 2016,2023 Intel Corporation -# Copyright (c) 2024 Intercreate, Inc. -# SPDX-License-Identifier: Apache-2.0 -# -config CRC - bool "Cyclic redundancy check (CRC) Support" - help - Enable use of CRC. - -if CRC -config CRC_SHELL - bool "CRC Shell" - depends on SHELL - select POSIX_C_LIB_EXT - help - Enable CRC checking for memory regions from the shell. - -config CRC32_K_4_2_TABLE_256 - bool "Use 256-length table for CRC32-K/4.2" - help - Enable the 256-length instead of 16-length table for CRC32-K/4.2. - -endif # CRC diff --git a/subsys/CMakeLists.txt b/subsys/CMakeLists.txt index a0a2bc828cf23..7115235f6d6ef 100644 --- a/subsys/CMakeLists.txt +++ b/subsys/CMakeLists.txt @@ -38,6 +38,7 @@ add_subdirectory_ifdef(CONFIG_ARM_SIP_SVC_SUBSYS sip_svc) add_subdirectory_ifdef(CONFIG_BINDESC bindesc) add_subdirectory_ifdef(CONFIG_BT bluetooth) add_subdirectory_ifdef(CONFIG_CONSOLE_SUBSYS console) +add_subdirectory_ifdef(CONFIG_CRC crc) add_subdirectory_ifdef(CONFIG_DAP dap) add_subdirectory_ifdef(CONFIG_DEMAND_PAGING demand_paging) add_subdirectory_ifdef(CONFIG_DISK_ACCESS disk) diff --git a/subsys/Kconfig b/subsys/Kconfig index a85bda6ece4be..532a601be3285 100644 --- a/subsys/Kconfig +++ b/subsys/Kconfig @@ -11,6 +11,7 @@ source "subsys/bindesc/Kconfig" source "subsys/bluetooth/Kconfig" source "subsys/canbus/Kconfig" source "subsys/console/Kconfig" +source "subsys/crc/Kconfig" source "subsys/dap/Kconfig" source "subsys/debug/Kconfig" source "subsys/demand_paging/Kconfig" diff --git a/subsys/crc/CMakeLists.txt b/subsys/crc/CMakeLists.txt new file mode 100644 index 0000000000000..0413b1b2158c9 --- /dev/null +++ b/subsys/crc/CMakeLists.txt @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_library() + +zephyr_library_sources(crc4_sw.c) +zephyr_library_sources(crc8_sw.c) +zephyr_library_sources(crc16_sw.c) +zephyr_library_sources(crc7_sw.c) +zephyr_library_sources(crc24_sw.c) +zephyr_library_sources(crc32c_sw.c) +zephyr_library_sources(crc32_sw.c) +zephyr_library_sources(crc32k_4_2_sw.c) + +zephyr_library_sources_ifdef(CONFIG_CRC_HW_HANDLER crc_hardware.c) +zephyr_library_sources_ifdef(CONFIG_CRC_SHELL crc_shell.c) diff --git a/subsys/crc/Kconfig b/subsys/crc/Kconfig new file mode 100644 index 0000000000000..c8403734aba69 --- /dev/null +++ b/subsys/crc/Kconfig @@ -0,0 +1,163 @@ +# Copyright (c) 2016,2023 Intel Corporation +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +DT_CHOSEN_Z_CRC := zephyr,crc + +menuconfig CRC + bool "Cyclic redundancy check (CRC) Support" + help + Enable use of CRC. + +if CRC + +module = CRC +module-str = CRC +source "subsys/logging/Kconfig.template.log_config" + +config CRC_HW_HANDLER + bool "CRC Hardware Accelerator" + default y if $(dt_chosen_enabled,$(DT_CHOSEN_Z_CRC)) + select CRC_DRIVER + help + Enable use of CRC hardware + +config CRC4 + bool "CRC-4 (Generic)" + depends on CRC_DRIVER_HAS_CRC4 + default y + help + Implements a generic CRC-4 algorithm. This is suitable for platforms + without hardware CRC support. Offers flexibility but has lower performance + compared to hardware-based implementations. + +config CRC4_TI + bool "CRC-4 (TI Polynomial)" + depends on CRC_DRIVER_HAS_CRC4_TI + default y + help + Implements the TI-specific CRC-4 algorithm. Commonly used in low-level + embedded communication where minimal CRC overhead is needed. + +config CRC7_BE + bool "CRC-7 (Big Endian)" + depends on CRC_DRIVER_HAS_CRC7_BE + default y + help + Implements a CRC-7 algorithm with Big Endian bit order. Often used + in SD card protocols and other serial communication standards. + +config CRC8 + bool "CRC-8 (Generic)" + depends on CRC_DRIVER_HAS_CRC8 + default y + help + Implements a generic CRC-8 algorithm. Useful for small data integrity + checks such as checksums and simple communication protocols. + +config CRC8_ROHC + bool "CRC-8 (ROHC)" + depends on CRC_DRIVER_HAS_CRC8_ROHC + default y + help + Implements the CRC-8 ROHC (Robust Header Compression) algorithm, + typically used in compressed IP header protocols and networking. + +config CRC8_CCITT + bool "CRC-8 (CCITT)" + depends on CRC_DRIVER_HAS_CRC8_CCITT + default y + help + Implements the CRC-8 CCITT polynomial. Commonly used in + telecommunications and low-power sensor protocols. + +config CRC16 + bool "CRC-16 (Generic)" + depends on CRC_DRIVER_HAS_CRC16 + default y + help + Implements the generic CRC-16 algorithm. Frequently used in + storage, file transmission, and basic serial communication protocols. + +config CRC16_ANSI + bool "CRC-16 (ANSI)" + depends on CRC_DRIVER_HAS_CRC16_ANSI + default y + help + Implements the ANSI variant of CRC-16, also known as CRC-16-IBM. + Commonly applied in legacy serial and file systems. + +config CRC16_CCITT + bool "CRC-16 (CCITT)" + depends on CRC_DRIVER_HAS_CRC16_CCITT + default y + help + Implements the CCITT variant of CRC-16, widely used in + telecommunication systems such as XMODEM and HDLC protocols. + +config CRC16_ITU_T + bool "CRC-16 (ITU-T)" + depends on CRC_DRIVER_HAS_CRC16_ITU_T + default y + help + Implements the ITU-T (formerly CCITT) CRC-16 variant. + Popular in modem protocols and wireless communication standards. + +config CRC16_REFLECT + bool "CRC-16 (Reflected)" + depends on CRC_DRIVER_HAS_CRC16_REFLECT + default y + help + Implements the reflected (bit-reversed) variant of CRC-16-CCITT. + Useful in systems that process data in LSB-first order. + +config CRC24_PGP + bool "CRC-24 (PGP)" + depends on CRC_DRIVER_HAS_CRC24_PGP + default y + help + Implements a CRC24 algorithm, used in applications like Bluetooth + and certain cryptographic protocols. + +config CRC32_C + bool "CRC-32C" + depends on CRC_DRIVER_HAS_CRC32_C + default y + help + Implements the CRC32-C (Castagnoli) algorithm, optimized for + high-performance applications such as storage, networking, + and error detection in modern processors. + +config CRC32_IEEE + bool "CRC-32 (IEEE)" + depends on CRC_DRIVER_HAS_CRC32_IEEE + default y + help + Implements the CRC32-IEEE (CRC-32) algorithm, commonly used + in Ethernet, ZIP file integrity checks, and other standard + networking and storage applications. + + +config CRC32_K_4_2 + bool "CRC-32K/4.2" + depends on CRC_DRIVER_HAS_CRC32_K_4_2 + default y + help + Implement the CRC-32K/4.2 algorithm, a variant of the standard + CRC32-IEEE used in Ethernet, ZIP files, and other data integrity + applications. + +config CRC32_K_4_2_TABLE_256 + bool "CRC-32K/4.2 Table 256" + help + Enables the software implementation of the CRC-32K/4.2 algorithm + using a 256-entry lookup table for faster computation. + +config CRC_SHELL + bool "CRC Shell" + depends on SHELL + select POSIX_C_LIB_EXT + help + Enable CRC checking for memory regions from the shell. + +endif # CRC diff --git a/lib/crc/crc16_sw.c b/subsys/crc/crc16_sw.c similarity index 75% rename from lib/crc/crc16_sw.c rename to subsys/crc/crc16_sw.c index 50684e25722d2..eea8be335472b 100644 --- a/lib/crc/crc16_sw.c +++ b/subsys/crc/crc16_sw.c @@ -6,7 +6,7 @@ #include -uint16_t crc16(uint16_t poly, uint16_t seed, const uint8_t *src, size_t len) +uint16_t __weak crc16(uint16_t poly, uint16_t seed, const uint8_t *src, size_t len) { uint16_t crc = seed; size_t i, j; @@ -23,11 +23,10 @@ uint16_t crc16(uint16_t poly, uint16_t seed, const uint8_t *src, size_t len) } } - return crc; } -uint16_t crc16_reflect(uint16_t poly, uint16_t seed, const uint8_t *src, size_t len) +uint16_t __weak crc16_reflect(uint16_t poly, uint16_t seed, const uint8_t *src, size_t len) { uint16_t crc = seed; size_t i, j; @@ -44,12 +43,10 @@ uint16_t crc16_reflect(uint16_t poly, uint16_t seed, const uint8_t *src, size_t } } - return crc; } - -uint16_t crc16_ccitt(uint16_t seed, const uint8_t *src, size_t len) +uint16_t __weak crc16_ccitt(uint16_t seed, const uint8_t *src, size_t len) { for (; len > 0; len--) { uint8_t e, f; @@ -63,7 +60,7 @@ uint16_t crc16_ccitt(uint16_t seed, const uint8_t *src, size_t len) return seed; } -uint16_t crc16_itu_t(uint16_t seed, const uint8_t *src, size_t len) +uint16_t __weak crc16_itu_t(uint16_t seed, const uint8_t *src, size_t len) { for (; len > 0; len--) { seed = (seed >> 8U) | (seed << 8U); diff --git a/lib/crc/crc24_sw.c b/subsys/crc/crc24_sw.c similarity index 77% rename from lib/crc/crc24_sw.c rename to subsys/crc/crc24_sw.c index 78c2c0517f83b..3800edfbd1024 100644 --- a/lib/crc/crc24_sw.c +++ b/subsys/crc/crc24_sw.c @@ -8,13 +8,13 @@ #define CRC24_PGP_POLY 0x01864cfbU -uint32_t crc24_pgp(const uint8_t *data, size_t len) +uint32_t __weak crc24_pgp(const uint8_t *data, size_t len) { return crc24_pgp_update(CRC24_PGP_INITIAL_VALUE, data, len) & CRC24_FINAL_VALUE_MASK; } /* CRC-24 implementation from the section 6.1 of the RFC 4880 */ -uint32_t crc24_pgp_update(uint32_t crc, const uint8_t *data, size_t len) +uint32_t __weak crc24_pgp_update(uint32_t crc, const uint8_t *data, size_t len) { int i; diff --git a/lib/crc/crc32_sw.c b/subsys/crc/crc32_sw.c similarity index 63% rename from lib/crc/crc32_sw.c rename to subsys/crc/crc32_sw.c index f2f2712ff5bf3..56c2490072b6c 100644 --- a/lib/crc/crc32_sw.c +++ b/subsys/crc/crc32_sw.c @@ -6,18 +6,17 @@ #include -uint32_t crc32_ieee(const uint8_t *data, size_t len) +uint32_t __weak crc32_ieee(const uint8_t *data, size_t len) { return crc32_ieee_update(0x0, data, len); } -uint32_t crc32_ieee_update(uint32_t crc, const uint8_t *data, size_t len) +uint32_t __weak crc32_ieee_update(uint32_t crc, const uint8_t *data, size_t len) { /* crc table generated from polynomial 0xedb88320 */ static const uint32_t table[16] = { - 0x00000000U, 0x1db71064U, 0x3b6e20c8U, 0x26d930acU, - 0x76dc4190U, 0x6b6b51f4U, 0x4db26158U, 0x5005713cU, - 0xedb88320U, 0xf00f9344U, 0xd6d6a3e8U, 0xcb61b38cU, + 0x00000000U, 0x1db71064U, 0x3b6e20c8U, 0x26d930acU, 0x76dc4190U, 0x6b6b51f4U, + 0x4db26158U, 0x5005713cU, 0xedb88320U, 0xf00f9344U, 0xd6d6a3e8U, 0xcb61b38cU, 0x9b64c2b0U, 0x86d3d2d4U, 0xa00ae278U, 0xbdbdf21cU, }; diff --git a/lib/crc/crc32c_sw.c b/subsys/crc/crc32c_sw.c similarity index 65% rename from lib/crc/crc32c_sw.c rename to subsys/crc/crc32c_sw.c index 4d885bcb0df71..c6a38b7c799b4 100644 --- a/lib/crc/crc32c_sw.c +++ b/subsys/crc/crc32c_sw.c @@ -8,24 +8,23 @@ /* crc table generated from polynomial 0x1EDC6F41UL (Castagnoli) */ static const uint32_t crc32c_table[16] = { - 0x00000000UL, 0x105EC76FUL, 0x20BD8EDEUL, 0x30E349B1UL, - 0x417B1DBCUL, 0x5125DAD3UL, 0x61C69362UL, 0x7198540DUL, - 0x82F63B78UL, 0x92A8FC17UL, 0xA24BB5A6UL, 0xB21572C9UL, - 0xC38D26C4UL, 0xD3D3E1ABUL, 0xE330A81AUL, 0xF36E6F75UL + 0x00000000UL, 0x105EC76FUL, 0x20BD8EDEUL, 0x30E349B1UL, 0x417B1DBCUL, 0x5125DAD3UL, + 0x61C69362UL, 0x7198540DUL, 0x82F63B78UL, 0x92A8FC17UL, 0xA24BB5A6UL, 0xB21572C9UL, + 0xC38D26C4UL, 0xD3D3E1ABUL, 0xE330A81AUL, 0xF36E6F75UL, }; /* This value needs to be XORed with the final crc value once crc for * the entire stream is calculated. This is a requirement of crc32c algo. */ -#define CRC32C_XOR_OUT 0xFFFFFFFFUL +#define CRC32C_XOR_OUT 0xFFFFFFFFUL /* The crc32c algorithm requires the below value as Init value at the * beginning of the stream. */ -#define CRC32C_INIT 0xFFFFFFFFUL +#define CRC32C_INIT 0xFFFFFFFFUL -uint32_t crc32_c(uint32_t crc, const uint8_t *data, - size_t len, bool first_pkt, bool last_pkt) +uint32_t __weak crc32_c(uint32_t crc, const uint8_t *data, size_t len, bool first_pkt, + bool last_pkt) { if (first_pkt) { crc = CRC32C_INIT; diff --git a/lib/crc/crc32k_4_2_sw.c b/subsys/crc/crc32k_4_2_sw.c similarity index 97% rename from lib/crc/crc32k_4_2_sw.c rename to subsys/crc/crc32k_4_2_sw.c index 9208d780de92d..419ecb2f48567 100644 --- a/lib/crc/crc32k_4_2_sw.c +++ b/subsys/crc/crc32k_4_2_sw.c @@ -6,7 +6,7 @@ #include -uint32_t crc32_k_4_2_update(uint32_t crc, const uint8_t *const data, const size_t len) +uint32_t __weak crc32_k_4_2_update(uint32_t crc, const uint8_t *const data, const size_t len) { #if defined(CONFIG_CRC32_K_4_2_TABLE_256) diff --git a/lib/crc/crc4_sw.c b/subsys/crc/crc4_sw.c similarity index 69% rename from lib/crc/crc4_sw.c rename to subsys/crc/crc4_sw.c index e636a2c8fae26..b541435f0df92 100644 --- a/lib/crc/crc4_sw.c +++ b/subsys/crc/crc4_sw.c @@ -6,8 +6,8 @@ #include -uint8_t crc4(const uint8_t *src, size_t len, uint8_t polynomial, uint8_t initial_value, - bool reversed) +uint8_t __weak crc4(const uint8_t *src, size_t len, uint8_t polynomial, uint8_t initial_value, + bool reversed) { uint8_t crc = initial_value; size_t i, j, k; @@ -37,14 +37,14 @@ uint8_t crc4(const uint8_t *src, size_t len, uint8_t polynomial, uint8_t initial return crc & 0xF; } -uint8_t crc4_ti(uint8_t seed, const uint8_t *src, size_t len) +uint8_t __weak crc4_ti(uint8_t seed, const uint8_t *src, size_t len) { - static const uint8_t lookup[8] = { 0x03, 0x65, 0xcf, 0xa9, 0xb8, 0xde, 0x74, 0x12 }; + static const uint8_t lookup[8] = {0x03, 0x65, 0xcf, 0xa9, 0xb8, 0xde, 0x74, 0x12}; uint8_t index; for (size_t i = 0; i < len; i++) { for (size_t j = 0U; j < 2U; j++) { - index = seed ^ ((src[i] >> (4*(1-j))) & 0xf); + index = seed ^ ((src[i] >> (4 * (1 - j))) & 0xf); seed = (lookup[index >> 1] >> (1 - (index & 1)) * 4) & 0xf; } } diff --git a/lib/crc/crc7_sw.c b/subsys/crc/crc7_sw.c similarity index 78% rename from lib/crc/crc7_sw.c rename to subsys/crc/crc7_sw.c index 970c5734c7ab3..1d004c782cfd4 100644 --- a/lib/crc/crc7_sw.c +++ b/subsys/crc/crc7_sw.c @@ -6,7 +6,7 @@ #include -uint8_t crc7_be(uint8_t seed, const uint8_t *src, size_t len) +uint8_t __weak crc7_be(uint8_t seed, const uint8_t *src, size_t len) { while (len-- != 0UL) { uint8_t e = seed ^ *src++; diff --git a/lib/crc/crc8_sw.c b/subsys/crc/crc8_sw.c similarity index 77% rename from lib/crc/crc8_sw.c rename to subsys/crc/crc8_sw.c index 59900e14a62f1..ac151157abcee 100644 --- a/lib/crc/crc8_sw.c +++ b/subsys/crc/crc8_sw.c @@ -10,15 +10,15 @@ static const uint8_t crc8_ccitt_small_table[16] = { 0x00, 0x07, 0x0e, 0x09, 0x1c, 0x1b, 0x12, 0x15, - 0x38, 0x3f, 0x36, 0x31, 0x24, 0x23, 0x2a, 0x2d + 0x38, 0x3f, 0x36, 0x31, 0x24, 0x23, 0x2a, 0x2d, }; static const uint8_t crc8_rohc_small_table[16] = { 0x00, 0x1c, 0x38, 0x24, 0x70, 0x6c, 0x48, 0x54, - 0xe0, 0xfc, 0xd8, 0xc4, 0x90, 0x8c, 0xa8, 0xb4 + 0xe0, 0xfc, 0xd8, 0xc4, 0x90, 0x8c, 0xa8, 0xb4, }; -uint8_t crc8_ccitt(uint8_t val, const void *buf, size_t cnt) +uint8_t __weak crc8_ccitt(uint8_t val, const void *buf, size_t cnt) { size_t i; const uint8_t *p = buf; @@ -31,7 +31,7 @@ uint8_t crc8_ccitt(uint8_t val, const void *buf, size_t cnt) return val; } -uint8_t crc8_rohc(uint8_t val, const void *buf, size_t cnt) +uint8_t __weak crc8_rohc(uint8_t val, const void *buf, size_t cnt) { size_t i; const uint8_t *p = buf; @@ -44,8 +44,8 @@ uint8_t crc8_rohc(uint8_t val, const void *buf, size_t cnt) return val; } -uint8_t crc8(const uint8_t *src, size_t len, uint8_t polynomial, uint8_t initial_value, - bool reversed) +uint8_t __weak crc8(const uint8_t *src, size_t len, uint8_t polynomial, uint8_t initial_value, + bool reversed) { uint8_t crc = initial_value; size_t i, j; diff --git a/subsys/crc/crc_hardware.c b/subsys/crc/crc_hardware.c new file mode 100644 index 0000000000000..13c1aa239ee05 --- /dev/null +++ b/subsys/crc/crc_hardware.c @@ -0,0 +1,378 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +LOG_MODULE_REGISTER(crc, CONFIG_CRC_LOG_LEVEL); + +#include +#include + +static const struct device *const crc_dev = DEVICE_DT_GET(DT_CHOSEN(zephyr_crc)); + +static int crc_operation(const struct device *const dev, struct crc_ctx *ctx, const uint8_t *src, + size_t len) +{ + int ret; + + if (!device_is_ready((crc_dev))) { + return -ENODEV; + } + + ret = crc_begin(crc_dev, ctx); + if (ret != 0) { + return ret; + } + + ret = crc_update(crc_dev, ctx, src, len); + if (ret != 0) { + return ret; + } + + ret = crc_finish(crc_dev, ctx); + if (ret != 0) { + return ret; + } + + return 0; +} + +#ifdef CONFIG_CRC4 +uint8_t crc4(const uint8_t *src, size_t len, uint8_t polynomial, uint8_t initial_value, + bool reversed) +{ + uint8_t flag_reversed; + int ret; + + if (reversed) { + flag_reversed = CRC_FLAG_REVERSE_OUTPUT | CRC_FLAG_REVERSE_INPUT; + } else { + flag_reversed = CRC_FLAG_NO_REVERSE_OUTPUT | CRC_FLAG_NO_REVERSE_INPUT; + } + + struct crc_ctx ctx = { + .type = CRC4, + .polynomial = polynomial, + .seed = initial_value, + .reversed = flag_reversed, + }; + + ret = crc_operation(crc_dev, &ctx, src, len); + if (ret != 0) { + __ASSERT_MSG_INFO("CRC operation failed: %d", ret); + return 0; + } + + return ctx.result & 0x0F; +} +#endif + +#ifdef CONFIG_CRC4_TI +uint8_t crc4_ti(uint8_t seed, const uint8_t *src, size_t len) +{ + int ret; + + struct crc_ctx ctx = { + .type = CRC4, + .polynomial = CRC4_POLY, + .seed = seed, + .reversed = CRC_FLAG_NO_REVERSE_OUTPUT | CRC_FLAG_NO_REVERSE_INPUT, + }; + + ret = crc_operation(crc_dev, &ctx, src, len); + if (ret != 0) { + __ASSERT_MSG_INFO("CRC operation failed: %d", ret); + return 0; + } + + return ctx.result & 0x0F; +} +#endif + +#ifdef CONFIG_CRC7_BE +uint8_t crc7_be(uint8_t seed, const uint8_t *src, size_t len) +{ + int ret; + + struct crc_ctx ctx = { + .type = CRC7_BE, + .polynomial = CRC7_BE_POLY, + .seed = seed, + .reversed = CRC_FLAG_NO_REVERSE_OUTPUT | CRC_FLAG_NO_REVERSE_INPUT, + }; + + ret = crc_operation(crc_dev, &ctx, src, len); + if (ret != 0) { + __ASSERT_MSG_INFO("CRC operation failed: %d", ret); + return 0; + } + + return ctx.result & 0x7F; +} +#endif + +#ifdef CONFIG_CRC8 +uint8_t crc8(const uint8_t *src, size_t len, uint8_t polynomial, uint8_t initial_value, + bool reversed) +{ + uint8_t flag_reversed; + int ret; + + if (reversed) { + flag_reversed = CRC_FLAG_REVERSE_OUTPUT | CRC_FLAG_REVERSE_INPUT; + } else { + flag_reversed = CRC_FLAG_NO_REVERSE_OUTPUT | CRC_FLAG_NO_REVERSE_INPUT; + } + + struct crc_ctx ctx = { + .type = CRC8, + .polynomial = polynomial, + .seed = initial_value, + .reversed = flag_reversed, + }; + + ret = crc_operation(crc_dev, &ctx, src, len); + if (ret != 0) { + __ASSERT_MSG_INFO("CRC operation failed: %d", ret); + return 0; + } + return ctx.result; +} +#endif + +#ifdef CONFIG_CRC8_ROHC +uint8_t crc8_rohc(uint8_t initial_value, const void *buf, size_t len) +{ + int ret; + + struct crc_ctx ctx = { + .type = CRC8, + .polynomial = CRC8_POLY, + .seed = initial_value, + .reversed = CRC_FLAG_REVERSE_OUTPUT | CRC_FLAG_REVERSE_INPUT, + }; + + ret = crc_operation(crc_dev, &ctx, buf, len); + if (ret != 0) { + __ASSERT_MSG_INFO("CRC operation failed: %d", ret); + return 0; + } + + return ctx.result; +} +#endif + +#ifdef CONFIG_CRC8_CCITT +uint8_t crc8_ccitt(uint8_t initial_value, const void *buf, size_t len) +{ + int ret; + + struct crc_ctx ctx = { + .type = CRC8, + .polynomial = CRC8_POLY, + .seed = initial_value, + .reversed = CRC_FLAG_NO_REVERSE_OUTPUT | CRC_FLAG_NO_REVERSE_INPUT, + }; + + ret = crc_operation(crc_dev, &ctx, buf, len); + if (ret != 0) { + __ASSERT_MSG_INFO("CRC operation failed: %d", ret); + return 0; + } + + return ctx.result; +} +#endif + +#ifdef CONFIG_CRC16 +uint16_t crc16(uint16_t poly, uint16_t seed, const uint8_t *src, size_t len) +{ + int ret; + + struct crc_ctx ctx = { + .type = CRC16, + .polynomial = CRC16_POLY, + .seed = seed, + .reversed = CRC_FLAG_NO_REVERSE_OUTPUT | CRC_FLAG_NO_REVERSE_INPUT, + }; + + ret = crc_operation(crc_dev, &ctx, src, len); + if (ret != 0) { + __ASSERT_MSG_INFO("CRC operation failed: %d", ret); + return 0; + } + + return ctx.result; +} +#endif + +#ifdef CONFIG_CRC16_REFLECT +uint16_t crc16_reflect(uint16_t poly, uint16_t seed, const uint8_t *src, size_t len) +{ + int ret; + + struct crc_ctx ctx = { + .type = CRC16, + .polynomial = CRC16_POLY, + .seed = seed, + .reversed = CRC_FLAG_REVERSE_OUTPUT | CRC_FLAG_REVERSE_INPUT, + }; + + ret = crc_operation(crc_dev, &ctx, src, len); + if (ret != 0) { + __ASSERT_MSG_INFO("CRC operation failed: %d", ret); + return 0; + } + return ctx.result; +} +#endif + +#ifdef CONFIG_CRC16_CCITT +uint16_t crc16_ccitt(uint16_t seed, const uint8_t *src, size_t len) +{ + int ret; + + struct crc_ctx ctx = { + .type = CRC16_CCITT, + .polynomial = CRC16_CCITT_POLY, + .seed = seed, + .reversed = CRC_FLAG_REVERSE_OUTPUT | CRC_FLAG_REVERSE_INPUT, + }; + + ret = crc_operation(crc_dev, &ctx, src, len); + if (ret != 0) { + __ASSERT_MSG_INFO("CRC operation failed: %d", ret); + return 0; + } + + return ctx.result; +} +#endif + +#ifdef CONFIG_CRC16_ITU_T +uint16_t crc16_itu_t(uint16_t seed, const uint8_t *src, size_t len) +{ + int ret; + + struct crc_ctx ctx = { + .type = CRC16_CCITT, + .polynomial = CRC16_CCITT_POLY, + .seed = seed, + .reversed = CRC_FLAG_NO_REVERSE_OUTPUT | CRC_FLAG_NO_REVERSE_INPUT, + }; + + ret = crc_operation(crc_dev, &ctx, src, len); + if (ret != 0) { + __ASSERT_MSG_INFO("CRC operation failed: %d", ret); + return 0; + } + + return ctx.result; +} +#endif + +#ifdef CONFIG_CRC24_PGP +uint32_t crc24_pgp_update(uint32_t crc, const uint8_t *data, size_t len) +{ + int ret; + + struct crc_ctx ctx = { + .type = CRC24_PGP, + .polynomial = CRC24_PGP_POLY, + .seed = CRC24_PGP_INITIAL_VALUE, + .reversed = CRC_FLAG_NO_REVERSE_OUTPUT | CRC_FLAG_NO_REVERSE_INPUT, + }; + + ret = crc_operation(crc_dev, &ctx, data, len); + if (ret != 0) { + __ASSERT_MSG_INFO("CRC operation failed: %d", ret); + return 0; + } + + return ctx.result; +} + +uint32_t crc24_pgp(const uint8_t *data, size_t len) +{ + return crc24_pgp_update(CRC24_PGP_INITIAL_VALUE, data, len) & CRC24_FINAL_VALUE_MASK; +} +#endif + +#ifdef CONFIG_CRC32_C +uint32_t crc32_c(uint32_t crc, const uint8_t *buf, size_t len, bool first_pkt, bool last_pkt) +{ + int ret; + + if (first_pkt) { + crc = CRC32_C_INIT_VAL; + } + + struct crc_ctx ctx = { + .type = CRC32_C, + .polynomial = CRC32C_POLY, + .seed = crc, + .reversed = CRC_FLAG_REVERSE_OUTPUT | CRC_FLAG_REVERSE_INPUT, + }; + + ret = crc_operation(crc_dev, &ctx, buf, len); + if (ret != 0) { + __ASSERT_MSG_INFO("CRC operation failed: %d", ret); + return 0; + } + + return last_pkt ? (ctx.result ^ CRC32C_XOR_OUT) : ctx.result; +} +#endif + +#ifdef CONFIG_CRC32_IEEE +uint32_t crc32_ieee_update(uint32_t crc, const uint8_t *buf, size_t len) +{ + int ret; + + crc = ~crc; + + struct crc_ctx ctx = { + .type = CRC32_IEEE, + .polynomial = CRC32_IEEE_POLY, + .seed = crc, + .reversed = CRC_FLAG_REVERSE_OUTPUT | CRC_FLAG_REVERSE_INPUT, + }; + + ret = crc_operation(crc_dev, &ctx, buf, len); + if (ret != 0) { + __ASSERT_MSG_INFO("CRC operation failed: %d", ret); + return 0; + } + + return ctx.result; +} + +uint32_t crc32_ieee(const uint8_t *buf, size_t len) +{ + return crc32_ieee_update(0x0, buf, len); +} +#endif + +#ifdef CONFIG_CRC32_K_4_2 +uint32_t crc32_k_4_2_update(uint32_t crc, const uint8_t *const data, const size_t len) +{ + int ret; + + struct crc_ctx ctx = { + .type = CRC32_K_4_2, + .polynomial = CRC32K_4_2_POLY, + .seed = crc, + .reversed = CRC_FLAG_NO_REVERSE_OUTPUT | CRC_FLAG_NO_REVERSE_INPUT, + }; + + ret = crc_operation(crc_dev, &ctx, data, len); + if (ret != 0) { + __ASSERT_MSG_INFO("CRC operation failed: %d", ret); + return 0; + } + + return ctx.result; +} +#endif diff --git a/lib/crc/crc_shell.c b/subsys/crc/crc_shell.c similarity index 100% rename from lib/crc/crc_shell.c rename to subsys/crc/crc_shell.c From 968ba149f5e10b285b01b3252a28762e028f00f5 Mon Sep 17 00:00:00 2001 From: Duy Vo Date: Fri, 14 Mar 2025 16:54:20 +0700 Subject: [PATCH 5/9] samples: drivers: crc: add samples for CRC driver Add samples for CRC driver Signed-off-by: Duy Vo --- samples/drivers/crc/CMakeLists.txt | 7 +++ samples/drivers/crc/README.rst | 53 +++++++++++++++++++ samples/drivers/crc/prj.conf | 2 + samples/drivers/crc/sample.yaml | 13 +++++ samples/drivers/crc/src/main.c | 85 ++++++++++++++++++++++++++++++ 5 files changed, 160 insertions(+) create mode 100644 samples/drivers/crc/CMakeLists.txt create mode 100644 samples/drivers/crc/README.rst create mode 100644 samples/drivers/crc/prj.conf create mode 100644 samples/drivers/crc/sample.yaml create mode 100644 samples/drivers/crc/src/main.c diff --git a/samples/drivers/crc/CMakeLists.txt b/samples/drivers/crc/CMakeLists.txt new file mode 100644 index 0000000000000..710a2cf5c4dbb --- /dev/null +++ b/samples/drivers/crc/CMakeLists.txt @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: Apache-2.0 + +cmake_minimum_required(VERSION 3.20.0) +find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) +project(driver_crc_example) + +target_sources(app PRIVATE src/main.c) diff --git a/samples/drivers/crc/README.rst b/samples/drivers/crc/README.rst new file mode 100644 index 0000000000000..947fb1c50c0f3 --- /dev/null +++ b/samples/drivers/crc/README.rst @@ -0,0 +1,53 @@ +.. zephyr:code-sample:: crc_drivers + :name: Cyclic Redundancy Check Drivers (CRC) + :relevant-api: crc_interface + + Compute and verify a CRC checksum using the CRC driver API. + +Overview +******** + +This sample demonstrates how to use the :ref:`CRC driver API `. + +Configuration Options +********************* + +This sample supports the following Kconfig options: + +- ``CONFIG_CRC``: Enable CRC driver. + +These options can be modified in the project's ``prj.conf`` file or passed via CMake arguments. + +Building and Running +******************** + +Building and Running for Renesas RA8M1 +====================================== + +The sample can be built and executed for the +:zephyr:board:`ek_ra8m1` as follows: + +.. zephyr-app-commands:: + :zephyr-app: samples/drivers/crc + :board: ek_ra8m1 + :goals: build flash + :compact: + +To build for another board, change "ek_ra8m1" above to that board's name. + +Sample Output +============= + +.. code-block:: console + + crc_example: CRC verification succeed. + +.. note:: If the CRC is not supported, the output will be an error message. + +Expected Behavior +***************** + +When the sample runs, it should: + +1. Compute the CRC8 values of predefined data. +2. Verify the CRC result. diff --git a/samples/drivers/crc/prj.conf b/samples/drivers/crc/prj.conf new file mode 100644 index 0000000000000..411e4bf848c5e --- /dev/null +++ b/samples/drivers/crc/prj.conf @@ -0,0 +1,2 @@ +CONFIG_CRC=y +CONFIG_LOG=y diff --git a/samples/drivers/crc/sample.yaml b/samples/drivers/crc/sample.yaml new file mode 100644 index 0000000000000..7fa3242a2dd1a --- /dev/null +++ b/samples/drivers/crc/sample.yaml @@ -0,0 +1,13 @@ +sample: + name: CRC Sample +tests: + sample.drivers.crc: + depends_on: crc + tags: + - drivers + - crc + harness: console + harness_config: + type: one_line + regex: + - "CRC verification succeeded" diff --git a/samples/drivers/crc/src/main.c b/samples/drivers/crc/src/main.c new file mode 100644 index 0000000000000..f5866982d1c63 --- /dev/null +++ b/samples/drivers/crc/src/main.c @@ -0,0 +1,85 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +LOG_MODULE_REGISTER(crc_example, CONFIG_LOG_DEFAULT_LEVEL); + +#include +#include + +/* The devicetree node identifier for the "crc" */ +#define CRC_NODE DT_NODELABEL(crc) + +/* + * A build error on this line means your board is unsupported. + * See the sample documentation for information on how to fix this. + */ + +int main(void) +{ + static const struct device *const dev = DEVICE_DT_GET(CRC_NODE); + /* Define the data to compute CRC */ + uint8_t data[8] = {0x0A, 0x2B, 0x4C, 0x6D, 0x8E, 0x49, 0x00, 0xC4}; + int ret; + + if (!device_is_ready(dev)) { + LOG_ERR("Device is not ready"); + return -ENODEV; + } + + struct crc_ctx ctx = { + .type = CRC8, + .polynomial = CRC8_POLY, + .seed = CRC8_INIT_VAL, + .reversed = CRC_FLAG_REVERSE_OUTPUT | CRC_FLAG_REVERSE_INPUT, + }; + + /* Start CRC computation */ + ret = crc_begin(dev, &ctx); + + if (ret != 0) { + LOG_ERR("Failed to begin CRC: %d", ret); + return ret; + } + + /* Update CRC computation */ + ret = crc_update(dev, &ctx, data, 8); + + if (ret != 0) { + LOG_ERR("Failed to update CRC: %d", ret); + return ret; + } + + /* Finish CRC computation */ + ret = crc_finish(dev, &ctx); + + if (ret != 0) { + LOG_ERR("Failed to finish CRC: %d", ret); + return ret; + } + /* Verify CRC computation + * (example expected value: 0xB2 with LSB, 0x4D with MSB bit order) + */ + if (ctx.reversed != (CRC_FLAG_REVERSE_OUTPUT | CRC_FLAG_REVERSE_INPUT)) { + ret = crc_verify(&ctx, 0x4D); + + if (ret != 0) { + LOG_ERR("CRC verification failed: %d", ret); + return ret; + } + } else { /* Reversed is no reversed output */ + ret = crc_verify(&ctx, 0xB2); + + if (ret != 0) { + LOG_ERR("CRC verification failed: %d", ret); + return ret; + } + } + + LOG_INF("CRC verification succeeded"); + + return 0; +} From 3ec2249b4020ce75a25174b2d5314e28b7f22fb6 Mon Sep 17 00:00:00 2001 From: Duy Vo Date: Fri, 14 Mar 2025 16:55:13 +0700 Subject: [PATCH 6/9] samples: subsys: crc: add samples for CRC subsystem Add samples for CRC subsystem Signed-off-by: Duy Vo --- samples/subsys/crc/CMakeLists.txt | 7 ++++ samples/subsys/crc/README.rst | 57 +++++++++++++++++++++++++++++++ samples/subsys/crc/prj.conf | 2 ++ samples/subsys/crc/sample.yaml | 13 +++++++ samples/subsys/crc/src/main.c | 28 +++++++++++++++ 5 files changed, 107 insertions(+) create mode 100644 samples/subsys/crc/CMakeLists.txt create mode 100644 samples/subsys/crc/README.rst create mode 100644 samples/subsys/crc/prj.conf create mode 100644 samples/subsys/crc/sample.yaml create mode 100644 samples/subsys/crc/src/main.c diff --git a/samples/subsys/crc/CMakeLists.txt b/samples/subsys/crc/CMakeLists.txt new file mode 100644 index 0000000000000..ba3b28b077e75 --- /dev/null +++ b/samples/subsys/crc/CMakeLists.txt @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: Apache-2.0 + +cmake_minimum_required(VERSION 3.20.0) +find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) +project(subsys_crc_example) + +target_sources(app PRIVATE src/main.c) diff --git a/samples/subsys/crc/README.rst b/samples/subsys/crc/README.rst new file mode 100644 index 0000000000000..57ed683408025 --- /dev/null +++ b/samples/subsys/crc/README.rst @@ -0,0 +1,57 @@ +.. zephyr:code-sample:: crc_subsys + :name: Cyclic Redundancy Check Subsystem (CRC Subsys) + + Compute and verify a CRC computation using the CRC subsys API. + +Overview +******** + +This sample demonstrates how to use the Cyclic Redundancy Check Subsystem + +Configuration Options +********************* + +This sample supports the following Kconfig options: + +- ``CONFIG_CRC``: Enable CRC functionality. +- ``CONFIG_CRC*``: Use software-based CRC if a chosen node is present; otherwise, hardware acceleration is used. + +These options can be modified in the project's ``prj.conf`` file or passed via CMake arguments. + +Building and Running +******************** + +Building and Running for Renesas RA8M1 +====================================== + +The sample can be built and executed for the +:zephyr:board:`ek_ra8m1` as follows: + +.. zephyr-app-commands:: + :zephyr-app: samples/subsys/crc + :board: ek_ra8m1 + :goals: build flash + :compact: + +To build for another board, change "ek_ra8m1" above to that board's name. + +Sample Output +============= + +.. code-block:: console + + subsys_crc_example: Result of CRC32 IEEE: 0xCEA4A6C2 + subsys_crc_example: Result of CRC8 CCITT: 0x96 + subsys_crc_example: CRC computation completed successfully + +.. note:: + If the board does not support a hardware CRC driver, the computation will fall + back to a software-based implementation. + +Expected Behavior +***************** + +When the sample runs, it should: + +1. Compute the CRC32 and CRC8 values of predefined data. +2. Print the computed CRC values. diff --git a/samples/subsys/crc/prj.conf b/samples/subsys/crc/prj.conf new file mode 100644 index 0000000000000..411e4bf848c5e --- /dev/null +++ b/samples/subsys/crc/prj.conf @@ -0,0 +1,2 @@ +CONFIG_CRC=y +CONFIG_LOG=y diff --git a/samples/subsys/crc/sample.yaml b/samples/subsys/crc/sample.yaml new file mode 100644 index 0000000000000..106b3cc611d65 --- /dev/null +++ b/samples/subsys/crc/sample.yaml @@ -0,0 +1,13 @@ +sample: + name: CRC Subsystem +tests: + samples.subsys.crc: + depends_on: crc + tags: + - subsys + - crc + harness: console + harness_config: + type: one_line + regex: + - "CRC computation completed successfully" diff --git a/samples/subsys/crc/src/main.c b/samples/subsys/crc/src/main.c new file mode 100644 index 0000000000000..c677508146e09 --- /dev/null +++ b/samples/subsys/crc/src/main.c @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +LOG_MODULE_REGISTER(subsys_crc_example, CONFIG_LOG_DEFAULT_LEVEL); + +#include + +int main(void) +{ + uint32_t result; + uint8_t data[8] = {0x0A, 0x2B, 0x4C, 0x6D, 0x8E, 0x49, 0x00, 0xC4}; + + /* CRC computation */ + result = crc32_ieee(data, sizeof(data)); + LOG_INF("Result of CRC32 IEEE: 0x%08X", result); + + /* CRC computation */ + result = (uint8_t)crc8_ccitt(0xFF, data, sizeof(data)); + LOG_INF("Result of CRC8 CCITT: 0x%02X", result & 0xFF); + + LOG_INF("CRC computation completed successfully"); + + return 0; +} From 70037d7f4e76914e176404da5a4ad642c4975b4a Mon Sep 17 00:00:00 2001 From: Duy Vo Date: Fri, 14 Mar 2025 16:56:24 +0700 Subject: [PATCH 7/9] tests: drivers: crc: add ztests for CRC driver Add ztests for CRC driver Signed-off-by: Duy Vo --- tests/drivers/crc/CMakeLists.txt | 6 + tests/drivers/crc/prj.conf | 3 + tests/drivers/crc/src/main.c | 329 +++++++++++++++++++++++++++++++ tests/drivers/crc/testcase.yaml | 7 + 4 files changed, 345 insertions(+) create mode 100644 tests/drivers/crc/CMakeLists.txt create mode 100644 tests/drivers/crc/prj.conf create mode 100644 tests/drivers/crc/src/main.c create mode 100644 tests/drivers/crc/testcase.yaml diff --git a/tests/drivers/crc/CMakeLists.txt b/tests/drivers/crc/CMakeLists.txt new file mode 100644 index 0000000000000..eb356a6dc870e --- /dev/null +++ b/tests/drivers/crc/CMakeLists.txt @@ -0,0 +1,6 @@ +cmake_minimum_required(VERSION 3.20.0) +find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) + +project(drivers_crc_test) + +target_sources(app PRIVATE src/main.c) diff --git a/tests/drivers/crc/prj.conf b/tests/drivers/crc/prj.conf new file mode 100644 index 0000000000000..e5d697260b126 --- /dev/null +++ b/tests/drivers/crc/prj.conf @@ -0,0 +1,3 @@ +CONFIG_ZTEST=y +CONFIG_CRC=y +CONFIG_CRC_LOG_LEVEL_INF=y diff --git a/tests/drivers/crc/src/main.c b/tests/drivers/crc/src/main.c new file mode 100644 index 0000000000000..253a566ea2c1b --- /dev/null +++ b/tests/drivers/crc/src/main.c @@ -0,0 +1,329 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +#include +#include +#include + +#define WAIT_THREAD_STACK_SIZE 1024 +#define WAIT_THREAD_PRIO -10 + +static void wait_thread_entry(void *a, void *b, void *c); + +K_THREAD_STACK_DEFINE(wait_thread_stack_area, WAIT_THREAD_STACK_SIZE); +struct k_thread wait_thread_data; + +/* Define result of CRC computation */ +#define RESULT_CRC_16_THREADSAFE 0xD543 + +/** + * 1) Take the semaphore + * 2) Sleep for 50 ms (to allow ztest main thread to attempt to acquire semaphore) + * 3) Give the semaphore + */ +static void wait_thread_entry(void *a, void *b, void *c) +{ + static const struct device *dev = DEVICE_DT_GET(DT_NODELABEL(crc)); + + uint8_t data[8] = {0x0A, 0x2B, 0x4C, 0x6D, 0x8E, 0x49, 0x00, 0xC4}; + + struct crc_ctx ctx = { + .type = CRC16, + .polynomial = CRC16_POLY, + .seed = CRC16_INIT_VAL, + .reversed = CRC_FLAG_REVERSE_OUTPUT | CRC_FLAG_REVERSE_INPUT, + }; + + crc_begin(dev, &ctx); + + k_sleep(K_MSEC(50)); + + crc_update(dev, &ctx, data, sizeof(data)); + crc_finish(dev, &ctx); + zassert_equal(crc_verify(&ctx, RESULT_CRC_16_THREADSAFE), 0); +} + +/* Define result of CRC computation */ +#define RESULT_CRC_8 0xB2 + +/** + * @brief Test that crc8 works + */ +ZTEST(crc, test_crc_8) +{ + static const struct device *dev = DEVICE_DT_GET(DT_NODELABEL(crc)); + + uint8_t data[8] = {0x0A, 0x2B, 0x4C, 0x6D, 0x8E, 0x49, 0x00, 0xC4}; + + struct crc_ctx ctx = { + .type = CRC8, + .polynomial = CRC8_POLY, + .seed = CRC8_INIT_VAL, + .reversed = CRC_FLAG_REVERSE_OUTPUT | CRC_FLAG_REVERSE_INPUT, + }; + + crc_begin(dev, &ctx); + + k_sleep(K_MSEC(50)); + + crc_update(dev, &ctx, data, sizeof(data)); + crc_finish(dev, &ctx); + zassert_equal(crc_verify(&ctx, RESULT_CRC_8), 0); +} + +/* Define result of CRC computation */ +#define RESULT_CRC_16 0xD543 + +/** + * @brief Test that crc16 works + */ +ZTEST(crc, test_crc_16) +{ + static const struct device *dev = DEVICE_DT_GET(DT_NODELABEL(crc)); + + uint8_t data[8] = {0x0A, 0x2B, 0x4C, 0x6D, 0x8E, 0x49, 0x00, 0xC4}; + + struct crc_ctx ctx = { + .type = CRC16, + .polynomial = CRC16_POLY, + .seed = CRC16_INIT_VAL, + .reversed = CRC_FLAG_REVERSE_OUTPUT | CRC_FLAG_REVERSE_INPUT, + }; + + zassert_equal(crc_begin(dev, &ctx), 0); + zassert_equal(crc_update(dev, &ctx, data, sizeof(data)), 0); + zassert_equal(crc_finish(dev, &ctx), 0); + + zassert_equal(crc_verify(&ctx, RESULT_CRC_16), 0); +} + +/* Define result of CRC computation */ +#define RESULT_CRC_CCITT 0x445C + +/** + * @brief Test that crc_16_ccitt works + */ +ZTEST(crc, test_crc_16_ccitt) +{ + static const struct device *dev = DEVICE_DT_GET(DT_NODELABEL(crc)); + + uint8_t data[8] = {0x0A, 0x2B, 0x4C, 0x6D, 0x8E, 0x49, 0x00, 0xC4}; + + struct crc_ctx ctx = { + .type = CRC16_CCITT, + .polynomial = CRC16_CCITT_POLY, + .seed = CRC16_CCITT_INIT_VAL, + .reversed = CRC_FLAG_REVERSE_OUTPUT | CRC_FLAG_REVERSE_INPUT, + }; + + zassert_equal(crc_begin(dev, &ctx), 0); + zassert_equal(crc_update(dev, &ctx, data, sizeof(data)), 0); + zassert_equal(crc_finish(dev, &ctx), 0); + + zassert_equal(crc_verify(&ctx, RESULT_CRC_CCITT), 0); +} + +/* Define result of CRC computation */ +#define RESULT_CRC_32_C 0xBB19ECB2 + +/** + * @brief Test that crc_32_c works + */ +ZTEST(crc, test_crc_32_c) +{ + static const struct device *dev = DEVICE_DT_GET(DT_NODELABEL(crc)); + + uint8_t data[8] = {0x0A, 0x2B, 0x4C, 0x6D, 0x8E, 0x49, 0x00, 0xC4}; + + struct crc_ctx ctx = { + .type = CRC32_C, + .polynomial = CRC32C_POLY, + .seed = CRC32_C_INIT_VAL, + .reversed = CRC_FLAG_REVERSE_OUTPUT | CRC_FLAG_REVERSE_INPUT, + }; + + zassert_equal(crc_begin(dev, &ctx), 0); + zassert_equal(crc_update(dev, &ctx, data, sizeof(data)), 0); + zassert_equal(crc_finish(dev, &ctx), 0); + + zassert_equal(crc_verify(&ctx, RESULT_CRC_32_C), 0); +} + +/* Define result of CRC computation */ +#define RESULT_CRC_32_IEEE 0xCEA4A6C2 + +/** + * @brief Test that crc_32_ieee works + */ +ZTEST(crc, test_crc_32_ieee) +{ + static const struct device *dev = DEVICE_DT_GET(DT_NODELABEL(crc)); + + uint8_t data[8] = {0x0A, 0x2B, 0x4C, 0x6D, 0x8E, 0x49, 0x00, 0xC4}; + struct crc_ctx ctx = { + .type = CRC32_IEEE, + .polynomial = CRC32_IEEE_POLY, + .seed = CRC32_IEEE_INIT_VAL, + .reversed = CRC_FLAG_REVERSE_OUTPUT | CRC_FLAG_REVERSE_INPUT, + }; + + zassert_equal(crc_begin(dev, &ctx), 0); + zassert_equal(crc_update(dev, &ctx, data, sizeof(data)), 0); + zassert_equal(crc_finish(dev, &ctx), 0); + zassert_equal(crc_verify(&ctx, RESULT_CRC_32_IEEE), 0); +} + +/* Define result of CRC computation */ +#define RESULT_CRC_8_REMAIN_3 0xBB + +/** + * @brief Test that crc_8_remain_3 works + */ +ZTEST(crc, test_crc_8_remain_3) +{ + static const struct device *dev = DEVICE_DT_GET(DT_NODELABEL(crc)); + + uint8_t data[11] = {0x0A, 0x2B, 0x4C, 0x6D, 0x8E, 0x49, 0x00, 0xC4, 0x3D, 0x4D, 0x51}; + + struct crc_ctx ctx = { + .type = CRC8, + .polynomial = CRC8_POLY, + .seed = CRC8_INIT_VAL, + .reversed = CRC_FLAG_REVERSE_OUTPUT | CRC_FLAG_REVERSE_INPUT, + }; + + zassert_equal(crc_begin(dev, &ctx), 0); + zassert_equal(crc_update(dev, &ctx, data, sizeof(data)), 0); + zassert_equal(crc_finish(dev, &ctx), 0); + zassert_equal(crc_verify(&ctx, RESULT_CRC_8_REMAIN_3), 0); +} + +/* Define result of CRC computation */ +#define RESULT_CRC_16_REMAIN_1 0x2055 + +/** + * @brief Test that crc_16_remain_1 works + */ +ZTEST(crc, test_crc_16_remain_1) +{ + static const struct device *dev = DEVICE_DT_GET(DT_NODELABEL(crc)); + + uint8_t data[9] = {0x0A, 0x2B, 0x4C, 0x6D, 0x8E, 0x49, 0x00, 0xC4, 0x3D}; + + struct crc_ctx ctx = { + .type = CRC16, + .polynomial = CRC16_POLY, + .seed = CRC16_INIT_VAL, + .reversed = CRC_FLAG_REVERSE_OUTPUT | CRC_FLAG_REVERSE_INPUT, + }; + + zassert_equal(crc_begin(dev, &ctx), 0); + zassert_equal(crc_update(dev, &ctx, data, sizeof(data)), 0); + zassert_equal(crc_finish(dev, &ctx), 0); + + zassert_equal(crc_verify(&ctx, RESULT_CRC_16_REMAIN_1), 0); +} + +/* Define result of CRC computation */ +#define RESULT_CRC_CCITT_REMAIN_2 0x24BD + +/** + * @brief Test that crc_16_ccitt works + */ +ZTEST(crc, test_crc_16_ccitt_remain_2) +{ + static const struct device *dev = DEVICE_DT_GET(DT_NODELABEL(crc)); + + uint8_t data[10] = {0x0A, 0x2B, 0x4C, 0x6D, 0x8E, 0x49, 0x00, 0xC4, 0xFF, 0xA0}; + + struct crc_ctx ctx = { + .type = CRC16_CCITT, + .polynomial = CRC16_CCITT_POLY, + .seed = CRC16_CCITT_INIT_VAL, + .reversed = CRC_FLAG_REVERSE_OUTPUT | CRC_FLAG_REVERSE_INPUT, + }; + + zassert_equal(crc_begin(dev, &ctx), 0); + zassert_equal(crc_update(dev, &ctx, data, sizeof(data)), 0); + zassert_equal(crc_finish(dev, &ctx), 0); + + zassert_equal(crc_verify(&ctx, RESULT_CRC_CCITT_REMAIN_2), 0); +} + +/* Define result of CRC computation */ +#define RESULT_DISCONTINUOUS_BUFFER 0x75 + +/** + * @brief Test CRC calculation with discontinuous buffers. + */ +ZTEST(crc, test_discontinuous_buf) +{ + static const struct device *dev = DEVICE_DT_GET(DT_NODELABEL(crc)); + + uint8_t data1[5] = {0x0A, 0x2B, 0x4C, 0x6D, 0x8E}; + uint8_t data2[5] = {0x49, 0x00, 0xC4, 0x3B, 0x78}; + + struct crc_ctx ctx = { + .type = CRC8, + .polynomial = CRC8_POLY, + .seed = CRC8_INIT_VAL, + .reversed = CRC_FLAG_REVERSE_INPUT | CRC_FLAG_REVERSE_OUTPUT, + }; + + zassert_equal(crc_begin(dev, &ctx), 0); + zassert_equal(crc_update(dev, &ctx, data1, sizeof(data1)), 0); + zassert_equal(crc_update(dev, &ctx, data2, sizeof(data2)), 0); + zassert_equal(crc_finish(dev, &ctx), 0); + zassert_equal(crc_verify(&ctx, RESULT_DISCONTINUOUS_BUFFER), 0); +} + +/* Define result of CRC computation */ +#define RESULT_CRC_8_REMAIN_3_THREADSAFE 0xBB + +/** + * @brief Test CRC function semaphore wait for thread safety + * + * Verifies that CRC operations are blocked until a semaphore is released. A new thread + * acquires the semaphore, and the main thread's CRC operations wait until it is released. + */ +ZTEST(crc, test_crc_threadsafe) +{ + static const struct device *dev = DEVICE_DT_GET(DT_NODELABEL(crc)); + + uint8_t data[11] = {0x0A, 0x2B, 0x4C, 0x6D, 0x8E, 0x49, 0x00, 0xC4, 0x3D, 0x4D, 0x51}; + + struct crc_ctx ctx = { + .type = CRC8, + .polynomial = CRC8_POLY, + .seed = CRC8_INIT_VAL, + .reversed = CRC_FLAG_REVERSE_OUTPUT | CRC_FLAG_REVERSE_INPUT, + }; + + /** + * Create new thread that will immediately take the semaphore + */ + k_thread_create(&wait_thread_data, wait_thread_stack_area, + K_THREAD_STACK_SIZEOF(wait_thread_stack_area), wait_thread_entry, NULL, + NULL, NULL, WAIT_THREAD_PRIO, 0, K_NO_WAIT); + + /** + * Sleep for 10 ms to ensure that new thread has taken lock + */ + k_sleep(K_MSEC(10)); + + /** + * Attempt to take semaphore, this should wait for the new thread to give the semaphore + * before executing + */ + crc_begin(dev, &ctx); + crc_update(dev, &ctx, data, sizeof(data)); + crc_finish(dev, &ctx); + zassert_equal(crc_verify(&ctx, RESULT_CRC_8_REMAIN_3_THREADSAFE), 0); +} + +ZTEST_SUITE(crc, NULL, NULL, NULL, NULL, NULL); diff --git a/tests/drivers/crc/testcase.yaml b/tests/drivers/crc/testcase.yaml new file mode 100644 index 0000000000000..f37cdba09cbcf --- /dev/null +++ b/tests/drivers/crc/testcase.yaml @@ -0,0 +1,7 @@ +tests: + drivers.crc: + depends_on: crc + tags: + - drivers + - crc + harness: ztest From b0115b047501472af0074df87d9278ef6ad671c8 Mon Sep 17 00:00:00 2001 From: Duy Vo Date: Fri, 14 Mar 2025 16:57:06 +0700 Subject: [PATCH 8/9] tests: subsys: crc: add ztests for CRC subsystem Add ztests for CRC subsystem Signed-off-by: Duy Vo --- tests/subsys/crc/CMakeLists.txt | 6 + tests/subsys/crc/prj.conf | 3 + tests/subsys/crc/src/main.c | 192 ++++++++++++++++++++++++++++++++ tests/subsys/crc/testcase.yaml | 7 ++ 4 files changed, 208 insertions(+) create mode 100644 tests/subsys/crc/CMakeLists.txt create mode 100644 tests/subsys/crc/prj.conf create mode 100644 tests/subsys/crc/src/main.c create mode 100644 tests/subsys/crc/testcase.yaml diff --git a/tests/subsys/crc/CMakeLists.txt b/tests/subsys/crc/CMakeLists.txt new file mode 100644 index 0000000000000..4046fc42d0c25 --- /dev/null +++ b/tests/subsys/crc/CMakeLists.txt @@ -0,0 +1,6 @@ +cmake_minimum_required(VERSION 3.20.0) +find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) + +project(subsys_crc_test) + +target_sources(app PRIVATE src/main.c) diff --git a/tests/subsys/crc/prj.conf b/tests/subsys/crc/prj.conf new file mode 100644 index 0000000000000..d187aba6a129d --- /dev/null +++ b/tests/subsys/crc/prj.conf @@ -0,0 +1,3 @@ +CONFIG_ZTEST=y +CONFIG_CRC=y +CONFIG_LOG=y diff --git a/tests/subsys/crc/src/main.c b/tests/subsys/crc/src/main.c new file mode 100644 index 0000000000000..b01693599bfe8 --- /dev/null +++ b/tests/subsys/crc/src/main.c @@ -0,0 +1,192 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include +#include +#include +#include + +/* Define result of CRC computation */ +#define RESULT_CRC8 0xB2 + +/** + * @brief Test crc8 works + */ +ZTEST(crc_subsys, test_crc_8) +{ + uint8_t data[8] = {0x0A, 0x2B, 0x4C, 0x6D, 0x8E, 0x49, 0x00, 0xC4}; + + zassert_equal(crc8(data, sizeof(data), CRC8_REFLECT_POLY, 0x00, true), RESULT_CRC8); +} + +/* Define result of CRC computation */ +#define RESULT_CRC8_CCITT 0x4D + +/** + * @brief Test crc8_ccitt works + */ +ZTEST(crc_subsys, test_crc_8_ccitt) +{ + uint8_t data[8] = {0x0A, 0x2B, 0x4C, 0x6D, 0x8E, 0x49, 0x00, 0xC4}; + + zassert_equal(crc8_ccitt(0x00, data, sizeof(data)), RESULT_CRC8_CCITT); +} + +/* Define result of CRC computation */ +#define RESULT_CRC8_ROHC 0xB2 + +/** + * @brief Test that crc_8_rohc works + */ +ZTEST(crc_subsys, test_crc_8_rohc) +{ + uint8_t data[8] = {0x0A, 0x2B, 0x4C, 0x6D, 0x8E, 0x49, 0x00, 0xC4}; + + zassert_equal(crc8_rohc(0x00, data, sizeof(data)), RESULT_CRC8_ROHC); +} + +/* Define result of CRC computation */ +#define RESULT_CRC16 0xE58F + +/** + * @brief Test that crc_16 works + */ +ZTEST(crc_subsys, test_crc_16) +{ + uint8_t data[8] = {0x0A, 0x2B, 0x4C, 0x6D, 0x8E, 0x49, 0x00, 0xC4}; + + zassert_equal(crc16(CRC16_POLY, CRC16_INIT_VAL, data, sizeof(data)), RESULT_CRC16); +} +/* Define result of CRC computation */ +#define RESULT_CRC16_REFLECT 0xD543 + +/** + * @brief Test that crc_16_reflect works + */ +ZTEST(crc_subsys, test_crc_16_reflect) +{ + uint8_t data[8] = {0x0A, 0x2B, 0x4C, 0x6D, 0x8E, 0x49, 0x00, 0xC4}; + + zassert_equal(crc16_reflect(CRC16_REFLECT_POLY, CRC16_INIT_VAL, data, sizeof(data)), + RESULT_CRC16_REFLECT); +} + +/* Define result of CRC computation */ +#define RESULT_CRC16_ANSI 0xDE03 + +/** + * @brief Test that crc_16_ansi works + */ +ZTEST(crc_subsys, test_crc_16_ansi) +{ + uint8_t data[8] = {0x0A, 0x2B, 0x4C, 0x6D, 0x8E, 0x49, 0x00, 0xC4}; + + zassert_equal(crc16_ansi(data, sizeof(data)), RESULT_CRC16_ANSI); +} + +/* Define result of CRC computation */ +#define RESULT_CRC_CCITT 0x445C + +/** + * @brief Test that crc_16_ccitt works + */ +ZTEST(crc_subsys, test_crc_16_ccitt) +{ + uint8_t data[8] = {0x0A, 0x2B, 0x4C, 0x6D, 0x8E, 0x49, 0x00, 0xC4}; + + zassert_equal(crc16_ccitt(0x0000, data, sizeof(data)), RESULT_CRC_CCITT); +} + +/* Define result of CRC computation */ +#define RESULT_CRC16_ITU_T 0x8866 + +/** + * @brief Test that crc_16_itu_t works + */ +ZTEST(crc_subsys, test_crc_16_itu_t) +{ + uint8_t data[8] = {0x0A, 0x2B, 0x4C, 0x6D, 0x8E, 0x49, 0x00, 0xC4}; + + zassert_equal(crc16_itu_t(0x0000, data, sizeof(data)), RESULT_CRC16_ITU_T); +} + +/* Define result of CRC computation */ +#define RESULT_CRC32_C 0xBB19ECB2 + +/** + * @brief Test that crc32_c works + */ +ZTEST(crc_subsys, test_crc_32_c) +{ + uint8_t data[8] = {0x0A, 0x2B, 0x4C, 0x6D, 0x8E, 0x49, 0x00, 0xC4}; + + zassert_equal(crc32_c(0x000, data, sizeof(data), true, false), RESULT_CRC32_C); +} +/* Define result of CRC computation */ +#define RESULT_CRC32_IEEE 0xCEA4A6C2 + +/** + * @brief Test that crc_32_ieee works + */ +ZTEST(crc_subsys, test_crc_32_ieee) +{ + uint8_t data[8] = {0x0A, 0x2B, 0x4C, 0x6D, 0x8E, 0x49, 0x00, 0xC4}; + + zassert_equal(crc32_ieee(data, sizeof(data)), RESULT_CRC32_IEEE); +} + +/* Define result of CRC computation */ +#define RESULT_CRC8_CCITT_REMAIN_1 0x57 + +/** + * @brief Test crc8_ccitt_remain_1 work + */ +ZTEST(crc_subsys, test_crc_8_ccitt_remain_1) +{ + uint8_t data[9] = {0x0A, 0x2B, 0x4C, 0x6D, 0x8E, 0x49, 0x00, 0xC4, 0x3D}; + + zassert_equal(crc8_ccitt(0x00, data, sizeof(data)), RESULT_CRC8_CCITT_REMAIN_1); +} + +/* Define result of CRC computation */ +#define RESULT_CRC8_ROHC_REMAIN_2 0x4F + +/** + * @brief Test that crc_8_rohc_remain_2 works + */ +ZTEST(crc_subsys, test_crc_8_rohc_remain_2) +{ + uint8_t data[10] = {0x0A, 0x2B, 0x4C, 0x6D, 0x8E, 0x49, 0x00, 0xC4, 0x3D, 0xFF}; + + zassert_equal(crc8_rohc(0x00, data, sizeof(data)), RESULT_CRC8_ROHC_REMAIN_2); +} + +/* Define result of CRC computation */ +#define RESULT_CRC_CCITT_REMAIN_3 0x454B + +/** + * @brief Test that crc_16_ccitt_remain_3 works + */ +ZTEST(crc_subsys, test_crc_16_ccitt_remain_3) +{ + uint8_t data[11] = {0x0A, 0x2B, 0x4C, 0x6D, 0x8E, 0x49, 0x00, 0xC4, 0x3D, 0xFF, 0xE2}; + + zassert_equal(crc16_ccitt(0x0000, data, sizeof(data)), RESULT_CRC_CCITT_REMAIN_3); +} + +/* Define result of CRC computation */ +#define RESULT_CRC16_ITU_T_REMAIN_1 0x917E + +/** + * @brief Test that crc_16_itu_t_remain_1 works + */ +ZTEST(crc_subsys, test_crc_16_itu_t_remain_1) +{ + uint8_t data[9] = {0x0A, 0x2B, 0x4C, 0x6D, 0x8E, 0x49, 0x00, 0xC4, 0x3D}; + + zassert_equal(crc16_itu_t(0x0000, data, sizeof(data)), RESULT_CRC16_ITU_T_REMAIN_1); +} + +ZTEST_SUITE(crc_subsys, NULL, NULL, NULL, NULL, NULL); diff --git a/tests/subsys/crc/testcase.yaml b/tests/subsys/crc/testcase.yaml new file mode 100644 index 0000000000000..6e8f87cc10fbd --- /dev/null +++ b/tests/subsys/crc/testcase.yaml @@ -0,0 +1,7 @@ +tests: + subsys.crc: + depends_on: crc + tags: + - subsys + - crc + harness: ztest From 772ccd48ce36e52061df949ed3b88d452cbe4c1a Mon Sep 17 00:00:00 2001 From: The Nguyen Date: Mon, 14 Apr 2025 14:05:15 +0700 Subject: [PATCH 9/9] tests: crc: update include path for CRC unit test Due to the move of lib/crc to subsys/crc, the include path of CRC handler in this test should be updated: - tests/unit/crc Signed-off-by: The Nguyen --- tests/unit/crc/main.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/tests/unit/crc/main.c b/tests/unit/crc/main.c index f2c2b91fd5b59..a8aa842ba54ad 100644 --- a/tests/unit/crc/main.c +++ b/tests/unit/crc/main.c @@ -6,14 +6,14 @@ #include #include -#include "../../../lib/crc/crc8_sw.c" -#include "../../../lib/crc/crc16_sw.c" -#include "../../../lib/crc/crc32_sw.c" -#include "../../../lib/crc/crc32c_sw.c" -#include "../../../lib/crc/crc7_sw.c" -#include "../../../lib/crc/crc24_sw.c" -#include "../../../lib/crc/crc4_sw.c" -#include "../../../lib/crc/crc32k_4_2_sw.c" +#include "../../../subsys/crc/crc8_sw.c" +#include "../../../subsys/crc/crc16_sw.c" +#include "../../../subsys/crc/crc32_sw.c" +#include "../../../subsys/crc/crc32c_sw.c" +#include "../../../subsys/crc/crc7_sw.c" +#include "../../../subsys/crc/crc24_sw.c" +#include "../../../subsys/crc/crc4_sw.c" +#include "../../../subsys/crc/crc32k_4_2_sw.c" ZTEST(crc, test_crc32_k_4_2) {