From f7faedd2711b919bdbd414ea7a0de8f16b5c737b Mon Sep 17 00:00:00 2001 From: TOKITA Hiroshi Date: Sat, 10 Aug 2024 19:37:24 +0900 Subject: [PATCH 01/25] manifest: update hal_rpi_pico Update RaspberryPi Pico hal to 2.0.0 release Signed-off-by: TOKITA Hiroshi --- west.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/west.yml b/west.yml index 58ab293197f9..fe98d53df823 100644 --- a/west.yml +++ b/west.yml @@ -219,7 +219,7 @@ manifest: - hal - name: hal_rpi_pico path: modules/hal/rpi_pico - revision: fba7162cc7bee06d0149622bbcaac4e41062d368 + revision: pull/6/head groups: - hal - name: hal_silabs From 2f249311a619e884e15131919c7e43cca229d3a2 Mon Sep 17 00:00:00 2001 From: TOKITA Hiroshi Date: Fri, 9 Aug 2024 22:56:51 +0900 Subject: [PATCH 02/25] modules: hal_rpi_pico: Update to fit for 2.0.0 directory structure The directory structure has changed in 2.0.0, so we update it accordingly. Signed-off-by: TOKITA Hiroshi --- modules/hal_rpi_pico/CMakeLists.txt | 37 +++++++++++-------- .../hal_rpi_pico/bootloader/CMakeLists.txt | 9 +++-- 2 files changed, 27 insertions(+), 19 deletions(-) diff --git a/modules/hal_rpi_pico/CMakeLists.txt b/modules/hal_rpi_pico/CMakeLists.txt index b68c2efdb37e..c91e64679925 100644 --- a/modules/hal_rpi_pico/CMakeLists.txt +++ b/modules/hal_rpi_pico/CMakeLists.txt @@ -8,7 +8,7 @@ if(CONFIG_HAS_RPI_PICO) set(rp2_common_dir ${ZEPHYR_HAL_RPI_PICO_MODULE_DIR}/src/rp2_common) set(rp2040_dir ${ZEPHYR_HAL_RPI_PICO_MODULE_DIR}/src/rp2040) set(common_dir ${ZEPHYR_HAL_RPI_PICO_MODULE_DIR}/src/common) - set(boot_stage_dir ${rp2_common_dir}/boot_stage2) + set(boot_stage_dir ${rp2040_dir}/boot_stage2) # The Second Stage Bootloader is only linked to the app that resides # at 0x100. Therefore, only if the app's offset is 0x100, the second @@ -46,6 +46,8 @@ if(CONFIG_HAS_RPI_PICO) zephyr_library_sources(${rp2_bootloader_asm}) endif() + zephyr_compile_definitions(PICO_RP2040) + # Pico sources and headers necessary for every build. # These contain definitions and implementation used mostly for # initializing the SoC, and therefore are always required. @@ -55,11 +57,12 @@ if(CONFIG_HAS_RPI_PICO) ${rp2_common_dir}/hardware_pll/pll.c ${rp2_common_dir}/hardware_xosc/xosc.c ${rp2_common_dir}/hardware_watchdog/watchdog.c - ${rp2_common_dir}/pico_platform/platform.c ${rp2_common_dir}/pico_bootrom/bootrom.c + ${rp2040_dir}/pico_platform/platform.c ) zephyr_include_directories( + ${common_dir}/pico_base_headers/include ${rp2_common_dir}/hardware_base/include ${rp2_common_dir}/hardware_clocks/include ${rp2_common_dir}/hardware_watchdog/include @@ -69,11 +72,18 @@ if(CONFIG_HAS_RPI_PICO) ${rp2_common_dir}/hardware_sync/include ${rp2_common_dir}/hardware_timer/include ${rp2_common_dir}/hardware_resets/include + ${rp2_common_dir}/hardware_boot_lock/include + ${rp2_common_dir}/hardware_ticks/include + ${rp2_common_dir}/hardware_sync_spin_lock/include ${rp2_common_dir}/pico_bootrom/include + ${rp2_common_dir}/pico_platform_compiler/include + ${rp2_common_dir}/pico_platform_sections/include + ${rp2_common_dir}/pico_platform_panic/include + ${common_dir}/boot_picoboot_headers/include + ${common_dir}/boot_picobin_headers/include ${rp2040_dir}/hardware_regs/include ${rp2040_dir}/hardware_structs/include - ${common_dir}/pico_base/include - ${rp2_common_dir}/pico_platform/include + ${rp2040_dir}/pico_platform/include ${CMAKE_CURRENT_LIST_DIR} ) @@ -108,16 +118,16 @@ if(CONFIG_HAS_RPI_PICO) zephyr_include_directories_ifdef(CONFIG_PICOSDK_USE_TIMER ${rp2_common_dir}/hardware_timer/include) - zephyr_library_sources_ifdef(CONFIG_PICOSDK_USE_CLAIM - ${rp2_common_dir}/hardware_claim/claim.c) - zephyr_include_directories_ifdef(CONFIG_PICOSDK_USE_CLAIM - ${rp2_common_dir}/hardware_claim/include) - zephyr_library_sources_ifdef(CONFIG_PICOSDK_USE_RTC ${rp2_common_dir}/hardware_rtc/rtc.c) zephyr_include_directories_ifdef(CONFIG_PICOSDK_USE_RTC ${rp2_common_dir}/hardware_rtc/include) + zephyr_library_sources_ifdef(CONFIG_PICOSDK_USE_PIO + ${rp2_common_dir}/hardware_pio/pio.c) + zephyr_include_directories_ifdef(CONFIG_PICOSDK_USE_PIO + ${rp2_common_dir}/hardware_pio/include) + # Some flash driver functions must be executed from the RAM. # Originally pico-sdk places them in the RW data section, so this # implementation does the same. @@ -130,14 +140,9 @@ if(CONFIG_HAS_RPI_PICO) COMPILE_FLAGS $ ) - zephyr_library_sources_ifdef(CONFIG_PICOSDK_USE_PIO - ${rp2_common_dir}/hardware_pio/pio.c) - zephyr_include_directories_ifdef(CONFIG_PICOSDK_USE_PIO - ${rp2_common_dir}/hardware_pio/include) - zephyr_library_sources_ifdef(CONFIG_PICOSDK_USE_CLAIM - ${rp2_common_dir}/hardware_claim/claim.c) + ${common_dir}/hardware_claim/claim.c) zephyr_include_directories_ifdef(CONFIG_PICOSDK_USE_CLAIM - ${rp2_common_dir}/hardware_claim/include) + ${common_dir}/hardware_claim/include) endif() diff --git a/modules/hal_rpi_pico/bootloader/CMakeLists.txt b/modules/hal_rpi_pico/bootloader/CMakeLists.txt index c8faaa67edb9..7e8d39d8951f 100644 --- a/modules/hal_rpi_pico/bootloader/CMakeLists.txt +++ b/modules/hal_rpi_pico/bootloader/CMakeLists.txt @@ -11,7 +11,7 @@ enable_language(ASM) set(rp2_common_dir ${ZEPHYR_HAL_RPI_PICO_MODULE_DIR}/src/rp2_common) set(rp2040_dir ${ZEPHYR_HAL_RPI_PICO_MODULE_DIR}/src/rp2040) set(common_dir ${ZEPHYR_HAL_RPI_PICO_MODULE_DIR}/src/common) -set(boot_stage_dir ${rp2_common_dir}/boot_stage2) +set(boot_stage_dir ${rp2040_dir}/boot_stage2) add_executable(boot_stage2) @@ -34,9 +34,12 @@ target_sources(boot_stage2 PRIVATE ${boot_stage_dir}/${flash_type_file}) target_include_directories(boot_stage2 PUBLIC .. ${boot_stage_dir}/asminclude - ${rp2_common_dir}/pico_platform/include + ${rp2040_dir}/pico_platform/include ${rp2040_dir}/hardware_regs/include - ${common_dir}/pico_base/include + ${common_dir}/pico_base_headers/include + ${rp2_common_dir}/pico_platform_compiler/include + ${rp2_common_dir}/pico_platform_sections/include + ${rp2_common_dir}/pico_platform_panic/include ${ZEPHYR_BASE}/include ) From ffbf439364c853a3077b50524dd2767ce4d28570 Mon Sep 17 00:00:00 2001 From: TOKITA Hiroshi Date: Sat, 10 Aug 2024 19:37:55 +0900 Subject: [PATCH 03/25] drivers: gpio: rpi_pico: Fitting for the changes made in pico-sdk 2.0.0 Following the GPIO interface changes in pico-sdk 2.0.0. Signed-off-by: TOKITA Hiroshi --- drivers/gpio/gpio_rpi_pico.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpio/gpio_rpi_pico.c b/drivers/gpio/gpio_rpi_pico.c index 41ed8e64ecbd..4c5ce08a8fa7 100644 --- a/drivers/gpio/gpio_rpi_pico.c +++ b/drivers/gpio/gpio_rpi_pico.c @@ -192,7 +192,7 @@ static const struct gpio_driver_api gpio_rpi_driver_api = { static void gpio_rpi_isr(const struct device *dev) { struct gpio_rpi_data *data = dev->data; - io_irq_ctrl_hw_t *irq_ctrl_base; + io_bank0_irq_ctrl_hw_t *irq_ctrl_base; const io_rw_32 *status_reg; uint32_t events; uint32_t pin; From 9796fddba87cf69fc847c057926aec9029edc8ae Mon Sep 17 00:00:00 2001 From: TOKITA Hiroshi Date: Sun, 11 Aug 2024 04:45:07 +0900 Subject: [PATCH 04/25] drivers: flash: rpi_pico: Rename to avoid conflicting with SDK Some symbol names have been conflicted with introducing pico-sdk 2.0.0. Rename these. Signed-off-by: TOKITA Hiroshi --- drivers/flash/flash_rpi_pico.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/flash/flash_rpi_pico.c b/drivers/flash/flash_rpi_pico.c index 71231c48043f..0940e94327c8 100644 --- a/drivers/flash/flash_rpi_pico.c +++ b/drivers/flash/flash_rpi_pico.c @@ -171,9 +171,9 @@ void __no_inline_not_in_flash_func(flash_write_partial)(uint32_t flash_offs, con { rom_connect_internal_flash_fn connect_internal_flash = (rom_connect_internal_flash_fn) rom_func_lookup_inline(ROM_FUNC_CONNECT_INTERNAL_FLASH); - rom_flash_exit_xip_fn flash_exit_xip = (rom_flash_exit_xip_fn) + rom_flash_exit_xip_fn exit_xip = (rom_flash_exit_xip_fn) rom_func_lookup_inline(ROM_FUNC_FLASH_EXIT_XIP); - rom_flash_flush_cache_fn flash_flush_cache = (rom_flash_flush_cache_fn) + rom_flash_flush_cache_fn flush_cache = (rom_flash_flush_cache_fn) rom_func_lookup_inline(ROM_FUNC_FLASH_FLUSH_CACHE); flash_init_boot2_copyout(); @@ -181,9 +181,9 @@ void __no_inline_not_in_flash_func(flash_write_partial)(uint32_t flash_offs, con __compiler_memory_barrier(); connect_internal_flash(); - flash_exit_xip(); + exit_xip(); flash_write_partial_internal(flash_offs, data, count); - flash_flush_cache(); + flush_cache(); flash_enable_xip_via_boot2(); } From c8111f820ecbf843fe4c0f121909a0a56b692781 Mon Sep 17 00:00:00 2001 From: Andrew Featherstone Date: Tue, 27 Aug 2024 17:55:49 +0100 Subject: [PATCH 05/25] dts: arm: Move rpi_pico under raspberrypi Follow the wider directory convention of dts///. This is foundation work ahead of introducing support for the RP2350. Signed-off-by: Andrew Featherstone --- CODEOWNERS | 2 +- MAINTAINERS.yml | 2 +- boards/adafruit/kb2040/adafruit_kb2040.dts | 2 +- boards/adafruit/qt_py_rp2040/adafruit_qt_py_rp2040.dts | 2 +- boards/raspberrypi/rpi_pico/rpi_pico-common.dtsi | 2 +- boards/seeed/xiao_rp2040/xiao_rp2040.dts | 2 +- boards/sparkfun/pro_micro_rp2040/sparkfun_pro_micro_rp2040.dts | 2 +- boards/wiznet/w5500_evb_pico/w5500_evb_pico.dts | 2 +- dts/arm/{ => raspberrypi}/rpi_pico/rp2040.dtsi | 0 dts/arm/{ => raspberrypi}/rpi_pico/rpi_pico_common.dtsi | 0 10 files changed, 8 insertions(+), 8 deletions(-) rename dts/arm/{ => raspberrypi}/rpi_pico/rp2040.dtsi (100%) rename dts/arm/{ => raspberrypi}/rpi_pico/rpi_pico_common.dtsi (100%) diff --git a/CODEOWNERS b/CODEOWNERS index 4c737dc9642d..f22493bf63e4 100644 --- a/CODEOWNERS +++ b/CODEOWNERS @@ -422,7 +422,7 @@ /dts/arm/nxp/ @mmahadevan108 @dleach02 /dts/arm/nxp/nxp_s32* @manuargue /dts/arm/microchip/ @franciscomunoz @albertofloyd @sjvasanth1 -/dts/arm/rpi_pico/ @yonsch +/dts/arm/raspberry/rpi_pico/ @yonsch /dts/arm/silabs/efm32_pg_1b.dtsi @rdmeneze /dts/arm/silabs/efm32gg11b* @oanerer /dts/arm/silabs/efr32bg13p* @mnkp diff --git a/MAINTAINERS.yml b/MAINTAINERS.yml index b1ee4baa3f21..02366d128c91 100644 --- a/MAINTAINERS.yml +++ b/MAINTAINERS.yml @@ -3473,7 +3473,7 @@ Raspberry Pi Pico Platforms: - boards/raspberrypi/ - boards/adafruit/kb2040/ - boards/sparkfun/pro_micro_rp2040/ - - dts/arm/rpi_pico/ + - dts/arm/raspberrypi/rpi_pico/ - dts/bindings/*/raspberrypi,pico* - drivers/*/*rpi_pico - drivers/*/*rpi_pico*/ diff --git a/boards/adafruit/kb2040/adafruit_kb2040.dts b/boards/adafruit/kb2040/adafruit_kb2040.dts index 45ff45595d29..b42b196b1738 100644 --- a/boards/adafruit/kb2040/adafruit_kb2040.dts +++ b/boards/adafruit/kb2040/adafruit_kb2040.dts @@ -7,7 +7,7 @@ /dts-v1/; -#include +#include #include "adafruit_kb2040-pinctrl.dtsi" #include "sparkfun_pro_micro_connector.dtsi" #include diff --git a/boards/adafruit/qt_py_rp2040/adafruit_qt_py_rp2040.dts b/boards/adafruit/qt_py_rp2040/adafruit_qt_py_rp2040.dts index 0209c1b86cd2..088325845c4f 100644 --- a/boards/adafruit/qt_py_rp2040/adafruit_qt_py_rp2040.dts +++ b/boards/adafruit/qt_py_rp2040/adafruit_qt_py_rp2040.dts @@ -7,7 +7,7 @@ /dts-v1/; -#include +#include #include "adafruit_qt_py_rp2040-pinctrl.dtsi" #include "seeed_xiao_connector.dtsi" #include diff --git a/boards/raspberrypi/rpi_pico/rpi_pico-common.dtsi b/boards/raspberrypi/rpi_pico/rpi_pico-common.dtsi index 36058ef6483e..f54b444bebda 100644 --- a/boards/raspberrypi/rpi_pico/rpi_pico-common.dtsi +++ b/boards/raspberrypi/rpi_pico/rpi_pico-common.dtsi @@ -6,7 +6,7 @@ #include -#include +#include #include "rpi_pico-pinctrl.dtsi" #include diff --git a/boards/seeed/xiao_rp2040/xiao_rp2040.dts b/boards/seeed/xiao_rp2040/xiao_rp2040.dts index 0a52f47d672d..61c917be38ac 100644 --- a/boards/seeed/xiao_rp2040/xiao_rp2040.dts +++ b/boards/seeed/xiao_rp2040/xiao_rp2040.dts @@ -7,7 +7,7 @@ /dts-v1/; -#include +#include #include "xiao_rp2040-pinctrl.dtsi" #include "seeed_xiao_connector.dtsi" #include diff --git a/boards/sparkfun/pro_micro_rp2040/sparkfun_pro_micro_rp2040.dts b/boards/sparkfun/pro_micro_rp2040/sparkfun_pro_micro_rp2040.dts index 43761b85a142..8c4e5acaf2cb 100644 --- a/boards/sparkfun/pro_micro_rp2040/sparkfun_pro_micro_rp2040.dts +++ b/boards/sparkfun/pro_micro_rp2040/sparkfun_pro_micro_rp2040.dts @@ -6,7 +6,7 @@ /dts-v1/; -#include +#include #include "sparkfun_pro_micro_rp2040-pinctrl.dtsi" #include "sparkfun_pro_micro_connector.dtsi" #include diff --git a/boards/wiznet/w5500_evb_pico/w5500_evb_pico.dts b/boards/wiznet/w5500_evb_pico/w5500_evb_pico.dts index c14cb0b7d649..5f5cf14ccedf 100644 --- a/boards/wiznet/w5500_evb_pico/w5500_evb_pico.dts +++ b/boards/wiznet/w5500_evb_pico/w5500_evb_pico.dts @@ -9,7 +9,7 @@ #include -#include +#include #include "w5500_evb_pico-pinctrl.dtsi" #include diff --git a/dts/arm/rpi_pico/rp2040.dtsi b/dts/arm/raspberrypi/rpi_pico/rp2040.dtsi similarity index 100% rename from dts/arm/rpi_pico/rp2040.dtsi rename to dts/arm/raspberrypi/rpi_pico/rp2040.dtsi diff --git a/dts/arm/rpi_pico/rpi_pico_common.dtsi b/dts/arm/raspberrypi/rpi_pico/rpi_pico_common.dtsi similarity index 100% rename from dts/arm/rpi_pico/rpi_pico_common.dtsi rename to dts/arm/raspberrypi/rpi_pico/rpi_pico_common.dtsi From b87c8a266604d1bfb46dfd95e767a5bff6aa6764 Mon Sep 17 00:00:00 2001 From: Andrew Featherstone Date: Tue, 27 Aug 2024 10:22:11 +0100 Subject: [PATCH 06/25] dts: arm: rp2040: Improve naming of included files Rename rpi_pico_common.dtsi to rp2040_reset.h . This is more consistent with the wider Zephyr source tree, and is foundation work ahead of introducing the RP2350 SoC. Signed-off-by: Andrew Featherstone --- dts/arm/raspberrypi/rpi_pico/rp2040.dtsi | 5 ++- .../raspberrypi/rpi_pico/rpi_pico_common.dtsi | 35 ------------------ .../zephyr/dt-bindings/reset/rp2040_reset.h | 36 +++++++++++++++++++ 3 files changed, 40 insertions(+), 36 deletions(-) delete mode 100644 dts/arm/raspberrypi/rpi_pico/rpi_pico_common.dtsi create mode 100644 include/zephyr/dt-bindings/reset/rp2040_reset.h diff --git a/dts/arm/raspberrypi/rpi_pico/rp2040.dtsi b/dts/arm/raspberrypi/rpi_pico/rp2040.dtsi index 1709d01c970d..45d5dfa71837 100644 --- a/dts/arm/raspberrypi/rpi_pico/rp2040.dtsi +++ b/dts/arm/raspberrypi/rpi_pico/rp2040.dtsi @@ -10,9 +10,12 @@ #include #include #include +#include #include -#include "rpi_pico_common.dtsi" +#ifndef RPI_PICO_DEFAULT_IRQ_PRIORITY +#define RPI_PICO_DEFAULT_IRQ_PRIORITY 3 +#endif / { aliases { diff --git a/dts/arm/raspberrypi/rpi_pico/rpi_pico_common.dtsi b/dts/arm/raspberrypi/rpi_pico/rpi_pico_common.dtsi deleted file mode 100644 index 58e7fff37201..000000000000 --- a/dts/arm/raspberrypi/rpi_pico/rpi_pico_common.dtsi +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Copyright (c) 2021 Yonatan Schachter - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef RPI_PICO_DEFAULT_IRQ_PRIORITY -#define RPI_PICO_DEFAULT_IRQ_PRIORITY 3 -#endif - -#define RPI_PICO_RESETS_RESET_ADC 0 -#define RPI_PICO_RESETS_RESET_BUSCTRL 1 -#define RPI_PICO_RESETS_RESET_DMA 2 -#define RPI_PICO_RESETS_RESET_I2C0 3 -#define RPI_PICO_RESETS_RESET_I2C1 4 -#define RPI_PICO_RESETS_RESET_IO_BANK0 5 -#define RPI_PICO_RESETS_RESET_IO_QSPI 6 -#define RPI_PICO_RESETS_RESET_JTAG 7 -#define RPI_PICO_RESETS_RESET_PADS_BANK0 8 -#define RPI_PICO_RESETS_RESET_PADS_QSPI 9 -#define RPI_PICO_RESETS_RESET_PIO0 10 -#define RPI_PICO_RESETS_RESET_PIO1 11 -#define RPI_PICO_RESETS_RESET_PLL_SYS 12 -#define RPI_PICO_RESETS_RESET_PLL_USB 13 -#define RPI_PICO_RESETS_RESET_PWM 14 -#define RPI_PICO_RESETS_RESET_RTC 15 -#define RPI_PICO_RESETS_RESET_SPI0 16 -#define RPI_PICO_RESETS_RESET_SPI1 17 -#define RPI_PICO_RESETS_RESET_SYSCFG 18 -#define RPI_PICO_RESETS_RESET_SYSINFO 19 -#define RPI_PICO_RESETS_RESET_TBMAN 20 -#define RPI_PICO_RESETS_RESET_TIMER 21 -#define RPI_PICO_RESETS_RESET_UART0 22 -#define RPI_PICO_RESETS_RESET_UART1 23 -#define RPI_PICO_RESETS_RESET_USBCTRL 24 diff --git a/include/zephyr/dt-bindings/reset/rp2040_reset.h b/include/zephyr/dt-bindings/reset/rp2040_reset.h new file mode 100644 index 000000000000..eeb253c38394 --- /dev/null +++ b/include/zephyr/dt-bindings/reset/rp2040_reset.h @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2021 Yonatan Schachter + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_RP2040_RESET_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_RP2040_RESET_H_ + +#define RPI_PICO_RESETS_RESET_ADC 0 +#define RPI_PICO_RESETS_RESET_BUSCTRL 1 +#define RPI_PICO_RESETS_RESET_DMA 2 +#define RPI_PICO_RESETS_RESET_I2C0 3 +#define RPI_PICO_RESETS_RESET_I2C1 4 +#define RPI_PICO_RESETS_RESET_IO_BANK0 5 +#define RPI_PICO_RESETS_RESET_IO_QSPI 6 +#define RPI_PICO_RESETS_RESET_JTAG 7 +#define RPI_PICO_RESETS_RESET_PADS_BANK0 8 +#define RPI_PICO_RESETS_RESET_PADS_QSPI 9 +#define RPI_PICO_RESETS_RESET_PIO0 10 +#define RPI_PICO_RESETS_RESET_PIO1 11 +#define RPI_PICO_RESETS_RESET_PLL_SYS 12 +#define RPI_PICO_RESETS_RESET_PLL_USB 13 +#define RPI_PICO_RESETS_RESET_PWM 14 +#define RPI_PICO_RESETS_RESET_RTC 15 +#define RPI_PICO_RESETS_RESET_SPI0 16 +#define RPI_PICO_RESETS_RESET_SPI1 17 +#define RPI_PICO_RESETS_RESET_SYSCFG 18 +#define RPI_PICO_RESETS_RESET_SYSINFO 19 +#define RPI_PICO_RESETS_RESET_TBMAN 20 +#define RPI_PICO_RESETS_RESET_TIMER 21 +#define RPI_PICO_RESETS_RESET_UART0 22 +#define RPI_PICO_RESETS_RESET_UART1 23 +#define RPI_PICO_RESETS_RESET_USBCTRL 24 + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_RESET_RP2040_RESET_H_ */ From c0fe9de050066f51a019b39e977862af41570736 Mon Sep 17 00:00:00 2001 From: Andrew Featherstone Date: Thu, 29 Aug 2024 21:25:19 +0100 Subject: [PATCH 07/25] drivers: clock_control: rpi_pico: Correct bitfields during init RESETS_RESET_PLL_USB_BITS was logically or'd twice and 'unreset'ting PWM doesn't seem to be required, based on the contents of the SDK. Signed-off-by: Andrew Featherstone --- drivers/clock_control/clock_control_rpi_pico.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/clock_control/clock_control_rpi_pico.c b/drivers/clock_control/clock_control_rpi_pico.c index e7f058ee32b5..130d785fed56 100644 --- a/drivers/clock_control/clock_control_rpi_pico.c +++ b/drivers/clock_control/clock_control_rpi_pico.c @@ -608,14 +608,13 @@ static int clock_control_rpi_pico_init(const struct device *dev) /* Reset all function before clock configuring */ reset_block(~(RESETS_RESET_IO_QSPI_BITS | RESETS_RESET_PADS_QSPI_BITS | RESETS_RESET_PLL_USB_BITS | RESETS_RESET_USBCTRL_BITS | - RESETS_RESET_PLL_USB_BITS | RESETS_RESET_SYSCFG_BITS | - RESETS_RESET_PLL_SYS_BITS)); + RESETS_RESET_SYSCFG_BITS | RESETS_RESET_PLL_SYS_BITS)); unreset_block_wait(RESETS_RESET_BITS & ~(RESETS_RESET_ADC_BITS | RESETS_RESET_RTC_BITS | RESETS_RESET_SPI0_BITS | RESETS_RESET_SPI1_BITS | RESETS_RESET_UART0_BITS | RESETS_RESET_UART1_BITS | - RESETS_RESET_USBCTRL_BITS | RESETS_RESET_PWM_BITS)); + RESETS_RESET_USBCTRL_BITS)); /* Start tick in watchdog */ watchdog_hw->tick = ((CLOCK_FREQ_xosc/1000000) | WATCHDOG_TICK_ENABLE_BITS); From 6582d2245224e87c09a5c6757dfcf9cf617ca576 Mon Sep 17 00:00:00 2001 From: Andrew Featherstone Date: Fri, 27 Sep 2024 12:51:59 +0100 Subject: [PATCH 08/25] drivers: clock_control: rpi_pico: Make pinctrl-0 optional No in-tree board uses this driver's pinctrl functionality, and every RP2040-based board was configuring this to be an empty node in the device tree, so remove them. Signed-off-by: Andrew Featherstone --- boards/adafruit/kb2040/adafruit_kb2040-pinctrl.dtsi | 3 --- boards/adafruit/kb2040/adafruit_kb2040.dts | 5 ----- .../adafruit/qt_py_rp2040/adafruit_qt_py_rp2040-pinctrl.dtsi | 3 --- boards/adafruit/qt_py_rp2040/adafruit_qt_py_rp2040.dts | 5 ----- boards/raspberrypi/rpi_pico/rpi_pico-common.dtsi | 5 ----- boards/raspberrypi/rpi_pico/rpi_pico-pinctrl.dtsi | 2 -- boards/seeed/xiao_rp2040/xiao_rp2040-pinctrl.dtsi | 3 --- boards/seeed/xiao_rp2040/xiao_rp2040.dts | 5 ----- .../pro_micro_rp2040/sparkfun_pro_micro_rp2040-pinctrl.dtsi | 3 --- .../sparkfun/pro_micro_rp2040/sparkfun_pro_micro_rp2040.dts | 5 ----- boards/wiznet/w5500_evb_pico/w5500_evb_pico-pinctrl.dtsi | 2 -- boards/wiznet/w5500_evb_pico/w5500_evb_pico.dts | 5 ----- drivers/clock_control/clock_control_rpi_pico.c | 2 +- 13 files changed, 1 insertion(+), 47 deletions(-) diff --git a/boards/adafruit/kb2040/adafruit_kb2040-pinctrl.dtsi b/boards/adafruit/kb2040/adafruit_kb2040-pinctrl.dtsi index cf1289acedc3..79681bb8ad34 100644 --- a/boards/adafruit/kb2040/adafruit_kb2040-pinctrl.dtsi +++ b/boards/adafruit/kb2040/adafruit_kb2040-pinctrl.dtsi @@ -48,9 +48,6 @@ }; }; - clocks_default: clocks_default { - }; - ws2812_pio0_default: ws2812_pio0_default { ws2812 { pinmux = ; diff --git a/boards/adafruit/kb2040/adafruit_kb2040.dts b/boards/adafruit/kb2040/adafruit_kb2040.dts index b42b196b1738..c79794217b54 100644 --- a/boards/adafruit/kb2040/adafruit_kb2040.dts +++ b/boards/adafruit/kb2040/adafruit_kb2040.dts @@ -56,11 +56,6 @@ }; }; -&clocks { - pinctrl-0 = <&clocks_default>; - pinctrl-names = "default"; -}; - &uart0 { current-speed = <115200>; status = "okay"; diff --git a/boards/adafruit/qt_py_rp2040/adafruit_qt_py_rp2040-pinctrl.dtsi b/boards/adafruit/qt_py_rp2040/adafruit_qt_py_rp2040-pinctrl.dtsi index d2e84ae41f86..561db005e65c 100644 --- a/boards/adafruit/qt_py_rp2040/adafruit_qt_py_rp2040-pinctrl.dtsi +++ b/boards/adafruit/qt_py_rp2040/adafruit_qt_py_rp2040-pinctrl.dtsi @@ -59,9 +59,6 @@ }; }; - clocks_default: clocks_default { - }; - ws2812_pio1_default: ws2812_pio1_default { ws2812 { pinmux = ; diff --git a/boards/adafruit/qt_py_rp2040/adafruit_qt_py_rp2040.dts b/boards/adafruit/qt_py_rp2040/adafruit_qt_py_rp2040.dts index 088325845c4f..94fca20837c2 100644 --- a/boards/adafruit/qt_py_rp2040/adafruit_qt_py_rp2040.dts +++ b/boards/adafruit/qt_py_rp2040/adafruit_qt_py_rp2040.dts @@ -56,11 +56,6 @@ }; }; -&clocks { - pinctrl-0 = <&clocks_default>; - pinctrl-names = "default"; -}; - &uart1 { current-speed = <115200>; status = "okay"; diff --git a/boards/raspberrypi/rpi_pico/rpi_pico-common.dtsi b/boards/raspberrypi/rpi_pico/rpi_pico-common.dtsi index f54b444bebda..c7dbc3f5aac8 100644 --- a/boards/raspberrypi/rpi_pico/rpi_pico-common.dtsi +++ b/boards/raspberrypi/rpi_pico/rpi_pico-common.dtsi @@ -89,11 +89,6 @@ }; }; -&clocks { - pinctrl-0 = <&clocks_default>; - pinctrl-names = "default"; -}; - &uart0 { current-speed = <115200>; status = "okay"; diff --git a/boards/raspberrypi/rpi_pico/rpi_pico-pinctrl.dtsi b/boards/raspberrypi/rpi_pico/rpi_pico-pinctrl.dtsi index 761354420c61..443b68953bbe 100644 --- a/boards/raspberrypi/rpi_pico/rpi_pico-pinctrl.dtsi +++ b/boards/raspberrypi/rpi_pico/rpi_pico-pinctrl.dtsi @@ -55,6 +55,4 @@ }; }; - clocks_default: clocks_default { - }; }; diff --git a/boards/seeed/xiao_rp2040/xiao_rp2040-pinctrl.dtsi b/boards/seeed/xiao_rp2040/xiao_rp2040-pinctrl.dtsi index 0e235884bf22..eb72fe503c00 100644 --- a/boards/seeed/xiao_rp2040/xiao_rp2040-pinctrl.dtsi +++ b/boards/seeed/xiao_rp2040/xiao_rp2040-pinctrl.dtsi @@ -57,9 +57,6 @@ }; }; - clocks_default: clocks_default { - }; - ws2812_pio0_default: ws2812_pio0_default { ws2812 { pinmux = ; diff --git a/boards/seeed/xiao_rp2040/xiao_rp2040.dts b/boards/seeed/xiao_rp2040/xiao_rp2040.dts index 61c917be38ac..728af5e28b4f 100644 --- a/boards/seeed/xiao_rp2040/xiao_rp2040.dts +++ b/boards/seeed/xiao_rp2040/xiao_rp2040.dts @@ -86,11 +86,6 @@ }; }; -&clocks { - pinctrl-0 = <&clocks_default>; - pinctrl-names = "default"; -}; - &timer { status = "okay"; }; diff --git a/boards/sparkfun/pro_micro_rp2040/sparkfun_pro_micro_rp2040-pinctrl.dtsi b/boards/sparkfun/pro_micro_rp2040/sparkfun_pro_micro_rp2040-pinctrl.dtsi index 5b9c353f802f..b2386014d6f7 100644 --- a/boards/sparkfun/pro_micro_rp2040/sparkfun_pro_micro_rp2040-pinctrl.dtsi +++ b/boards/sparkfun/pro_micro_rp2040/sparkfun_pro_micro_rp2040-pinctrl.dtsi @@ -47,9 +47,6 @@ }; }; - clocks_default: clocks_default { - }; - ws2812_pio0_default: ws2812_pio_default { ws2812 { pinmux = ; diff --git a/boards/sparkfun/pro_micro_rp2040/sparkfun_pro_micro_rp2040.dts b/boards/sparkfun/pro_micro_rp2040/sparkfun_pro_micro_rp2040.dts index 8c4e5acaf2cb..999da0560953 100644 --- a/boards/sparkfun/pro_micro_rp2040/sparkfun_pro_micro_rp2040.dts +++ b/boards/sparkfun/pro_micro_rp2040/sparkfun_pro_micro_rp2040.dts @@ -58,11 +58,6 @@ }; }; -&clocks { - pinctrl-0 = <&clocks_default>; - pinctrl-names = "default"; -}; - &uart0 { current-speed = <115200>; status = "okay"; diff --git a/boards/wiznet/w5500_evb_pico/w5500_evb_pico-pinctrl.dtsi b/boards/wiznet/w5500_evb_pico/w5500_evb_pico-pinctrl.dtsi index 761354420c61..443b68953bbe 100644 --- a/boards/wiznet/w5500_evb_pico/w5500_evb_pico-pinctrl.dtsi +++ b/boards/wiznet/w5500_evb_pico/w5500_evb_pico-pinctrl.dtsi @@ -55,6 +55,4 @@ }; }; - clocks_default: clocks_default { - }; }; diff --git a/boards/wiznet/w5500_evb_pico/w5500_evb_pico.dts b/boards/wiznet/w5500_evb_pico/w5500_evb_pico.dts index 5f5cf14ccedf..3f853ce06051 100644 --- a/boards/wiznet/w5500_evb_pico/w5500_evb_pico.dts +++ b/boards/wiznet/w5500_evb_pico/w5500_evb_pico.dts @@ -112,11 +112,6 @@ }; }; -&clocks { - pinctrl-0 = <&clocks_default>; - pinctrl-names = "default"; -}; - &uart0 { current-speed = <115200>; status = "okay"; diff --git a/drivers/clock_control/clock_control_rpi_pico.c b/drivers/clock_control/clock_control_rpi_pico.c index 130d785fed56..e4c3afb46820 100644 --- a/drivers/clock_control/clock_control_rpi_pico.c +++ b/drivers/clock_control/clock_control_rpi_pico.c @@ -713,7 +713,7 @@ static int clock_control_rpi_pico_init(const struct device *dev) } ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT); - if (ret < 0) { + if (ret < 0 && ret != -ENOENT) { return ret; } From 7b01d18dcd4b327868bd48fe7fa888597f07a8b3 Mon Sep 17 00:00:00 2001 From: Andrew Featherstone Date: Wed, 21 Aug 2024 15:37:56 +0100 Subject: [PATCH 09/25] soc: rp2350: Add initial support for the Raspberry Pi RP2350 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit RP2350 is Raspberry Pi's newest SoC. From the datasheet: "RP2350 is a new family of microcontrollers from Raspberry Pi that offers significant enhancements over RP2040. Key features include: • Dual Cortex-M33 or Hazard3 processors at 150 MHz • 520 kB on-chip SRAM, in 10 independent banks • 8 kB of one-time-programmable storage (OTP) • Up to 16 MB of external QSPI flash/PSRAM via dedicated QSPI bus ... " This commit introduces some changes to support the existing RP2040 and what is describe by Raspberry Pi as the "RP2350 family". Currently there are 4 published products in the family: RP2350A, RP2350B, RP2354A, and RP2354A. Within Zephyr's taxonomy, split the configuration as follows: Family: Raspberry Pi Pico. This contains all RP2XXX SoCs, SoC Series: RP2040 and RP2350. SoC: RP2040 and, for now, just the RP2350A, which is present on the Pico 2, where the A suffix indicates QFN-60 package type. This structure is reflected in `soc/raspberrypi/soc.yml`, and somewhat assumes that there won't be a RP2050, for example, as a RP2040 with more RAM. This is foundation work ahead of introducing support for Raspberry Pi's Pico 2 board, which is fitted with a RP2350A and 4MB of flash. Signed-off-by: Andrew Featherstone --- Kconfig.zephyr | 2 +- drivers/hwinfo/Kconfig | 2 +- dts/arm/raspberrypi/rpi_pico/rp2350.dtsi | 402 ++++++++++++++++++ dts/arm/raspberrypi/rpi_pico/rp2350a.dtsi | 9 + .../dt-bindings/clock/rpi_pico_rp2350_clock.h | 15 + .../zephyr/dt-bindings/reset/rp2350_reset.h | 40 ++ modules/hal_rpi_pico/CMakeLists.txt | 25 +- soc/raspberrypi/Kconfig.soc | 12 - soc/raspberrypi/{ => rpi_pico}/CMakeLists.txt | 1 + soc/raspberrypi/{ => rpi_pico}/Kconfig | 0 .../{ => rpi_pico}/Kconfig.defconfig | 0 soc/raspberrypi/rpi_pico/Kconfig.soc | 25 ++ .../rpi_pico/common/CMakeLists.txt | 8 + .../{rp2xxx => rpi_pico/common}/pinctrl_soc.h | 0 .../{rp2xxx => rpi_pico/common}/soc.c | 13 +- .../{rp2xxx => rpi_pico/common}/soc.h | 6 +- .../rpi_pico/rp2040/CMakeLists.txt | 6 + .../{rp2xxx => rpi_pico/rp2040}/Kconfig | 8 +- .../rp2040}/Kconfig.defconfig | 8 +- .../rp2040}/Kconfig.defconfig.rp2040 | 0 .../{rp2xxx => rpi_pico/rp2040}/Kconfig.soc | 11 +- .../{rp2xxx => rpi_pico/rp2040}/linker.ld | 0 .../rp2350}/CMakeLists.txt | 0 soc/raspberrypi/rpi_pico/rp2350/Kconfig | 26 ++ .../rpi_pico/rp2350/Kconfig.defconfig | 11 + soc/raspberrypi/rpi_pico/rp2350/Kconfig.soc | 12 + soc/raspberrypi/rpi_pico/rp2350/linker.ld | 27 ++ soc/raspberrypi/rpi_pico/rp2350/soc.c | 24 ++ soc/raspberrypi/{ => rpi_pico}/soc.yml | 5 +- 29 files changed, 649 insertions(+), 49 deletions(-) create mode 100644 dts/arm/raspberrypi/rpi_pico/rp2350.dtsi create mode 100644 dts/arm/raspberrypi/rpi_pico/rp2350a.dtsi create mode 100644 include/zephyr/dt-bindings/clock/rpi_pico_rp2350_clock.h create mode 100644 include/zephyr/dt-bindings/reset/rp2350_reset.h delete mode 100644 soc/raspberrypi/Kconfig.soc rename soc/raspberrypi/{ => rpi_pico}/CMakeLists.txt (73%) rename soc/raspberrypi/{ => rpi_pico}/Kconfig (100%) rename soc/raspberrypi/{ => rpi_pico}/Kconfig.defconfig (100%) create mode 100644 soc/raspberrypi/rpi_pico/Kconfig.soc create mode 100644 soc/raspberrypi/rpi_pico/common/CMakeLists.txt rename soc/raspberrypi/{rp2xxx => rpi_pico/common}/pinctrl_soc.h (100%) rename soc/raspberrypi/{rp2xxx => rpi_pico/common}/soc.c (71%) rename soc/raspberrypi/{rp2xxx => rpi_pico/common}/soc.h (71%) create mode 100644 soc/raspberrypi/rpi_pico/rp2040/CMakeLists.txt rename soc/raspberrypi/{rp2xxx => rpi_pico/rp2040}/Kconfig (92%) rename soc/raspberrypi/{rp2xxx => rpi_pico/rp2040}/Kconfig.defconfig (61%) rename soc/raspberrypi/{rp2xxx => rpi_pico/rp2040}/Kconfig.defconfig.rp2040 (100%) rename soc/raspberrypi/{rp2xxx => rpi_pico/rp2040}/Kconfig.soc (52%) rename soc/raspberrypi/{rp2xxx => rpi_pico/rp2040}/linker.ld (100%) rename soc/raspberrypi/{rp2xxx => rpi_pico/rp2350}/CMakeLists.txt (100%) create mode 100644 soc/raspberrypi/rpi_pico/rp2350/Kconfig create mode 100644 soc/raspberrypi/rpi_pico/rp2350/Kconfig.defconfig create mode 100644 soc/raspberrypi/rpi_pico/rp2350/Kconfig.soc create mode 100644 soc/raspberrypi/rpi_pico/rp2350/linker.ld create mode 100644 soc/raspberrypi/rpi_pico/rp2350/soc.c rename soc/raspberrypi/{ => rpi_pico}/soc.yml (50%) diff --git a/Kconfig.zephyr b/Kconfig.zephyr index 425d79f4e74e..c45329048812 100644 --- a/Kconfig.zephyr +++ b/Kconfig.zephyr @@ -766,7 +766,7 @@ config BUILD_OUTPUT_UF2_FAMILY_ID default "0xada52840" if SOC_NRF52840_QIAA default "0x4fb2d5bd" if SOC_SERIES_IMXRT10XX || SOC_SERIES_IMXRT11XX default "0x2abc77ec" if SOC_SERIES_LPC55XXX - default "0xe48bff56" if SOC_SERIES_RP2XXX + default "0xe48bff56" if SOC_SERIES_RP2040 default "0x68ed2b88" if SOC_SERIES_SAMD21 default "0x55114460" if SOC_SERIES_SAMD51 default "0x647824b6" if SOC_SERIES_STM32F0X diff --git a/drivers/hwinfo/Kconfig b/drivers/hwinfo/Kconfig index 2e2707406192..04cec3c6a42c 100644 --- a/drivers/hwinfo/Kconfig +++ b/drivers/hwinfo/Kconfig @@ -130,7 +130,7 @@ config HWINFO_IMXRT config HWINFO_RPI_PICO bool "Raspberry Pi Pico hwinfo driver" default y - depends on SOC_SERIES_RP2XXX + depends on SOC_FAMILY_RPI_PICO select HWINFO_HAS_DRIVER select PICOSDK_USE_FLASH help diff --git a/dts/arm/raspberrypi/rpi_pico/rp2350.dtsi b/dts/arm/raspberrypi/rpi_pico/rp2350.dtsi new file mode 100644 index 000000000000..b5a066f37158 --- /dev/null +++ b/dts/arm/raspberrypi/rpi_pico/rp2350.dtsi @@ -0,0 +1,402 @@ +/* + * Copyright (c) 2024 Andrew Featherstone + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#ifndef RPI_PICO_DEFAULT_IRQ_PRIORITY +#define RPI_PICO_DEFAULT_IRQ_PRIORITY 7 +#endif + +/ { + aliases { + die-temp0 = &die_temp; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-m33"; + reg = <0>; + }; + + cpu1: cpu@1 { + compatible = "arm,cortex-m33"; + reg = <1>; + }; + }; + + clocks { + clk_gpout0: clk-gpout0 { + compatible = "raspberrypi,pico-clock"; + clocks = <&pll_sys>; + clock-names = "pll_sys"; + clock-frequency = <150000000>; + #clock-cells = <0>; + #address-cells = <0>; + }; + + clk_gpout1: clk-gpout1 { + compatible = "raspberrypi,pico-clock"; + clocks = <&pll_sys>; + clock-names = "pll_sys"; + clock-frequency = <150000000>; + #clock-cells = <0>; + }; + + clk_gpout2: clk-gpout2 { + compatible = "raspberrypi,pico-clock"; + clocks = <&pll_sys>; + clock-names = "pll_sys"; + clock-frequency = <150000000>; + #clock-cells = <0>; + }; + + clk_gpout3: clk-gpout3 { + compatible = "raspberrypi,pico-clock"; + clocks = <&pll_sys>; + clock-names = "pll_sys"; + clock-frequency = <150000000>; + #clock-cells = <0>; + }; + + clk_hstx: clk-hstx { + compatible = "raspberrypi,pico-clock"; + clocks = <&pll_sys>; + clock-names = "pll_sys"; + clock-frequency = <150000000>; + #clock-cells = <0>; + }; + + clk_ref: clk-ref { + compatible = "raspberrypi,pico-clock"; + clocks = <&xosc>; + clock-names = "xosc"; + clock-frequency = <12000000>; + #clock-cells = <0>; + }; + + clk_sys: clk-sys { + compatible = "raspberrypi,pico-clock"; + clocks = <&pll_sys>; + clock-names = "pll_sys"; + clock-frequency = <150000000>; + #clock-cells = <0>; + }; + + clk_usb: clk-usb { + compatible = "raspberrypi,pico-clock"; + clocks = <&pll_usb>; + clock-names = "pll_usb"; + clock-frequency = <48000000>; + #clock-cells = <0>; + }; + + clk_adc: clk-adc { + compatible = "raspberrypi,pico-clock"; + clocks = <&pll_usb>; + clock-names = "pll_usb"; + clock-frequency = <48000000>; + #clock-cells = <0>; + }; + + clk_peri: clk-peri { + compatible = "raspberrypi,pico-clock"; + clocks = <&clk_sys>; + clock-names = "clk_sys"; + clock-frequency = <150000000>; + #clock-cells = <0>; + }; + + pll_sys: pll-sys { + compatible = "raspberrypi,pico-pll"; + clocks = <&xosc>; + clock-names = "xosc"; + clock-div= <1>; + fb-div= <125>; + post-div1 = <5>; + post-div2 = <2>; + #clock-cells = <0>; + }; + + pll_usb: pll-usb { + compatible = "raspberrypi,pico-pll"; + clocks = <&xosc>; + clock-names = "xosc"; + clock-div= <1>; + fb-div = <100>; + post-div1 = <5>; + post-div2 = <5>; + #clock-cells = <0>; + }; + + rosc: rosc { + compatible = "raspberrypi,pico-rosc"; + clock-frequency = <6500000>; + range = ; + stage-drive-strength = <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>; + clock-div = <16>; + phase = <0>; + #clock-cells = <0>; + }; + + rosc_ph: rosc-ph { + compatible = "raspberrypi,pico-clock"; + clock-frequency = <6500000>; + clocks = <&rosc>; + clock-names = "rosc"; + #clock-cells = <0>; + }; + + xosc: xosc { + compatible = "raspberrypi,pico-clock"; + clock-frequency = <12000000>; + #clock-cells = <0>; + }; + + gpin0: gpin0 { + compatible = "raspberrypi,pico-clock"; + status = "disabled"; + clock-frequency = <0>; + #clock-cells = <0>; + }; + + gpin1: gpin1 { + compatible = "raspberrypi,pico-clock"; + status = "disabled"; + clock-frequency = <0>; + #clock-cells = <0>; + }; + }; + + soc { + compatible = "raspberrypi,rp2350", "simple-bus"; + + sram0: memory@20000000 { + compatible = "mmio-sram"; + reg = <0x20000000 DT_SIZE_K(520)>; + }; + + qmi: flash-controller@400d0000 { + compatible = "raspberrypi,pico-flash-controller"; + reg = <0x400d0000 0xfc>; + + #address-cells = <1>; + #size-cells = <1>; + + flash0: flash@10000000 { + compatible = "soc-nv-flash"; + write-block-size = <1>; + erase-block-size = ; + }; + status = "disabled"; + }; + + reset: reset-controller@40020000 { + compatible = "raspberrypi,pico-reset"; + reg = <0x40020000 DT_SIZE_K(4)>; + reg-width = <4>; + active-low = <0>; + #reset-cells = <1>; + }; + + clocks: clock-controller@40010000 { + compatible = "raspberrypi,pico-clock-controller"; + reg = <0x40010000 DT_SIZE_K(4) + 0x40048000 DT_SIZE_K(4) + 0x40050000 DT_SIZE_K(4) + 0x40058000 DT_SIZE_K(4) + 0x400e8000 DT_SIZE_K(4)>; + reg-names = "clocks", "xosc", "pll_sys", "pll_usb", "rosc"; + #clock-cells = <1>; + status = "okay"; + clocks = <&clk_gpout0>, <&clk_gpout1>, <&clk_gpout2>, <&clk_gpout3>, + <&clk_hstx>, <&clk_ref>, <&clk_sys>, <&clk_peri>, + <&clk_usb>, <&clk_adc>, + <&pll_sys>, <&pll_usb>, <&xosc>, <&rosc>, <&rosc_ph>, + <&gpin0>, <&gpin1>; + clock-names = "clk_gpout0", "clk_gpout1", "clk_gpout2", "clk_gpout3", + "clk_hstx", "clk_ref", "clk_sys", "clk_peri", + "clk_usb", "clk_adc", + "pll_sys", "pll_usb", "xosc", "rosc", "rosc_ph", + "gpin0", "gpin1"; + }; + + gpio0: gpio@40028000 { + compatible = "raspberrypi,pico-gpio"; + reg = <0x40028000 DT_SIZE_K(4)>; + interrupts = <21 RPI_PICO_DEFAULT_IRQ_PRIORITY>; + gpio-controller; + #gpio-cells = <2>; + status = "disabled"; + }; + + uart0: uart@40070000 { + compatible = "raspberrypi,pico-uart", "arm,pl011"; + reg = <0x40070000 DT_SIZE_K(4)>; + clocks = <&clocks RPI_PICO_CLKID_CLK_PERI>; + resets = <&reset RPI_PICO_RESETS_RESET_UART0>; + interrupts = <33 RPI_PICO_DEFAULT_IRQ_PRIORITY>; + interrupt-names = "uart0"; + status = "disabled"; + }; + + uart1: uart@40078000 { + compatible = "raspberrypi,pico-uart", "arm,pl011"; + reg = <0x40078000 DT_SIZE_K(4)>; + clocks = <&clocks RPI_PICO_CLKID_CLK_PERI>; + resets = <&reset RPI_PICO_RESETS_RESET_UART1>; + interrupts = <34 RPI_PICO_DEFAULT_IRQ_PRIORITY>; + interrupt-names = "uart1"; + status = "disabled"; + }; + + spi0: spi@40080000 { + compatible = "raspberrypi,pico-spi", "arm,pl022"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x40080000 DT_SIZE_K(4)>; + clocks = <&clocks RPI_PICO_CLKID_CLK_PERI>; + resets = <&reset RPI_PICO_RESETS_RESET_SPI0>; + interrupts = <31 RPI_PICO_DEFAULT_IRQ_PRIORITY>; + interrupt-names = "spi0"; + status = "disabled"; + }; + + spi1: spi@40088000 { + compatible = "raspberrypi,pico-spi", "arm,pl022"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x40088000 DT_SIZE_K(4)>; + resets = <&reset RPI_PICO_RESETS_RESET_SPI1>; + clocks = <&clocks RPI_PICO_CLKID_CLK_PERI>; + interrupts = <32 RPI_PICO_DEFAULT_IRQ_PRIORITY>; + interrupt-names = "spi1"; + status = "disabled"; + }; + + i2c0: i2c@40090000 { + compatible = "raspberrypi,pico-i2c", "snps,designware-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x40090000 DT_SIZE_K(4)>; + resets = <&reset RPI_PICO_RESETS_RESET_I2C0>; + clocks = <&clocks RPI_PICO_CLKID_CLK_SYS>; + interrupts = <36 RPI_PICO_DEFAULT_IRQ_PRIORITY>; + interrupt-names = "i2c0"; + status = "disabled"; + }; + + i2c1: i2c@40098000 { + compatible = "raspberrypi,pico-i2c", "snps,designware-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x40098000 DT_SIZE_K(4)>; + resets = <&reset RPI_PICO_RESETS_RESET_I2C1>; + clocks = <&clocks RPI_PICO_CLKID_CLK_SYS>; + interrupts = <37 RPI_PICO_DEFAULT_IRQ_PRIORITY>; + interrupt-names = "i2c1"; + status = "disabled"; + }; + + adc: adc@400a0000 { + compatible = "raspberrypi,pico-adc"; + reg = <0x400a0000 DT_SIZE_K(4)>; + resets = <&reset RPI_PICO_RESETS_RESET_ADC>; + clocks = <&clocks RPI_PICO_CLKID_CLK_ADC>; + interrupts = <35 RPI_PICO_DEFAULT_IRQ_PRIORITY>; + interrupt-names = "adc0"; + status = "disabled"; + #io-channel-cells = <1>; + }; + + pwm: pwm@400a8000 { + compatible = "raspberrypi,pico-pwm"; + reg = <0x400a8000 DT_SIZE_K(4)>; + resets = <&reset RPI_PICO_RESETS_RESET_PWM>; + clocks = <&clocks RPI_PICO_CLKID_CLK_SYS>; + interrupts = <8 RPI_PICO_DEFAULT_IRQ_PRIORITY>, + <9 RPI_PICO_DEFAULT_IRQ_PRIORITY>; + interrupt-names = "PWM_IRQ_WRAP_0", + "PWM_IRQ_WRAP_1"; + status = "disabled"; + #pwm-cells = <3>; + }; + + timer0: timer@400b0000 { + compatible = "raspberrypi,pico-timer"; + reg = <0x400b0000 DT_SIZE_K(4)>; + resets = <&reset RPI_PICO_RESETS_RESET_TIMER0>; + clocks = <&clocks RPI_PICO_CLKID_CLK_REF>; + interrupts = <0 RPI_PICO_DEFAULT_IRQ_PRIORITY>, + <1 RPI_PICO_DEFAULT_IRQ_PRIORITY>, + <2 RPI_PICO_DEFAULT_IRQ_PRIORITY>, + <3 RPI_PICO_DEFAULT_IRQ_PRIORITY>; + interrupt-names = "TIMER0_IRQ_0", + "TIMER0_IRQ_1", + "TIMER0_IRQ_2", + "TIMER0_IRQ_3"; + status = "disabled"; + }; + + timer1: timer@400b8000 { + compatible = "raspberrypi,pico-timer"; + reg = <0x400b8000 DT_SIZE_K(4)>; + resets = <&reset RPI_PICO_RESETS_RESET_TIMER1>; + clocks = <&clocks RPI_PICO_CLKID_CLK_REF>; + interrupts = <4 RPI_PICO_DEFAULT_IRQ_PRIORITY>, + <5 RPI_PICO_DEFAULT_IRQ_PRIORITY>, + <6 RPI_PICO_DEFAULT_IRQ_PRIORITY>, + <7 RPI_PICO_DEFAULT_IRQ_PRIORITY>; + interrupt-names = "TIMER1_IRQ_0", + "TIMER1_IRQ_1", + "TIMER1_IRQ_2", + "TIMER1_IRQ_3"; + status = "disabled"; + }; + + wdt0: watchdog@400d8000 { + compatible = "raspberrypi,pico-watchdog"; + reg = <0x400d8000 DT_SIZE_K(4)>; + clocks = <&clocks RPI_PICO_CLKID_CLK_REF>; + status = "disabled"; + }; + + usbd: usbd@50100000 { + compatible = "raspberrypi,pico-usbd"; + reg = <0x50100000 0x10000>; + resets = <&reset RPI_PICO_RESETS_RESET_USBCTRL>; + clocks = <&clocks RPI_PICO_CLKID_CLK_USB>; + interrupts = <14 RPI_PICO_DEFAULT_IRQ_PRIORITY>; + interrupt-names = "usbctrl"; + num-bidir-endpoints = <16>; + status = "disabled"; + }; + + }; + + pinctrl: pin-controller { + compatible = "raspberrypi,pico-pinctrl"; + status = "okay"; + }; + + die_temp: dietemp { + compatible = "raspberrypi,pico-temp"; + status = "disabled"; + }; +}; + +&nvic { + arm,num-irq-priority-bits = <4>; +}; diff --git a/dts/arm/raspberrypi/rpi_pico/rp2350a.dtsi b/dts/arm/raspberrypi/rpi_pico/rp2350a.dtsi new file mode 100644 index 000000000000..762af8d82c3a --- /dev/null +++ b/dts/arm/raspberrypi/rpi_pico/rp2350a.dtsi @@ -0,0 +1,9 @@ +#include + +&gpio0 { + ngpios = <30>; +}; + +&die_temp { + io-channels = <&adc 4>; +}; diff --git a/include/zephyr/dt-bindings/clock/rpi_pico_rp2350_clock.h b/include/zephyr/dt-bindings/clock/rpi_pico_rp2350_clock.h new file mode 100644 index 000000000000..92066bd1345c --- /dev/null +++ b/include/zephyr/dt-bindings/clock/rpi_pico_rp2350_clock.h @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2024 Andrew Featherstone + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RPI_PICO_CLOCK_RP2350_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RPI_PICO_CLOCK_RP2350_H_ + +#include "rpi_pico_clock_common.h" + +#define RPI_PICO_CLKID_CLK_HSTX 7 +#define RPI_PICO_CLKID_CLK_USB 8 +#define RPI_PICO_CLKID_CLK_ADC 9 + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RPI_PICO_CLOCK_RP2350_H_ */ diff --git a/include/zephyr/dt-bindings/reset/rp2350_reset.h b/include/zephyr/dt-bindings/reset/rp2350_reset.h new file mode 100644 index 000000000000..81fcfa9ff31d --- /dev/null +++ b/include/zephyr/dt-bindings/reset/rp2350_reset.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2024 Andrew Featherstone + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_RP2350_RESET_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_RP2350_RESET_H_ + +#define RPI_PICO_RESETS_RESET_ADC 0 +#define RPI_PICO_RESETS_RESET_BUSCTRL 1 +#define RPI_PICO_RESETS_RESET_DMA 2 +#define RPI_PICO_RESETS_RESET_HSTX 3 +#define RPI_PICO_RESETS_RESET_I2C0 4 +#define RPI_PICO_RESETS_RESET_I2C1 5 +#define RPI_PICO_RESETS_RESET_IO_BANK0 6 +#define RPI_PICO_RESETS_RESET_IO_QSPI 7 +#define RPI_PICO_RESETS_RESET_JTAG 8 +#define RPI_PICO_RESETS_RESET_PADS_BANK0 9 +#define RPI_PICO_RESETS_RESET_PADS_QSPI 10 +#define RPI_PICO_RESETS_RESET_PIO0 11 +#define RPI_PICO_RESETS_RESET_PIO1 12 +#define RPI_PICO_RESETS_RESET_PIO2 13 +#define RPI_PICO_RESETS_RESET_PLL_SYS 14 +#define RPI_PICO_RESETS_RESET_PLL_USB 15 +#define RPI_PICO_RESETS_RESET_PWM 16 +#define RPI_PICO_RESETS_RESET_SHA256 17 +#define RPI_PICO_RESETS_RESET_SPI0 18 +#define RPI_PICO_RESETS_RESET_SPI1 19 +#define RPI_PICO_RESETS_RESET_SYSCFG 20 +#define RPI_PICO_RESETS_RESET_SYSINFO 21 +#define RPI_PICO_RESETS_RESET_TBMAN 22 +#define RPI_PICO_RESETS_RESET_TIMER0 23 +#define RPI_PICO_RESETS_RESET_TIMER1 24 +#define RPI_PICO_RESETS_RESET_TRNG 25 +#define RPI_PICO_RESETS_RESET_UART0 26 +#define RPI_PICO_RESETS_RESET_UART1 27 +#define RPI_PICO_RESETS_RESET_USBCTRL 28 + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_RESET_RP2350_RESET_H_ */ diff --git a/modules/hal_rpi_pico/CMakeLists.txt b/modules/hal_rpi_pico/CMakeLists.txt index c91e64679925..6fa5559afa65 100644 --- a/modules/hal_rpi_pico/CMakeLists.txt +++ b/modules/hal_rpi_pico/CMakeLists.txt @@ -6,9 +6,9 @@ if(CONFIG_HAS_RPI_PICO) zephyr_library() set(rp2_common_dir ${ZEPHYR_HAL_RPI_PICO_MODULE_DIR}/src/rp2_common) - set(rp2040_dir ${ZEPHYR_HAL_RPI_PICO_MODULE_DIR}/src/rp2040) + set(rp2xxx_dir ${ZEPHYR_HAL_RPI_PICO_MODULE_DIR}/src/${CONFIG_SOC_SERIES}) set(common_dir ${ZEPHYR_HAL_RPI_PICO_MODULE_DIR}/src/common) - set(boot_stage_dir ${rp2040_dir}/boot_stage2) + set(boot_stage_dir ${rp2xxx_dir}/boot_stage2) # The Second Stage Bootloader is only linked to the app that resides # at 0x100. Therefore, only if the app's offset is 0x100, the second @@ -46,7 +46,11 @@ if(CONFIG_HAS_RPI_PICO) zephyr_library_sources(${rp2_bootloader_asm}) endif() - zephyr_compile_definitions(PICO_RP2040) + if(CONFIG_SOC_SERIES_RP2040) + zephyr_compile_definitions(PICO_RP2040) + elseif(CONFIG_SOC_SERIES_RP2350) + zephyr_compile_definitions(PICO_RP2350) + endif() # Pico sources and headers necessary for every build. # These contain definitions and implementation used mostly for @@ -57,8 +61,9 @@ if(CONFIG_HAS_RPI_PICO) ${rp2_common_dir}/hardware_pll/pll.c ${rp2_common_dir}/hardware_xosc/xosc.c ${rp2_common_dir}/hardware_watchdog/watchdog.c + ${rp2_common_dir}/hardware_sync_spin_lock/sync_spin_lock.c ${rp2_common_dir}/pico_bootrom/bootrom.c - ${rp2040_dir}/pico_platform/platform.c + ${rp2xxx_dir}/pico_platform/platform.c ) zephyr_include_directories( @@ -81,9 +86,9 @@ if(CONFIG_HAS_RPI_PICO) ${rp2_common_dir}/pico_platform_panic/include ${common_dir}/boot_picoboot_headers/include ${common_dir}/boot_picobin_headers/include - ${rp2040_dir}/hardware_regs/include - ${rp2040_dir}/hardware_structs/include - ${rp2040_dir}/pico_platform/include + ${rp2xxx_dir}/hardware_regs/include + ${rp2xxx_dir}/hardware_structs/include + ${rp2xxx_dir}/pico_platform/include ${CMAKE_CURRENT_LIST_DIR} ) @@ -145,4 +150,10 @@ if(CONFIG_HAS_RPI_PICO) zephyr_include_directories_ifdef(CONFIG_PICOSDK_USE_CLAIM ${common_dir}/hardware_claim/include) + zephyr_library_sources_ifdef(CONFIG_SOC_SERIES_RP2350 + ${rp2_common_dir}/pico_runtime_init/runtime_init.c) + zephyr_include_directories_ifdef(CONFIG_SOC_SERIES_RP2350 + ${rp2_common_dir}/pico_runtime/include + ${rp2_common_dir}/pico_runtime_init/include) + endif() diff --git a/soc/raspberrypi/Kconfig.soc b/soc/raspberrypi/Kconfig.soc deleted file mode 100644 index b0b8b7b761fe..000000000000 --- a/soc/raspberrypi/Kconfig.soc +++ /dev/null @@ -1,12 +0,0 @@ -# Raspberry Pi (RP) MCU line - -# Copyright (c) 2021 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config SOC_FAMILY_RPI_PICO - bool - -config SOC_FAMILY - default "rpi_pico" if SOC_FAMILY_RPI_PICO - -rsource "*/Kconfig.soc" diff --git a/soc/raspberrypi/CMakeLists.txt b/soc/raspberrypi/rpi_pico/CMakeLists.txt similarity index 73% rename from soc/raspberrypi/CMakeLists.txt rename to soc/raspberrypi/rpi_pico/CMakeLists.txt index 226f3bd626f6..c5f97039eb75 100644 --- a/soc/raspberrypi/CMakeLists.txt +++ b/soc/raspberrypi/rpi_pico/CMakeLists.txt @@ -1,3 +1,4 @@ # SPDX-License-Identifier: Apache-2.0 +add_subdirectory(common) add_subdirectory(${SOC_SERIES}) diff --git a/soc/raspberrypi/Kconfig b/soc/raspberrypi/rpi_pico/Kconfig similarity index 100% rename from soc/raspberrypi/Kconfig rename to soc/raspberrypi/rpi_pico/Kconfig diff --git a/soc/raspberrypi/Kconfig.defconfig b/soc/raspberrypi/rpi_pico/Kconfig.defconfig similarity index 100% rename from soc/raspberrypi/Kconfig.defconfig rename to soc/raspberrypi/rpi_pico/Kconfig.defconfig diff --git a/soc/raspberrypi/rpi_pico/Kconfig.soc b/soc/raspberrypi/rpi_pico/Kconfig.soc new file mode 100644 index 000000000000..b452e9d79c78 --- /dev/null +++ b/soc/raspberrypi/rpi_pico/Kconfig.soc @@ -0,0 +1,25 @@ +# Raspberry Pi (RP) MCU line + +# Copyright (c) 2021 Nordic Semiconductor ASA +# Copyright (c) 2024 Andrew Featherstone +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_RPI_PICO + bool + +config SOC_FAMILY + default "rpi_pico" if SOC_FAMILY_RPI_PICO + +config SOC_SERIES + default "rp2040" if SOC_SERIES_RP2040 + default "rp2350" if SOC_SERIES_RP2350 + +config SOC_SERIES_RP2040 + bool + select SOC_FAMILY_RPI_PICO + +config SOC_SERIES_RP2350 + bool + select SOC_FAMILY_RPI_PICO + +rsource "*/Kconfig.soc" diff --git a/soc/raspberrypi/rpi_pico/common/CMakeLists.txt b/soc/raspberrypi/rpi_pico/common/CMakeLists.txt new file mode 100644 index 000000000000..d87ecff49c08 --- /dev/null +++ b/soc/raspberrypi/rpi_pico/common/CMakeLists.txt @@ -0,0 +1,8 @@ +# Copyright (c) 2024 Andrew Featherstone +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) + +zephyr_sources( + soc.c +) diff --git a/soc/raspberrypi/rp2xxx/pinctrl_soc.h b/soc/raspberrypi/rpi_pico/common/pinctrl_soc.h similarity index 100% rename from soc/raspberrypi/rp2xxx/pinctrl_soc.h rename to soc/raspberrypi/rpi_pico/common/pinctrl_soc.h diff --git a/soc/raspberrypi/rp2xxx/soc.c b/soc/raspberrypi/rpi_pico/common/soc.c similarity index 71% rename from soc/raspberrypi/rp2xxx/soc.c rename to soc/raspberrypi/rpi_pico/common/soc.c index 012f5431283b..37e98105fa14 100644 --- a/soc/raspberrypi/rp2xxx/soc.c +++ b/soc/raspberrypi/rpi_pico/common/soc.c @@ -1,28 +1,23 @@ /* * Copyright (c) 2021 Nordic Semiconductor ASA * Copyright (c) 2021 Yonatan Schachter + * Copyright (c) 2024 Andrew Featherstone * * SPDX-License-Identifier: Apache-2.0 */ /** * @file - * @brief System/hardware module for Raspberry Pi RP2040 family processor + * @brief System/hardware module for Raspberry Pi RP2xxx family of processors * * This module provides routines to initialize and support board-level hardware - * for the Raspberry Pi RP2040 family processor. + * for the Raspberry Pi RP2xxx family of processors (RP2040, RP235x). */ #include -#include -#include -#include #include - -#include -#include -#include +#include LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL); diff --git a/soc/raspberrypi/rp2xxx/soc.h b/soc/raspberrypi/rpi_pico/common/soc.h similarity index 71% rename from soc/raspberrypi/rp2xxx/soc.h rename to soc/raspberrypi/rpi_pico/common/soc.h index 0eef4cf92a24..c3d669ec99be 100644 --- a/soc/raspberrypi/rp2xxx/soc.h +++ b/soc/raspberrypi/rpi_pico/common/soc.h @@ -9,9 +9,9 @@ * @file SoC configuration macros for the Raspberry Pi RP2040 family processors */ -#ifndef _RPI_PICO_RP2040_SOC_H_ -#define _RPI_PICO_RP2040_SOC_H_ +#ifndef _RPI_PICO_COMMON_SOC_H_ +#define _RPI_PICO_COMMON_SOC_H_ #include -#endif /* _RPI_PICO_RP2040_SOC_H_ */ +#endif /* _RPI_PICO_COMMON_SOC_H_ */ diff --git a/soc/raspberrypi/rpi_pico/rp2040/CMakeLists.txt b/soc/raspberrypi/rpi_pico/rp2040/CMakeLists.txt new file mode 100644 index 000000000000..4c53cf10d0fd --- /dev/null +++ b/soc/raspberrypi/rpi_pico/rp2040/CMakeLists.txt @@ -0,0 +1,6 @@ +# Copyright (c) 2021 Yonatan Schachter +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/raspberrypi/rp2xxx/Kconfig b/soc/raspberrypi/rpi_pico/rp2040/Kconfig similarity index 92% rename from soc/raspberrypi/rp2xxx/Kconfig rename to soc/raspberrypi/rpi_pico/rp2040/Kconfig index 1abc32af2cee..05f2a3ae49b6 100644 --- a/soc/raspberrypi/rp2xxx/Kconfig +++ b/soc/raspberrypi/rpi_pico/rp2040/Kconfig @@ -4,7 +4,7 @@ # Copyright (c) 2021 Yonatan Schachter # SPDX-License-Identifier: Apache-2.0 -config SOC_SERIES_RP2XXX +config SOC_SERIES_RP2040 select ARM select CPU_CORTEX_M0PLUS select CPU_CORTEX_M_HAS_SYSTICK @@ -14,7 +14,9 @@ config SOC_SERIES_RP2XXX select XIP select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE help - Enable support for Raspberry Pi RP2 MCU series + Enable support for Raspberry Pi RP20 MCU series + +if SOC_SERIES_RP2040 config RP2_REQUIRES_SECOND_STAGE_BOOT bool @@ -51,3 +53,5 @@ config RP2_FLASH_AT25SF128A help Configure RP2 to use a AT25SF128A flash chip, or similar. Should be selected by the board definition, not the user. + +endif diff --git a/soc/raspberrypi/rp2xxx/Kconfig.defconfig b/soc/raspberrypi/rpi_pico/rp2040/Kconfig.defconfig similarity index 61% rename from soc/raspberrypi/rp2xxx/Kconfig.defconfig rename to soc/raspberrypi/rpi_pico/rp2040/Kconfig.defconfig index 82256e806d05..16ac3ebb4f30 100644 --- a/soc/raspberrypi/rp2xxx/Kconfig.defconfig +++ b/soc/raspberrypi/rpi_pico/rp2040/Kconfig.defconfig @@ -1,14 +1,14 @@ -# Raspberry Pi RP2XXX MCU line +# Raspberry Pi RP2040 MCU line # Copyright (c) 2021 Nordic Semiconductor ASA # Copyright (c) 2021 Yonatan Schachter # SPDX-License-Identifier: Apache-2.0 -if SOC_SERIES_RP2XXX +if SOC_SERIES_RP2040 rsource "Kconfig.defconfig.rp2*" config NUM_IRQS - default 26 + default 26 if SOC_SERIES_RP2040 -endif # SOC_SERIES_RP2XXX +endif # SOC_SERIES_RP2040 diff --git a/soc/raspberrypi/rp2xxx/Kconfig.defconfig.rp2040 b/soc/raspberrypi/rpi_pico/rp2040/Kconfig.defconfig.rp2040 similarity index 100% rename from soc/raspberrypi/rp2xxx/Kconfig.defconfig.rp2040 rename to soc/raspberrypi/rpi_pico/rp2040/Kconfig.defconfig.rp2040 diff --git a/soc/raspberrypi/rp2xxx/Kconfig.soc b/soc/raspberrypi/rpi_pico/rp2040/Kconfig.soc similarity index 52% rename from soc/raspberrypi/rp2xxx/Kconfig.soc rename to soc/raspberrypi/rpi_pico/rp2040/Kconfig.soc index 045061697fe3..25f0da8103db 100644 --- a/soc/raspberrypi/rp2xxx/Kconfig.soc +++ b/soc/raspberrypi/rpi_pico/rp2040/Kconfig.soc @@ -1,4 +1,4 @@ -# Raspberry Pi RP2XXX MCU line +# Raspberry Pi RP2040 MCU line # Copyright (c) 2021 Nordic Semiconductor ASA # Copyright (c) 2021 Yonatan Schachter @@ -6,14 +6,7 @@ config SOC_RP2040 bool - select SOC_SERIES_RP2XXX - -config SOC_SERIES_RP2XXX - bool - select SOC_FAMILY_RPI_PICO - -config SOC_SERIES - default "rp2xxx" if SOC_SERIES_RP2XXX + select SOC_SERIES_RP2040 config SOC default "rp2040" if SOC_RP2040 diff --git a/soc/raspberrypi/rp2xxx/linker.ld b/soc/raspberrypi/rpi_pico/rp2040/linker.ld similarity index 100% rename from soc/raspberrypi/rp2xxx/linker.ld rename to soc/raspberrypi/rpi_pico/rp2040/linker.ld diff --git a/soc/raspberrypi/rp2xxx/CMakeLists.txt b/soc/raspberrypi/rpi_pico/rp2350/CMakeLists.txt similarity index 100% rename from soc/raspberrypi/rp2xxx/CMakeLists.txt rename to soc/raspberrypi/rpi_pico/rp2350/CMakeLists.txt diff --git a/soc/raspberrypi/rpi_pico/rp2350/Kconfig b/soc/raspberrypi/rpi_pico/rp2350/Kconfig new file mode 100644 index 000000000000..7175fe02a556 --- /dev/null +++ b/soc/raspberrypi/rpi_pico/rp2350/Kconfig @@ -0,0 +1,26 @@ +# Raspberry Pi RP235XX MCU line + +# Copyright (c) 2024 Andrew Featherstone +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_RP2350 + select ARM + select ARM_TRUSTZONE_M + select CPU_CORTEX_M33 + select CPU_CORTEX_M_HAS_SYSTICK + select CPU_CORTEX_M_HAS_VTOR + select CPU_HAS_ARM_MPU + select CPU_HAS_ARM_SAU + select HAS_RPI_PICO + select XIP + select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE + select SOC_RESET_HOOK + help + Enable support for Raspberry Pi RP23 MCU series + +config RP2_REQUIRES_IMAGE_DEFINITION_BLOCK + bool + default y + help + Include an Image Definition Block (IMAGE_DEF) to enable the bootroom in + RP23XX devices to consider this a valid image in flash. diff --git a/soc/raspberrypi/rpi_pico/rp2350/Kconfig.defconfig b/soc/raspberrypi/rpi_pico/rp2350/Kconfig.defconfig new file mode 100644 index 000000000000..3e59a9b98871 --- /dev/null +++ b/soc/raspberrypi/rpi_pico/rp2350/Kconfig.defconfig @@ -0,0 +1,11 @@ +# Raspberry Pi RP2350 MCU line + +# Copyright (c) 2024 Andrew Featherstone +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_RP2350 + +config NUM_IRQS + default 52 + +endif # SOC_SERIES_RP2350 diff --git a/soc/raspberrypi/rpi_pico/rp2350/Kconfig.soc b/soc/raspberrypi/rpi_pico/rp2350/Kconfig.soc new file mode 100644 index 000000000000..68e2becffc06 --- /dev/null +++ b/soc/raspberrypi/rpi_pico/rp2350/Kconfig.soc @@ -0,0 +1,12 @@ +# Raspberry Pi RP2350 MCU line + +# Copyright (c) 2021 Nordic Semiconductor ASA +# Copyright (c) 2021 Yonatan Schachter +# SPDX-License-Identifier: Apache-2.0 + +config SOC_RP2350A + bool + select SOC_SERIES_RP2350 + +config SOC + default "rp2350a" if SOC_RP2350A diff --git a/soc/raspberrypi/rpi_pico/rp2350/linker.ld b/soc/raspberrypi/rpi_pico/rp2350/linker.ld new file mode 100644 index 000000000000..6368409c9e27 --- /dev/null +++ b/soc/raspberrypi/rpi_pico/rp2350/linker.ld @@ -0,0 +1,27 @@ +/* linker.ld - Linker command/script file */ + +/* + * Copyright (c) 2024 Andrew Featherstone + * + * SPDX-License-Identifier: Apache-2.0 + */ + +MEMORY +{ + IMAGE_DEF_FLASH (r) : ORIGIN = 0x10000000, LENGTH = 128 +} + +SECTIONS +{ + .image_def : { + LONG(0xffffded3) /* PICOBIN_BLOCK_MARKER_START */ + LONG(0x10210142) /* IMAGE_DEF Item */ + LONG(0x00000203) /* VECTOR_TABLE Item */ + LONG(ABSOLUTE(_vector_start)) /* - Address of the vector table in flash */ + LONG(0x000003ff) /* Last Item in Block */ + LONG(0x00000000) /* End of block loop */ + LONG(0xab123579) /* PICOBIN_BLOCK_MARKER_END */ + } > IMAGE_DEF_FLASH +} + +#include diff --git a/soc/raspberrypi/rpi_pico/rp2350/soc.c b/soc/raspberrypi/rpi_pico/rp2350/soc.c new file mode 100644 index 000000000000..84bcbffc7d97 --- /dev/null +++ b/soc/raspberrypi/rpi_pico/rp2350/soc.c @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2024 Andrew Featherstone + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief System/hardware module for Raspberry Pi RP235xx MCUs + * + * This module provides routines to initialize and support board-level hardware + * for the Raspberry Pi RP235xx (RP2350A, RP2350B, RP2354A, RP2354B). + */ + +#if CONFIG_SOC_RESET_HOOK +#include + + +void soc_reset_hook(void) +{ + runtime_init_per_core_enable_coprocessors(); +} + +#endif /* CONFIG_SOC_RESET_HOOK */ diff --git a/soc/raspberrypi/soc.yml b/soc/raspberrypi/rpi_pico/soc.yml similarity index 50% rename from soc/raspberrypi/soc.yml rename to soc/raspberrypi/rpi_pico/soc.yml index 192d7a947f26..29752c7df42c 100644 --- a/soc/raspberrypi/soc.yml +++ b/soc/raspberrypi/rpi_pico/soc.yml @@ -1,6 +1,9 @@ family: - name: rpi_pico series: - - name: rp2xxx + - name: rp2040 socs: - name: rp2040 + - name: rp2350 + socs: + - name: rp2350a From 0c3568060cd1251ff553a2a1bf6471854a6419e5 Mon Sep 17 00:00:00 2001 From: Andrew Featherstone Date: Wed, 21 Aug 2024 20:50:36 +0100 Subject: [PATCH 10/25] drivers: clock_control: rpi_pico: Add support for the RP2350. Add support for SoC-specific clock ids and update the initialization function to support the existing RP2040 and add support for the RP2350. clock_control_rpi_pico.c uses numerical values for clock ids taken from rpi_pico_clock.h which are the "clock generator". For the RP2350 these values are different for some of the same logical clock sources, as well as the RP2040 and RP2350 having different clock sources available. Signed-off-by: Andrew Featherstone --- .../clock_control/clock_control_rpi_pico.c | 98 ++++++++++++++++--- dts/arm/raspberrypi/rpi_pico/rp2040.dtsi | 2 +- ...i_pico_clock.h => rpi_pico_clock_common.h} | 10 +- .../dt-bindings/clock/rpi_pico_rp2040_clock.h | 15 +++ 4 files changed, 103 insertions(+), 22 deletions(-) rename include/zephyr/dt-bindings/clock/{rpi_pico_clock.h => rpi_pico_clock_common.h} (77%) create mode 100644 include/zephyr/dt-bindings/clock/rpi_pico_rp2040_clock.h diff --git a/drivers/clock_control/clock_control_rpi_pico.c b/drivers/clock_control/clock_control_rpi_pico.c index e4c3afb46820..26d9dda4fde4 100644 --- a/drivers/clock_control/clock_control_rpi_pico.c +++ b/drivers/clock_control/clock_control_rpi_pico.c @@ -10,7 +10,11 @@ #include #include #include -#include +#if defined(CONFIG_SOC_SERIES_RP2040) +#include +#else +#include +#endif #include #include @@ -77,6 +81,7 @@ #define CLOCK_FREQ_clk_gpout1 DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, clk_gpout1), clock_frequency) #define CLOCK_FREQ_clk_gpout2 DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, clk_gpout2), clock_frequency) #define CLOCK_FREQ_clk_gpout3 DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, clk_gpout3), clock_frequency) +#define CLOCK_FREQ_clk_hstx DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, clk_hstx), clock_frequency) #define CLOCK_FREQ_clk_ref DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, clk_ref), clock_frequency) #define CLOCK_FREQ_clk_sys DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, clk_sys), clock_frequency) #define CLOCK_FREQ_clk_usb DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, clk_usb), clock_frequency) @@ -102,9 +107,16 @@ #define AUXSRC_clk_sys CLK_SYS #define AUXSRC_clk_usb CLK_USB #define AUXSRC_clk_adc CLK_ADC -#define AUXSRC_clk_rtc CLK_RTC #define AUXSRC_clk_gpin0 CLKSRC_GPIN0 #define AUXSRC_clk_gpin1 CLKSRC_GPIN1 +#if defined(CONFIG_SOC_SERIES_RP2040) +#define AUXSRC_clk_rtc CLK_RTC +#else +#define AUXSRC_pll_usb_primary_ref_opcg CLKSRC_PLL_PLL_USB_PRIMARY_REF_OPCG +#define AUXSRC_lposc LPOSC_CLKSRC +#define AUXSRC_clk_hstx CLK_HSTX +#define AUXSRC_otp_clk2fc OTP_CLK2FC +#endif #define AUXSTEM_clk_gpout0 CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_ #define AUXSTEM_clk_gpout1 CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_ @@ -114,8 +126,12 @@ #define AUXSTEM_clk_sys CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_ #define AUXSTEM_clk_usb CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_ #define AUXSTEM_clk_adc CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_ -#define AUXSTEM_clk_rtc CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_ -#define AUXSTEM_clk_peri CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_ +#define AUXSTEM_clk_peri CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_ +#if defined(CONFIG_SOC_SERIES_RP2040) +#define AUXSTEM_clk_rtc CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_ +#else +#define AUXSTEM_clk_hstx CLOCKS_CLK_HSTX_CTRL_AUXSRC_VALUE_ +#endif #define TUPLE_ENTRY(n, p, i) \ { \ @@ -141,7 +157,9 @@ enum rpi_pico_clkid { rpi_pico_clkid_clk_peri = RPI_PICO_CLKID_CLK_PERI, rpi_pico_clkid_clk_usb = RPI_PICO_CLKID_CLK_USB, rpi_pico_clkid_clk_adc = RPI_PICO_CLKID_CLK_ADC, +#if defined(RPI_PICO_CLKID_CLK_RTC) rpi_pico_clkid_clk_rtc = RPI_PICO_CLKID_CLK_RTC, +#endif rpi_pico_clkid_pll_sys = RPI_PICO_CLKID_PLL_SYS, rpi_pico_clkid_pll_usb = RPI_PICO_CLKID_PLL_USB, rpi_pico_clkid_xosc = RPI_PICO_CLKID_XOSC, @@ -223,9 +241,11 @@ uint64_t rpi_pico_frequency_count(const struct device *dev, clock_control_subsys case rpi_pico_clkid_clk_adc: fc0_id = CLOCKS_FC0_SRC_VALUE_CLK_ADC; break; +#if defined(CONFIG_SOC_SERIES_RP2040) case rpi_pico_clkid_clk_rtc: fc0_id = CLOCKS_FC0_SRC_VALUE_CLK_RTC; break; +#endif case rpi_pico_clkid_pll_sys: fc0_id = CLOCKS_FC0_SRC_VALUE_PLL_SYS_CLKSRC_PRIMARY; break; @@ -284,10 +304,13 @@ static int rpi_pico_rosc_write(const struct device *dev, io_rw_32 *addr, uint32_ static enum rpi_pico_clkid rpi_pico_get_clock_src(const struct device *dev, enum rpi_pico_clkid id) { const struct clock_control_rpi_pico_config *config = dev->config; - enum rpi_pico_clkid srcid = rpi_pico_clkid_none; + enum rpi_pico_clkid srcid; - if (id == rpi_pico_clkid_clk_gpout0 || id == rpi_pico_clkid_clk_gpout1 || - id == rpi_pico_clkid_clk_gpout2 || id == rpi_pico_clkid_clk_gpout3) { + switch (id) { + case rpi_pico_clkid_clk_gpout0: + case rpi_pico_clkid_clk_gpout1: + case rpi_pico_clkid_clk_gpout2: + case rpi_pico_clkid_clk_gpout3: { const static enum rpi_pico_clkid table[] = { rpi_pico_clkid_pll_sys, rpi_pico_clkid_gpin0, @@ -298,7 +321,9 @@ static enum rpi_pico_clkid rpi_pico_get_clock_src(const struct device *dev, enum rpi_pico_clkid_clk_sys, rpi_pico_clkid_clk_usb, rpi_pico_clkid_clk_adc, +#if defined(CONFIG_SOC_SERIES_RP2040) rpi_pico_clkid_clk_rtc, +#endif rpi_pico_clkid_clk_ref, }; @@ -306,7 +331,9 @@ static enum rpi_pico_clkid rpi_pico_get_clock_src(const struct device *dev, enum uint32_t aux = ((clock_hw->ctrl & CTRL_AUXSRC_BITS) >> CTRL_AUXSRC_LSB); srcid = table[aux]; - } else if (id == rpi_pico_clkid_clk_ref) { + break; + } + case rpi_pico_clkid_clk_ref: { const static enum rpi_pico_clkid table[] = { rpi_pico_clkid_pll_usb, rpi_pico_clkid_gpin0, @@ -324,7 +351,9 @@ static enum rpi_pico_clkid rpi_pico_get_clock_src(const struct device *dev, enum } else { srcid = table[aux]; } - } else if (id == rpi_pico_clkid_clk_sys) { + break; + } + case rpi_pico_clkid_clk_sys: { const static enum rpi_pico_clkid table[] = { rpi_pico_clkid_pll_sys, rpi_pico_clkid_pll_usb, @@ -343,7 +372,9 @@ static enum rpi_pico_clkid rpi_pico_get_clock_src(const struct device *dev, enum } else { srcid = table[aux]; } - } else if (id == rpi_pico_clkid_clk_peri) { + break; + } + case rpi_pico_clkid_clk_peri: { const static enum rpi_pico_clkid table[] = { rpi_pico_clkid_clk_sys, rpi_pico_clkid_pll_sys, @@ -358,8 +389,16 @@ static enum rpi_pico_clkid rpi_pico_get_clock_src(const struct device *dev, enum uint32_t aux = ((clock_hw->ctrl & CTRL_AUXSRC_BITS) >> CTRL_AUXSRC_LSB); srcid = table[aux]; - } else if (id == rpi_pico_clkid_clk_usb || id == rpi_pico_clkid_clk_adc || - id == rpi_pico_clkid_clk_rtc) { + break; + } + case rpi_pico_clkid_clk_usb: + case rpi_pico_clkid_clk_adc: +#if defined(RPI_PICO_CLKID_CLK_RTC) + case rpi_pico_clkid_clk_rtc: +#else + +#endif + { const static enum rpi_pico_clkid table[] = { rpi_pico_clkid_pll_usb, rpi_pico_clkid_pll_sys, @@ -373,8 +412,16 @@ static enum rpi_pico_clkid rpi_pico_get_clock_src(const struct device *dev, enum uint32_t aux = ((clock_hw->ctrl & CTRL_AUXSRC_BITS) >> CTRL_AUXSRC_LSB); srcid = table[aux]; - } else if (id == rpi_pico_clkid_pll_sys || id == rpi_pico_clkid_pll_usb) { + break; + } + case rpi_pico_clkid_pll_sys: + case rpi_pico_clkid_pll_usb: { srcid = rpi_pico_clkid_xosc; + break; + } + default: + srcid = rpi_pico_clkid_none; + break; } return srcid; @@ -396,7 +443,9 @@ static bool rpi_pico_is_clock_enabled(const struct device *dev, enum rpi_pico_cl } else if (id == rpi_pico_clkid_clk_usb || id == rpi_pico_clkid_clk_peri || id == rpi_pico_clkid_clk_adc || +#if defined(RPI_PICO_CLKID_CLK_RTC) id == rpi_pico_clkid_clk_rtc || +#endif id == rpi_pico_clkid_clk_gpout0 || id == rpi_pico_clkid_clk_gpout1 || id == rpi_pico_clkid_clk_gpout2 || @@ -444,7 +493,9 @@ static float rpi_pico_calc_clock_freq(const struct device *dev, enum rpi_pico_cl if (id == rpi_pico_clkid_clk_sys || id == rpi_pico_clkid_clk_usb || id == rpi_pico_clkid_clk_adc || +#if defined(RPI_PICO_CLKID_CLK_RTC) id == rpi_pico_clkid_clk_rtc || +#endif id == rpi_pico_clkid_clk_ref || id == rpi_pico_clkid_clk_gpout0 || id == rpi_pico_clkid_clk_gpout1 || @@ -611,13 +662,19 @@ static int clock_control_rpi_pico_init(const struct device *dev) RESETS_RESET_SYSCFG_BITS | RESETS_RESET_PLL_SYS_BITS)); unreset_block_wait(RESETS_RESET_BITS & - ~(RESETS_RESET_ADC_BITS | RESETS_RESET_RTC_BITS | + ~(RESETS_RESET_ADC_BITS | +#if defined(RESETS_RESET_RTC_BITS) + RESETS_RESET_RTC_BITS | +#endif +#if defined(RESETS_RESET_HSTX_BITS) + RESETS_RESET_HSTX_BITS | +#endif RESETS_RESET_SPI0_BITS | RESETS_RESET_SPI1_BITS | RESETS_RESET_UART0_BITS | RESETS_RESET_UART1_BITS | RESETS_RESET_USBCTRL_BITS)); /* Start tick in watchdog */ - watchdog_hw->tick = ((CLOCK_FREQ_xosc/1000000) | WATCHDOG_TICK_ENABLE_BITS); + watchdog_start_tick(CLOCK_FREQ_xosc / 1000000); clocks_regs->resus.ctrl = 0; @@ -755,8 +812,10 @@ BUILD_ASSERT(SRC_CLOCK_FREQ(clk_usb) >= CLOCK_FREQ_clk_usb, "clk_usb: clock divider is out of range"); BUILD_ASSERT(SRC_CLOCK_FREQ(clk_adc) >= CLOCK_FREQ_clk_adc, "clk_adc: clock divider is out of range"); +#if defined(CONFIG_SOC_SERIES_RP2040) BUILD_ASSERT(SRC_CLOCK_FREQ(clk_rtc) >= CLOCK_FREQ_clk_rtc, "clk_rtc: clock divider is out of range"); +#endif BUILD_ASSERT(SRC_CLOCK_FREQ(clk_peri) >= CLOCK_FREQ_clk_peri, "clk_peri: clock divider is out of range"); @@ -838,12 +897,21 @@ static const struct clock_control_rpi_pico_config clock_control_rpi_pico_config .source_rate = SRC_CLOCK_FREQ(clk_adc), .rate = CLOCK_FREQ(clk_adc), }, +#if defined(RPI_PICO_CLKID_CLK_RTC) [RPI_PICO_CLKID_CLK_RTC] = { .source = 0, .aux_source = CLOCK_AUX_SOURCE(clk_rtc), .source_rate = SRC_CLOCK_FREQ(clk_rtc), .rate = CLOCK_FREQ(clk_rtc), }, +#elif defined(RPI_PICO_CLKID_CLK_HSTX) + [RPI_PICO_CLKID_CLK_HSTX] = { + .source = 0, + .aux_source = CLOCK_AUX_SOURCE(clk_hstx), + .source_rate = SRC_CLOCK_FREQ(clk_hstx), + .rate = CLOCK_FREQ(clk_hstx), + }, +#endif }, .plls_data = { [RPI_PICO_PLL_SYS] = { diff --git a/dts/arm/raspberrypi/rpi_pico/rp2040.dtsi b/dts/arm/raspberrypi/rpi_pico/rp2040.dtsi index 45d5dfa71837..d2fed1b49fe1 100644 --- a/dts/arm/raspberrypi/rpi_pico/rp2040.dtsi +++ b/dts/arm/raspberrypi/rpi_pico/rp2040.dtsi @@ -7,7 +7,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/include/zephyr/dt-bindings/clock/rpi_pico_clock.h b/include/zephyr/dt-bindings/clock/rpi_pico_clock_common.h similarity index 77% rename from include/zephyr/dt-bindings/clock/rpi_pico_clock.h rename to include/zephyr/dt-bindings/clock/rpi_pico_clock_common.h index 07522be66329..f19c9baaa645 100644 --- a/include/zephyr/dt-bindings/clock/rpi_pico_clock.h +++ b/include/zephyr/dt-bindings/clock/rpi_pico_clock_common.h @@ -3,8 +3,8 @@ * * SPDX-License-Identifier: Apache-2.0 */ -#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RPI_PICO_CLOCK_H_ -#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RPI_PICO_CLOCK_H_ +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RPI_PICO_CLOCK_COMMON_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RPI_PICO_CLOCK_COMMON_H_ #define RPI_PICO_PLL_SYS 0 #define RPI_PICO_PLL_USB 1 @@ -21,9 +21,7 @@ #define RPI_PICO_CLKID_CLK_REF 4 #define RPI_PICO_CLKID_CLK_SYS 5 #define RPI_PICO_CLKID_CLK_PERI 6 -#define RPI_PICO_CLKID_CLK_USB 7 -#define RPI_PICO_CLKID_CLK_ADC 8 -#define RPI_PICO_CLKID_CLK_RTC 9 +/* N.b. clock ids 7-9 are defined in SoC-specific files. */ #define RPI_PICO_CLKID_PLL_SYS 10 #define RPI_PICO_CLKID_PLL_USB 11 @@ -41,4 +39,4 @@ #define RPI_PICO_CLOCK_COUNT 10 -#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RPI_PICO_CLOCK_H_ */ +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RPI_PICO_CLOCK_COMMON_H_ */ diff --git a/include/zephyr/dt-bindings/clock/rpi_pico_rp2040_clock.h b/include/zephyr/dt-bindings/clock/rpi_pico_rp2040_clock.h new file mode 100644 index 000000000000..c0c4786a0379 --- /dev/null +++ b/include/zephyr/dt-bindings/clock/rpi_pico_rp2040_clock.h @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2022 Andrei-Edward Popa + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RPI_PICO_CLOCK_RP2040_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RPI_PICO_CLOCK_RP2040_H_ + +#include "rpi_pico_clock_common.h" + +#define RPI_PICO_CLKID_CLK_USB 7 +#define RPI_PICO_CLKID_CLK_ADC 8 +#define RPI_PICO_CLKID_CLK_RTC 9 + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RPI_PICO_CLOCK_RP2040_H_ */ From cacef4119d5c7bad146602fbb9f457e364f05612 Mon Sep 17 00:00:00 2001 From: Andrew Featherstone Date: Fri, 23 Aug 2024 10:28:44 +0100 Subject: [PATCH 11/25] drivers: hwinfo: rp2350: Add initial support for RP2350 Extend the existing driver to add some initial support for the new SoC, whilst maintaining compatibility with the RP2040. Signed-off-by: Andrew Featherstone --- drivers/hwinfo/hwinfo_rpi_pico.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/drivers/hwinfo/hwinfo_rpi_pico.c b/drivers/hwinfo/hwinfo_rpi_pico.c index 89d5cb5654cd..b83078e4b494 100644 --- a/drivers/hwinfo/hwinfo_rpi_pico.c +++ b/drivers/hwinfo/hwinfo_rpi_pico.c @@ -1,5 +1,6 @@ /* * Copyright (c) 2022 Yonatan Schachter + * Copyright (c) 2024 Andrew Featherstone * * SPDX-License-Identifier: Apache-2.0 */ @@ -7,13 +8,23 @@ #include #include #include +#if defined(CONFIG_SOC_SERIES_RP2040) #include +#else +#include +#endif #define FLASH_RUID_DATA_BYTES 8 +#if defined(CONFIG_SOC_SERIES_RP2040) #define HAD_RUN_BIT BIT(VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN_LSB) #define HAD_PSM_RESTART_BIT BIT(VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART_LSB) #define HAD_POR_BIT BIT(VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR_LSB) +#else +#define HAD_RUN_BIT BIT(POWMAN_CHIP_RESET_HAD_RUN_LOW_LSB) +#define HAD_PSM_RESTART_BIT BIT(POWMAN_CHIP_RESET_HAD_DP_RESET_REQ_LSB) +#define HAD_POR_BIT BIT(POWMAN_CHIP_RESET_HAD_POR_LSB) +#endif ssize_t z_impl_hwinfo_get_device_id(uint8_t *buffer, size_t length) { @@ -41,7 +52,11 @@ ssize_t z_impl_hwinfo_get_device_id(uint8_t *buffer, size_t length) int z_impl_hwinfo_get_reset_cause(uint32_t *cause) { uint32_t flags = 0; +#if defined(CONFIG_SOC_SERIES_RP2040) uint32_t reset_register = vreg_and_chip_reset_hw->chip_reset; +#else + uint32_t reset_register = powman_hw->chip_reset; +#endif if (reset_register & HAD_POR_BIT) { flags |= RESET_POR; @@ -54,6 +69,18 @@ int z_impl_hwinfo_get_reset_cause(uint32_t *cause) if (reset_register & HAD_PSM_RESTART_BIT) { flags |= RESET_DEBUG; } +#if defined(CONFIG_SOC_SERIES_RP2350) + if (reset_register & POWMAN_CHIP_RESET_HAD_BOR_BITS) { + flags |= RESET_BROWNOUT; + } + + if (reset_register & (POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_RSM_BITS | + POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_SWCORE_BITS | + POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_POWMAN_BITS | + POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_POWMAN_ASYNC_BITS)) { + flags |= RESET_WATCHDOG; + } +#endif *cause = flags; return 0; @@ -69,6 +96,9 @@ int z_impl_hwinfo_clear_reset_cause(void) int z_impl_hwinfo_get_supported_reset_cause(uint32_t *supported) { *supported = RESET_PIN | RESET_DEBUG | RESET_POR; +#if defined(CONFIG_SOC_SERIES_RP2350) + *supported |= RESET_BROWNOUT | RESET_WATCHDOG; +#endif return 0; } From e415533731abd44a14545f4f0076c120c5d63743 Mon Sep 17 00:00:00 2001 From: Andrew Featherstone Date: Sun, 1 Sep 2024 11:04:16 +0100 Subject: [PATCH 12/25] drivers: clock_control: rpi_pico: Start tick generators for timers Unlike the RP2040, the RP2350 has multiple tick generators that need to be started. Start TIMER0 and TIMER1 tick generators during clock_control_init. Signed-off-by: Andrew Featherstone --- drivers/clock_control/clock_control_rpi_pico.c | 8 +++++++- modules/hal_rpi_pico/CMakeLists.txt | 1 + 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/clock_control/clock_control_rpi_pico.c b/drivers/clock_control/clock_control_rpi_pico.c index 26d9dda4fde4..e5d630aebf89 100644 --- a/drivers/clock_control/clock_control_rpi_pico.c +++ b/drivers/clock_control/clock_control_rpi_pico.c @@ -22,6 +22,7 @@ #include #include #include +#include /* Undefine to prevent conflicts with header definitions */ #undef pll_sys @@ -646,6 +647,7 @@ void rpi_pico_clkid_tuple_reorder_by_dependencies(struct rpi_pico_clkid_tuple *t static int clock_control_rpi_pico_init(const struct device *dev) { + const uint32_t cycles_per_tick = CLOCK_FREQ_xosc / 1000000; const struct clock_control_rpi_pico_config *config = dev->config; struct clock_control_rpi_pico_data *data = dev->data; clocks_hw_t *clocks_regs = config->clocks_regs; @@ -674,7 +676,11 @@ static int clock_control_rpi_pico_init(const struct device *dev) RESETS_RESET_USBCTRL_BITS)); /* Start tick in watchdog */ - watchdog_start_tick(CLOCK_FREQ_xosc / 1000000); + watchdog_start_tick(cycles_per_tick); +#if defined(CONFIG_SOC_SERIES_RP2350) + tick_start(TICK_TIMER0, cycles_per_tick); + tick_start(TICK_TIMER1, cycles_per_tick); +#endif clocks_regs->resus.ctrl = 0; diff --git a/modules/hal_rpi_pico/CMakeLists.txt b/modules/hal_rpi_pico/CMakeLists.txt index 6fa5559afa65..9b3b2e9b8477 100644 --- a/modules/hal_rpi_pico/CMakeLists.txt +++ b/modules/hal_rpi_pico/CMakeLists.txt @@ -62,6 +62,7 @@ if(CONFIG_HAS_RPI_PICO) ${rp2_common_dir}/hardware_xosc/xosc.c ${rp2_common_dir}/hardware_watchdog/watchdog.c ${rp2_common_dir}/hardware_sync_spin_lock/sync_spin_lock.c + ${rp2_common_dir}/hardware_ticks/ticks.c ${rp2_common_dir}/pico_bootrom/bootrom.c ${rp2xxx_dir}/pico_platform/platform.c ) From 9cc824b08ac0c6b34a89b21a48159cdb5623f887 Mon Sep 17 00:00:00 2001 From: TOKITA Hiroshi Date: Mon, 2 Sep 2024 23:54:56 +0900 Subject: [PATCH 13/25] drivers: watchdog: rpi_pico: Add support for RP2350 The watchdog register configuration of RP2350 differs from that of RP2040, so we make fit that. Signed-off-by: TOKITA Hiroshi Signed-off-by: Andrew Featherstone --- drivers/watchdog/wdt_rpi_pico.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/watchdog/wdt_rpi_pico.c b/drivers/watchdog/wdt_rpi_pico.c index 7d3f2a5fc607..d9ab8f497962 100644 --- a/drivers/watchdog/wdt_rpi_pico.c +++ b/drivers/watchdog/wdt_rpi_pico.c @@ -7,6 +7,7 @@ #define DT_DRV_COMPAT raspberrypi_pico_watchdog #include +#include #include #include #include @@ -15,9 +16,13 @@ #include LOG_MODULE_REGISTER(wdt_rpi_pico, CONFIG_WDT_LOG_LEVEL); +#ifdef CONFIG_SOC_RP2040 /* Maximum watchdog time is halved due to errata RP2040-E1 */ -#define RPI_PICO_MAX_WDT_TIME (0xffffff / 2) #define RPI_PICO_WDT_TIME_MULTIPLICATION_FACTOR 2 +#else +#define RPI_PICO_WDT_TIME_MULTIPLICATION_FACTOR 1 +#endif +#define RPI_PICO_MAX_WDT_TIME (0xffffff / RPI_PICO_WDT_TIME_MULTIPLICATION_FACTOR) /* Watchdog requires a 1MHz clock source, divided from the crystal oscillator */ #define RPI_PICO_CLK_REF_FREQ_WDT_TICK_DIVISOR 1000000 @@ -89,8 +94,13 @@ static int wdt_rpi_pico_setup(const struct device *dev, uint8_t options) return err; } +#ifdef CONFIG_SOC_RP2040 watchdog_hw->tick = (ref_clk / RPI_PICO_CLK_REF_FREQ_WDT_TICK_DIVISOR) | WATCHDOG_TICK_ENABLE_BITS; +#else + ticks_hw->ticks[TICK_WATCHDOG].cycles = ref_clk / RPI_PICO_CLK_REF_FREQ_WDT_TICK_DIVISOR; + ticks_hw->ticks[TICK_WATCHDOG].ctrl = TICKS_WATCHDOG_CTRL_ENABLE_BITS; +#endif return 0; } From 4ffd58a8309465442a219c409d40b68325886068 Mon Sep 17 00:00:00 2001 From: Andrew Featherstone Date: Wed, 25 Sep 2024 11:37:40 +0100 Subject: [PATCH 14/25] drivers: counter: rpi_pico_timer: Add support for RP2350 The RP2350 SoC series contain two timer peripherals. Extend the driver to support using the second timer (`TIMER1`). N.b. this requires a fix from the Pico SDK to be patched into hal_rpi_pico. See https://github.com/raspberrypi/pico-sdk/pull/1949 . Signed-off-by: Andrew Featherstone --- drivers/counter/counter_rpi_pico_timer.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/counter/counter_rpi_pico_timer.c b/drivers/counter/counter_rpi_pico_timer.c index c2140d587774..341aa20c9236 100644 --- a/drivers/counter/counter_rpi_pico_timer.c +++ b/drivers/counter/counter_rpi_pico_timer.c @@ -95,11 +95,11 @@ static int counter_rpi_pico_timer_set_alarm(const struct device *dev, uint8_t id chdata->callback = alarm_cfg->callback; chdata->user_data = alarm_cfg->user_data; - missed = hardware_alarm_set_target(id, alarm_at); + missed = timer_hardware_alarm_set_target(config->timer, id, alarm_at); if (missed) { if (alarm_cfg->flags & COUNTER_ALARM_CFG_EXPIRE_WHEN_LATE) { - hardware_alarm_force_irq(id); + timer_hardware_alarm_force_irq(config->timer, id); } chdata->callback = NULL; chdata->user_data = NULL; @@ -113,10 +113,11 @@ static int counter_rpi_pico_timer_cancel_alarm(const struct device *dev, uint8_t { struct counter_rpi_pico_timer_data *data = dev->data; struct counter_rpi_pico_timer_ch_data *chdata = &data->ch_data[id]; + const struct counter_rpi_pico_timer_config *config = dev->config; chdata->callback = NULL; chdata->user_data = NULL; - hardware_alarm_cancel(id); + timer_hardware_alarm_cancel(config->timer, id); return 0; } @@ -203,7 +204,8 @@ static const struct counter_driver_api counter_rpi_pico_driver_api = { #define RPI_PICO_TIMER_IRQ_ENABLE(node_id, name, idx) \ do { \ - hardware_alarm_set_callback(idx, counter_rpi_pico_irq_handle); \ + timer_hardware_alarm_set_callback((timer_hw_t *)DT_REG_ADDR(node_id), idx, \ + counter_rpi_pico_irq_handle); \ IRQ_CONNECT((DT_IRQ_BY_IDX(node_id, idx, irq)), \ (DT_IRQ_BY_IDX(node_id, idx, priority)), hardware_alarm_irq_handler, \ (DEVICE_DT_GET(node_id)), 0); \ From c9591f9cc2d081be83cfa5bee1037dbbc20e19c7 Mon Sep 17 00:00:00 2001 From: Andrew Featherstone Date: Mon, 9 Sep 2024 13:50:38 +0100 Subject: [PATCH 15/25] pinctrl: raspberrypi: rp2350: Add support for RP2350X A significant amount of the pin muxing is duplicated between the RP2040, the RP2350A, and RP2350B. Reflect this in the file structure, with a `-common` suffix used to to indicate this. Macros are defined in ascending order of the function index in the relevant table in the datasheet. SoC/SoC-series specific macros are defined in their respective tables. Functions that are not currently used (e.g. the new HSTX) are intentionally not defined here as they do not (currently) have any use in the Zephyr tree (i.e. there's no drivers that make use of this functionality). clang-format has been run over the existing definitions to reduce the noise generated by CI. These are cosmetic changes; I've tried to retain attribution to the relevant authors where applicable. Signed-off-by: Andrew Featherstone --- .../pinctrl/rpi-pico-pinctrl-common.h | 230 ++++++++++++++++++ .../pinctrl/rpi-pico-rp2040-pinctrl.h | 226 +---------------- .../pinctrl/rpi-pico-rp2350-pinctrl-common.h | 71 ++++++ .../pinctrl/rpi-pico-rp2350a-pinctrl.h | 20 ++ .../pinctrl/rpi-pico-rp2350b-pinctrl.h | 182 ++++++++++++++ soc/raspberrypi/rpi_pico/common/pinctrl_soc.h | 2 +- 6 files changed, 511 insertions(+), 220 deletions(-) create mode 100644 include/zephyr/dt-bindings/pinctrl/rpi-pico-pinctrl-common.h create mode 100644 include/zephyr/dt-bindings/pinctrl/rpi-pico-rp2350-pinctrl-common.h create mode 100644 include/zephyr/dt-bindings/pinctrl/rpi-pico-rp2350a-pinctrl.h create mode 100644 include/zephyr/dt-bindings/pinctrl/rpi-pico-rp2350b-pinctrl.h diff --git a/include/zephyr/dt-bindings/pinctrl/rpi-pico-pinctrl-common.h b/include/zephyr/dt-bindings/pinctrl/rpi-pico-pinctrl-common.h new file mode 100644 index 000000000000..d6a26cf220f4 --- /dev/null +++ b/include/zephyr/dt-bindings/pinctrl/rpi-pico-pinctrl-common.h @@ -0,0 +1,230 @@ +/* + * Copyright (c) 2021, Yonatan Schachter + * Copyright (c) 2024, Andrew Featherstone + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef __RPI_PICO_PINCTRL_COMMON_H__ +#define __RPI_PICO_PINCTRL_COMMON_H__ + +#define RP2_ALT_FUNC_POS 0 +#define RP2_ALT_FUNC_MASK 0xf + +#define RP2_PIN_NUM_POS 4 +#define RP2_PIN_NUM_MASK 0x1f + +#define RP2_GPIO_OVERRIDE_NORMAL 0 +#define RP2_GPIO_OVERRIDE_INVERT 1 +#define RP2_GPIO_OVERRIDE_LOW 2 +#define RP2_GPIO_OVERRIDE_HIGH 3 + +#define RP2XXX_PINMUX(pin_num, alt_func) (pin_num << RP2_PIN_NUM_POS | alt_func << RP2_ALT_FUNC_POS) + +/* These function are common. SoC-specific functions are defined in their + * respective header file. Refer to table 279 and 642 in the RP2040 and RP2350 + * datasheets for the source of these numbers. + */ +#define RP2_PINCTRL_GPIO_FUNC_SPI 1 +#define RP2_PINCTRL_GPIO_FUNC_UART 2 +#define RP2_PINCTRL_GPIO_FUNC_I2C 3 +#define RP2_PINCTRL_GPIO_FUNC_PWM 4 +#define RP2_PINCTRL_GPIO_FUNC_SIO 5 +#define RP2_PINCTRL_GPIO_FUNC_PIO0 6 +#define RP2_PINCTRL_GPIO_FUNC_PIO1 7 + +/* These pin assignments for each function are similarly common. */ +#define SPI0_RX_P0 RP2XXX_PINMUX(0, RP2_PINCTRL_GPIO_FUNC_SPI) +#define SPI0_CSN_P1 RP2XXX_PINMUX(1, RP2_PINCTRL_GPIO_FUNC_SPI) +#define SPI0_SCK_P2 RP2XXX_PINMUX(2, RP2_PINCTRL_GPIO_FUNC_SPI) +#define SPI0_TX_P3 RP2XXX_PINMUX(3, RP2_PINCTRL_GPIO_FUNC_SPI) +#define SPI0_RX_P4 RP2XXX_PINMUX(4, RP2_PINCTRL_GPIO_FUNC_SPI) +#define SPI0_CSN_P5 RP2XXX_PINMUX(5, RP2_PINCTRL_GPIO_FUNC_SPI) +#define SPI0_SCK_P6 RP2XXX_PINMUX(6, RP2_PINCTRL_GPIO_FUNC_SPI) +#define SPI0_TX_P7 RP2XXX_PINMUX(7, RP2_PINCTRL_GPIO_FUNC_SPI) +#define SPI1_RX_P8 RP2XXX_PINMUX(8, RP2_PINCTRL_GPIO_FUNC_SPI) +#define SPI1_CSN_P9 RP2XXX_PINMUX(9, RP2_PINCTRL_GPIO_FUNC_SPI) +#define SPI1_SCK_P10 RP2XXX_PINMUX(10, RP2_PINCTRL_GPIO_FUNC_SPI) +#define SPI1_TX_P11 RP2XXX_PINMUX(11, RP2_PINCTRL_GPIO_FUNC_SPI) +#define SPI1_RX_P12 RP2XXX_PINMUX(12, RP2_PINCTRL_GPIO_FUNC_SPI) +#define SPI1_CSN_P13 RP2XXX_PINMUX(13, RP2_PINCTRL_GPIO_FUNC_SPI) +#define SPI1_SCK_P14 RP2XXX_PINMUX(14, RP2_PINCTRL_GPIO_FUNC_SPI) +#define SPI1_TX_P15 RP2XXX_PINMUX(15, RP2_PINCTRL_GPIO_FUNC_SPI) +#define SPI0_RX_P16 RP2XXX_PINMUX(16, RP2_PINCTRL_GPIO_FUNC_SPI) +#define SPI0_CSN_P17 RP2XXX_PINMUX(17, RP2_PINCTRL_GPIO_FUNC_SPI) +#define SPI0_SCK_P18 RP2XXX_PINMUX(18, RP2_PINCTRL_GPIO_FUNC_SPI) +#define SPI0_TX_P19 RP2XXX_PINMUX(19, RP2_PINCTRL_GPIO_FUNC_SPI) +#define SPI0_RX_P20 RP2XXX_PINMUX(20, RP2_PINCTRL_GPIO_FUNC_SPI) +#define SPI0_CSN_P21 RP2XXX_PINMUX(21, RP2_PINCTRL_GPIO_FUNC_SPI) +#define SPI0_SCK_P22 RP2XXX_PINMUX(22, RP2_PINCTRL_GPIO_FUNC_SPI) +#define SPI0_TX_P23 RP2XXX_PINMUX(23, RP2_PINCTRL_GPIO_FUNC_SPI) +#define SPI1_RX_P24 RP2XXX_PINMUX(24, RP2_PINCTRL_GPIO_FUNC_SPI) +#define SPI1_CSN_P25 RP2XXX_PINMUX(25, RP2_PINCTRL_GPIO_FUNC_SPI) +#define SPI1_SCK_P26 RP2XXX_PINMUX(26, RP2_PINCTRL_GPIO_FUNC_SPI) +#define SPI1_TX_P27 RP2XXX_PINMUX(27, RP2_PINCTRL_GPIO_FUNC_SPI) +#define SPI1_RX_P28 RP2XXX_PINMUX(28, RP2_PINCTRL_GPIO_FUNC_SPI) +#define SPI1_CSN_P29 RP2XXX_PINMUX(29, RP2_PINCTRL_GPIO_FUNC_SPI) + +#define UART0_TX_P0 RP2XXX_PINMUX(0, RP2_PINCTRL_GPIO_FUNC_UART) +#define UART0_RX_P1 RP2XXX_PINMUX(1, RP2_PINCTRL_GPIO_FUNC_UART) +#define UART0_CTS_P2 RP2XXX_PINMUX(2, RP2_PINCTRL_GPIO_FUNC_UART) +#define UART0_RTS_P3 RP2XXX_PINMUX(3, RP2_PINCTRL_GPIO_FUNC_UART) +#define UART1_TX_P4 RP2XXX_PINMUX(4, RP2_PINCTRL_GPIO_FUNC_UART) +#define UART1_RX_P5 RP2XXX_PINMUX(5, RP2_PINCTRL_GPIO_FUNC_UART) +#define UART1_CTS_P6 RP2XXX_PINMUX(6, RP2_PINCTRL_GPIO_FUNC_UART) +#define UART1_RTS_P7 RP2XXX_PINMUX(7, RP2_PINCTRL_GPIO_FUNC_UART) +#define UART1_TX_P8 RP2XXX_PINMUX(8, RP2_PINCTRL_GPIO_FUNC_UART) +#define UART1_RX_P9 RP2XXX_PINMUX(9, RP2_PINCTRL_GPIO_FUNC_UART) +#define UART1_CTS_P10 RP2XXX_PINMUX(10, RP2_PINCTRL_GPIO_FUNC_UART) +#define UART1_RTS_P11 RP2XXX_PINMUX(11, RP2_PINCTRL_GPIO_FUNC_UART) +#define UART0_TX_P12 RP2XXX_PINMUX(12, RP2_PINCTRL_GPIO_FUNC_UART) +#define UART0_RX_P13 RP2XXX_PINMUX(13, RP2_PINCTRL_GPIO_FUNC_UART) +#define UART0_CTS_P14 RP2XXX_PINMUX(14, RP2_PINCTRL_GPIO_FUNC_UART) +#define UART0_RTS_P15 RP2XXX_PINMUX(15, RP2_PINCTRL_GPIO_FUNC_UART) +#define UART0_TX_P16 RP2XXX_PINMUX(16, RP2_PINCTRL_GPIO_FUNC_UART) +#define UART0_RX_P17 RP2XXX_PINMUX(17, RP2_PINCTRL_GPIO_FUNC_UART) +#define UART0_CTS_P18 RP2XXX_PINMUX(18, RP2_PINCTRL_GPIO_FUNC_UART) +#define UART0_RTS_P19 RP2XXX_PINMUX(19, RP2_PINCTRL_GPIO_FUNC_UART) +#define UART1_TX_P20 RP2XXX_PINMUX(20, RP2_PINCTRL_GPIO_FUNC_UART) +#define UART1_RX_P21 RP2XXX_PINMUX(21, RP2_PINCTRL_GPIO_FUNC_UART) +#define UART1_CTS_P22 RP2XXX_PINMUX(22, RP2_PINCTRL_GPIO_FUNC_UART) +#define UART1_RTS_P23 RP2XXX_PINMUX(23, RP2_PINCTRL_GPIO_FUNC_UART) +#define UART1_TX_P24 RP2XXX_PINMUX(24, RP2_PINCTRL_GPIO_FUNC_UART) +#define UART1_RX_P25 RP2XXX_PINMUX(25, RP2_PINCTRL_GPIO_FUNC_UART) +#define UART1_CTS_P26 RP2XXX_PINMUX(26, RP2_PINCTRL_GPIO_FUNC_UART) +#define UART1_RTS_P27 RP2XXX_PINMUX(27, RP2_PINCTRL_GPIO_FUNC_UART) +#define UART0_TX_P28 RP2XXX_PINMUX(28, RP2_PINCTRL_GPIO_FUNC_UART) +#define UART0_RX_P29 RP2XXX_PINMUX(29, RP2_PINCTRL_GPIO_FUNC_UART) + +#define I2C0_SDA_P0 RP2XXX_PINMUX(0, RP2_PINCTRL_GPIO_FUNC_I2C) +#define I2C0_SCL_P1 RP2XXX_PINMUX(1, RP2_PINCTRL_GPIO_FUNC_I2C) +#define I2C1_SDA_P2 RP2XXX_PINMUX(2, RP2_PINCTRL_GPIO_FUNC_I2C) +#define I2C1_SCL_P3 RP2XXX_PINMUX(3, RP2_PINCTRL_GPIO_FUNC_I2C) +#define I2C0_SDA_P4 RP2XXX_PINMUX(4, RP2_PINCTRL_GPIO_FUNC_I2C) +#define I2C0_SCL_P5 RP2XXX_PINMUX(5, RP2_PINCTRL_GPIO_FUNC_I2C) +#define I2C1_SDA_P6 RP2XXX_PINMUX(6, RP2_PINCTRL_GPIO_FUNC_I2C) +#define I2C1_SCL_P7 RP2XXX_PINMUX(7, RP2_PINCTRL_GPIO_FUNC_I2C) +#define I2C0_SDA_P8 RP2XXX_PINMUX(8, RP2_PINCTRL_GPIO_FUNC_I2C) +#define I2C0_SCL_P9 RP2XXX_PINMUX(9, RP2_PINCTRL_GPIO_FUNC_I2C) +#define I2C1_SDA_P10 RP2XXX_PINMUX(10, RP2_PINCTRL_GPIO_FUNC_I2C) +#define I2C1_SCL_P11 RP2XXX_PINMUX(11, RP2_PINCTRL_GPIO_FUNC_I2C) +#define I2C0_SDA_P12 RP2XXX_PINMUX(12, RP2_PINCTRL_GPIO_FUNC_I2C) +#define I2C0_SCL_P13 RP2XXX_PINMUX(13, RP2_PINCTRL_GPIO_FUNC_I2C) +#define I2C1_SDA_P14 RP2XXX_PINMUX(14, RP2_PINCTRL_GPIO_FUNC_I2C) +#define I2C1_SCL_P15 RP2XXX_PINMUX(15, RP2_PINCTRL_GPIO_FUNC_I2C) +#define I2C0_SDA_P16 RP2XXX_PINMUX(16, RP2_PINCTRL_GPIO_FUNC_I2C) +#define I2C0_SCL_P17 RP2XXX_PINMUX(17, RP2_PINCTRL_GPIO_FUNC_I2C) +#define I2C1_SDA_P18 RP2XXX_PINMUX(18, RP2_PINCTRL_GPIO_FUNC_I2C) +#define I2C1_SCL_P19 RP2XXX_PINMUX(19, RP2_PINCTRL_GPIO_FUNC_I2C) +#define I2C0_SDA_P20 RP2XXX_PINMUX(20, RP2_PINCTRL_GPIO_FUNC_I2C) +#define I2C0_SCL_P21 RP2XXX_PINMUX(21, RP2_PINCTRL_GPIO_FUNC_I2C) +#define I2C1_SDA_P22 RP2XXX_PINMUX(22, RP2_PINCTRL_GPIO_FUNC_I2C) +#define I2C1_SCL_P23 RP2XXX_PINMUX(23, RP2_PINCTRL_GPIO_FUNC_I2C) +#define I2C0_SDA_P24 RP2XXX_PINMUX(24, RP2_PINCTRL_GPIO_FUNC_I2C) +#define I2C0_SCL_P25 RP2XXX_PINMUX(25, RP2_PINCTRL_GPIO_FUNC_I2C) +#define I2C1_SDA_P26 RP2XXX_PINMUX(26, RP2_PINCTRL_GPIO_FUNC_I2C) +#define I2C1_SCL_P27 RP2XXX_PINMUX(27, RP2_PINCTRL_GPIO_FUNC_I2C) +#define I2C0_SDA_P28 RP2XXX_PINMUX(28, RP2_PINCTRL_GPIO_FUNC_I2C) +#define I2C0_SCL_P29 RP2XXX_PINMUX(29, RP2_PINCTRL_GPIO_FUNC_I2C) + +#define PWM_0A_P0 RP2XXX_PINMUX(0, RP2_PINCTRL_GPIO_FUNC_PWM) +#define PWM_0B_P1 RP2XXX_PINMUX(1, RP2_PINCTRL_GPIO_FUNC_PWM) +#define PWM_1A_P2 RP2XXX_PINMUX(2, RP2_PINCTRL_GPIO_FUNC_PWM) +#define PWM_1B_P3 RP2XXX_PINMUX(3, RP2_PINCTRL_GPIO_FUNC_PWM) +#define PWM_2A_P4 RP2XXX_PINMUX(4, RP2_PINCTRL_GPIO_FUNC_PWM) +#define PWM_2B_P5 RP2XXX_PINMUX(5, RP2_PINCTRL_GPIO_FUNC_PWM) +#define PWM_3A_P6 RP2XXX_PINMUX(6, RP2_PINCTRL_GPIO_FUNC_PWM) +#define PWM_3B_P7 RP2XXX_PINMUX(7, RP2_PINCTRL_GPIO_FUNC_PWM) +#define PWM_4A_P8 RP2XXX_PINMUX(8, RP2_PINCTRL_GPIO_FUNC_PWM) +#define PWM_4B_P9 RP2XXX_PINMUX(9, RP2_PINCTRL_GPIO_FUNC_PWM) +#define PWM_5A_P10 RP2XXX_PINMUX(10, RP2_PINCTRL_GPIO_FUNC_PWM) +#define PWM_5B_P11 RP2XXX_PINMUX(11, RP2_PINCTRL_GPIO_FUNC_PWM) +#define PWM_6A_P12 RP2XXX_PINMUX(12, RP2_PINCTRL_GPIO_FUNC_PWM) +#define PWM_6B_P13 RP2XXX_PINMUX(13, RP2_PINCTRL_GPIO_FUNC_PWM) +#define PWM_7A_P14 RP2XXX_PINMUX(14, RP2_PINCTRL_GPIO_FUNC_PWM) +#define PWM_7B_P15 RP2XXX_PINMUX(15, RP2_PINCTRL_GPIO_FUNC_PWM) +#define PWM_0A_P16 RP2XXX_PINMUX(16, RP2_PINCTRL_GPIO_FUNC_PWM) +#define PWM_0B_P17 RP2XXX_PINMUX(17, RP2_PINCTRL_GPIO_FUNC_PWM) +#define PWM_1A_P18 RP2XXX_PINMUX(18, RP2_PINCTRL_GPIO_FUNC_PWM) +#define PWM_1B_P19 RP2XXX_PINMUX(19, RP2_PINCTRL_GPIO_FUNC_PWM) +#define PWM_2A_P20 RP2XXX_PINMUX(20, RP2_PINCTRL_GPIO_FUNC_PWM) +#define PWM_2B_P21 RP2XXX_PINMUX(21, RP2_PINCTRL_GPIO_FUNC_PWM) +#define PWM_3A_P22 RP2XXX_PINMUX(22, RP2_PINCTRL_GPIO_FUNC_PWM) +#define PWM_3B_P22 RP2XXX_PINMUX(23, RP2_PINCTRL_GPIO_FUNC_PWM) +#define PWM_4A_P24 RP2XXX_PINMUX(24, RP2_PINCTRL_GPIO_FUNC_PWM) +#define PWM_4B_P25 RP2XXX_PINMUX(25, RP2_PINCTRL_GPIO_FUNC_PWM) +#define PWM_5A_P26 RP2XXX_PINMUX(26, RP2_PINCTRL_GPIO_FUNC_PWM) +#define PWM_5B_P27 RP2XXX_PINMUX(27, RP2_PINCTRL_GPIO_FUNC_PWM) +#define PWM_6A_P28 RP2XXX_PINMUX(28, RP2_PINCTRL_GPIO_FUNC_PWM) +#define PWM_6B_P29 RP2XXX_PINMUX(29, RP2_PINCTRL_GPIO_FUNC_PWM) + +#define PIO0_P0 RP2XXX_PINMUX(0, RP2_PINCTRL_GPIO_FUNC_PIO0) +#define PIO0_P1 RP2XXX_PINMUX(1, RP2_PINCTRL_GPIO_FUNC_PIO0) +#define PIO0_P2 RP2XXX_PINMUX(2, RP2_PINCTRL_GPIO_FUNC_PIO0) +#define PIO0_P3 RP2XXX_PINMUX(3, RP2_PINCTRL_GPIO_FUNC_PIO0) +#define PIO0_P4 RP2XXX_PINMUX(4, RP2_PINCTRL_GPIO_FUNC_PIO0) +#define PIO0_P5 RP2XXX_PINMUX(5, RP2_PINCTRL_GPIO_FUNC_PIO0) +#define PIO0_P6 RP2XXX_PINMUX(6, RP2_PINCTRL_GPIO_FUNC_PIO0) +#define PIO0_P7 RP2XXX_PINMUX(7, RP2_PINCTRL_GPIO_FUNC_PIO0) +#define PIO0_P8 RP2XXX_PINMUX(8, RP2_PINCTRL_GPIO_FUNC_PIO0) +#define PIO0_P9 RP2XXX_PINMUX(9, RP2_PINCTRL_GPIO_FUNC_PIO0) +#define PIO0_P10 RP2XXX_PINMUX(10, RP2_PINCTRL_GPIO_FUNC_PIO0) +#define PIO0_P11 RP2XXX_PINMUX(11, RP2_PINCTRL_GPIO_FUNC_PIO0) +#define PIO0_P12 RP2XXX_PINMUX(12, RP2_PINCTRL_GPIO_FUNC_PIO0) +#define PIO0_P13 RP2XXX_PINMUX(13, RP2_PINCTRL_GPIO_FUNC_PIO0) +#define PIO0_P14 RP2XXX_PINMUX(14, RP2_PINCTRL_GPIO_FUNC_PIO0) +#define PIO0_P15 RP2XXX_PINMUX(15, RP2_PINCTRL_GPIO_FUNC_PIO0) +#define PIO0_P16 RP2XXX_PINMUX(16, RP2_PINCTRL_GPIO_FUNC_PIO0) +#define PIO0_P17 RP2XXX_PINMUX(17, RP2_PINCTRL_GPIO_FUNC_PIO0) +#define PIO0_P18 RP2XXX_PINMUX(18, RP2_PINCTRL_GPIO_FUNC_PIO0) +#define PIO0_P19 RP2XXX_PINMUX(19, RP2_PINCTRL_GPIO_FUNC_PIO0) +#define PIO0_P20 RP2XXX_PINMUX(20, RP2_PINCTRL_GPIO_FUNC_PIO0) +#define PIO0_P21 RP2XXX_PINMUX(21, RP2_PINCTRL_GPIO_FUNC_PIO0) +#define PIO0_P22 RP2XXX_PINMUX(22, RP2_PINCTRL_GPIO_FUNC_PIO0) +#define PIO0_P23 RP2XXX_PINMUX(23, RP2_PINCTRL_GPIO_FUNC_PIO0) +#define PIO0_P24 RP2XXX_PINMUX(24, RP2_PINCTRL_GPIO_FUNC_PIO0) +#define PIO0_P25 RP2XXX_PINMUX(25, RP2_PINCTRL_GPIO_FUNC_PIO0) +#define PIO0_P26 RP2XXX_PINMUX(26, RP2_PINCTRL_GPIO_FUNC_PIO0) +#define PIO0_P27 RP2XXX_PINMUX(27, RP2_PINCTRL_GPIO_FUNC_PIO0) +#define PIO0_P28 RP2XXX_PINMUX(28, RP2_PINCTRL_GPIO_FUNC_PIO0) +#define PIO0_P29 RP2XXX_PINMUX(29, RP2_PINCTRL_GPIO_FUNC_PIO0) + +#define PIO1_P0 RP2XXX_PINMUX(0, RP2_PINCTRL_GPIO_FUNC_PIO1) +#define PIO1_P1 RP2XXX_PINMUX(1, RP2_PINCTRL_GPIO_FUNC_PIO1) +#define PIO1_P2 RP2XXX_PINMUX(2, RP2_PINCTRL_GPIO_FUNC_PIO1) +#define PIO1_P3 RP2XXX_PINMUX(3, RP2_PINCTRL_GPIO_FUNC_PIO1) +#define PIO1_P4 RP2XXX_PINMUX(4, RP2_PINCTRL_GPIO_FUNC_PIO1) +#define PIO1_P5 RP2XXX_PINMUX(5, RP2_PINCTRL_GPIO_FUNC_PIO1) +#define PIO1_P6 RP2XXX_PINMUX(6, RP2_PINCTRL_GPIO_FUNC_PIO1) +#define PIO1_P7 RP2XXX_PINMUX(7, RP2_PINCTRL_GPIO_FUNC_PIO1) +#define PIO1_P8 RP2XXX_PINMUX(8, RP2_PINCTRL_GPIO_FUNC_PIO1) +#define PIO1_P9 RP2XXX_PINMUX(9, RP2_PINCTRL_GPIO_FUNC_PIO1) +#define PIO1_P10 RP2XXX_PINMUX(10, RP2_PINCTRL_GPIO_FUNC_PIO1) +#define PIO1_P11 RP2XXX_PINMUX(11, RP2_PINCTRL_GPIO_FUNC_PIO1) +#define PIO1_P12 RP2XXX_PINMUX(12, RP2_PINCTRL_GPIO_FUNC_PIO1) +#define PIO1_P13 RP2XXX_PINMUX(13, RP2_PINCTRL_GPIO_FUNC_PIO1) +#define PIO1_P14 RP2XXX_PINMUX(14, RP2_PINCTRL_GPIO_FUNC_PIO1) +#define PIO1_P15 RP2XXX_PINMUX(15, RP2_PINCTRL_GPIO_FUNC_PIO1) +#define PIO1_P16 RP2XXX_PINMUX(16, RP2_PINCTRL_GPIO_FUNC_PIO1) +#define PIO1_P17 RP2XXX_PINMUX(17, RP2_PINCTRL_GPIO_FUNC_PIO1) +#define PIO1_P18 RP2XXX_PINMUX(18, RP2_PINCTRL_GPIO_FUNC_PIO1) +#define PIO1_P19 RP2XXX_PINMUX(19, RP2_PINCTRL_GPIO_FUNC_PIO1) +#define PIO1_P20 RP2XXX_PINMUX(20, RP2_PINCTRL_GPIO_FUNC_PIO1) +#define PIO1_P21 RP2XXX_PINMUX(21, RP2_PINCTRL_GPIO_FUNC_PIO1) +#define PIO1_P22 RP2XXX_PINMUX(22, RP2_PINCTRL_GPIO_FUNC_PIO1) +#define PIO1_P23 RP2XXX_PINMUX(23, RP2_PINCTRL_GPIO_FUNC_PIO1) +#define PIO1_P24 RP2XXX_PINMUX(24, RP2_PINCTRL_GPIO_FUNC_PIO1) +#define PIO1_P25 RP2XXX_PINMUX(25, RP2_PINCTRL_GPIO_FUNC_PIO1) +#define PIO1_P26 RP2XXX_PINMUX(26, RP2_PINCTRL_GPIO_FUNC_PIO1) +#define PIO1_P27 RP2XXX_PINMUX(27, RP2_PINCTRL_GPIO_FUNC_PIO1) +#define PIO1_P28 RP2XXX_PINMUX(28, RP2_PINCTRL_GPIO_FUNC_PIO1) +#define PIO1_P29 RP2XXX_PINMUX(29, RP2_PINCTRL_GPIO_FUNC_PIO1) + +#define GPIN0_P20 RP2XXX_PINMUX(20, RP2_PINCTRL_GPIO_FUNC_GPCK) +#define GPIN1_P22 RP2XXX_PINMUX(22, RP2_PINCTRL_GPIO_FUNC_GPCK) +#define GPOUT0_P21 RP2XXX_PINMUX(21, RP2_PINCTRL_GPIO_FUNC_GPCK) +#define GPOUT1_P23 RP2XXX_PINMUX(23, RP2_PINCTRL_GPIO_FUNC_GPCK) +#define GPOUT2_P24 RP2XXX_PINMUX(24, RP2_PINCTRL_GPIO_FUNC_GPCK) +#define GPOUT3_P25 RP2XXX_PINMUX(25, RP2_PINCTRL_GPIO_FUNC_GPCK) + +#endif /* __RPI_PICO_PINCTRL_COMMON_H__ */ diff --git a/include/zephyr/dt-bindings/pinctrl/rpi-pico-rp2040-pinctrl.h b/include/zephyr/dt-bindings/pinctrl/rpi-pico-rp2040-pinctrl.h index afe7577d9915..43760aa16ad1 100644 --- a/include/zephyr/dt-bindings/pinctrl/rpi-pico-rp2040-pinctrl.h +++ b/include/zephyr/dt-bindings/pinctrl/rpi-pico-rp2040-pinctrl.h @@ -7,228 +7,16 @@ #ifndef __RP2040_PINCTRL_H__ #define __RP2040_PINCTRL_H__ -#define RP2_PINCTRL_GPIO_FUNC_XIP 0 -#define RP2_PINCTRL_GPIO_FUNC_SPI 1 -#define RP2_PINCTRL_GPIO_FUNC_UART 2 -#define RP2_PINCTRL_GPIO_FUNC_I2C 3 -#define RP2_PINCTRL_GPIO_FUNC_PWM 4 -#define RP2_PINCTRL_GPIO_FUNC_SIO 5 -#define RP2_PINCTRL_GPIO_FUNC_PIO0 6 -#define RP2_PINCTRL_GPIO_FUNC_PIO1 7 +#define RP2_PINCTRL_GPIO_FUNC_XIP 0 #define RP2_PINCTRL_GPIO_FUNC_GPCK 8 -#define RP2_PINCTRL_GPIO_FUNC_USB 9 +#define RP2_PINCTRL_GPIO_FUNC_USB 9 #define RP2_PINCTRL_GPIO_FUNC_NULL 0xf -#define RP2_ALT_FUNC_POS 0 -#define RP2_ALT_FUNC_MASK 0xf +#include "rpi-pico-pinctrl-common.h" -#define RP2_PIN_NUM_POS 4 -#define RP2_PIN_NUM_MASK 0x1f - -#define RP2_GPIO_OVERRIDE_NORMAL 0 -#define RP2_GPIO_OVERRIDE_INVERT 1 -#define RP2_GPIO_OVERRIDE_LOW 2 -#define RP2_GPIO_OVERRIDE_HIGH 3 - -#define RP2040_PINMUX(pin_num, alt_func) (pin_num << RP2_PIN_NUM_POS | \ - alt_func << RP2_ALT_FUNC_POS) - -#define UART0_TX_P0 RP2040_PINMUX(0, RP2_PINCTRL_GPIO_FUNC_UART) -#define UART0_RX_P1 RP2040_PINMUX(1, RP2_PINCTRL_GPIO_FUNC_UART) -#define UART0_CTS_P2 RP2040_PINMUX(2, RP2_PINCTRL_GPIO_FUNC_UART) -#define UART0_RTS_P3 RP2040_PINMUX(3, RP2_PINCTRL_GPIO_FUNC_UART) -#define UART1_TX_P4 RP2040_PINMUX(4, RP2_PINCTRL_GPIO_FUNC_UART) -#define UART1_RX_P5 RP2040_PINMUX(5, RP2_PINCTRL_GPIO_FUNC_UART) -#define UART1_CTS_P6 RP2040_PINMUX(6, RP2_PINCTRL_GPIO_FUNC_UART) -#define UART1_RTS_P7 RP2040_PINMUX(7, RP2_PINCTRL_GPIO_FUNC_UART) -#define UART1_TX_P8 RP2040_PINMUX(8, RP2_PINCTRL_GPIO_FUNC_UART) -#define UART1_RX_P9 RP2040_PINMUX(9, RP2_PINCTRL_GPIO_FUNC_UART) -#define UART1_CTS_P10 RP2040_PINMUX(10, RP2_PINCTRL_GPIO_FUNC_UART) -#define UART1_RTS_P11 RP2040_PINMUX(11, RP2_PINCTRL_GPIO_FUNC_UART) -#define UART0_TX_P12 RP2040_PINMUX(12, RP2_PINCTRL_GPIO_FUNC_UART) -#define UART0_RX_P13 RP2040_PINMUX(13, RP2_PINCTRL_GPIO_FUNC_UART) -#define UART0_CTS_P14 RP2040_PINMUX(14, RP2_PINCTRL_GPIO_FUNC_UART) -#define UART0_RTS_P15 RP2040_PINMUX(15, RP2_PINCTRL_GPIO_FUNC_UART) -#define UART0_TX_P16 RP2040_PINMUX(16, RP2_PINCTRL_GPIO_FUNC_UART) -#define UART0_RX_P17 RP2040_PINMUX(17, RP2_PINCTRL_GPIO_FUNC_UART) -#define UART0_CTS_P18 RP2040_PINMUX(18, RP2_PINCTRL_GPIO_FUNC_UART) -#define UART0_RTS_P19 RP2040_PINMUX(19, RP2_PINCTRL_GPIO_FUNC_UART) -#define UART1_TX_P20 RP2040_PINMUX(20, RP2_PINCTRL_GPIO_FUNC_UART) -#define UART1_RX_P21 RP2040_PINMUX(21, RP2_PINCTRL_GPIO_FUNC_UART) -#define UART1_CTS_P22 RP2040_PINMUX(22, RP2_PINCTRL_GPIO_FUNC_UART) -#define UART1_RTS_P23 RP2040_PINMUX(23, RP2_PINCTRL_GPIO_FUNC_UART) -#define UART1_TX_P24 RP2040_PINMUX(24, RP2_PINCTRL_GPIO_FUNC_UART) -#define UART1_RX_P25 RP2040_PINMUX(25, RP2_PINCTRL_GPIO_FUNC_UART) -#define UART1_CTS_P26 RP2040_PINMUX(26, RP2_PINCTRL_GPIO_FUNC_UART) -#define UART1_RTS_P27 RP2040_PINMUX(27, RP2_PINCTRL_GPIO_FUNC_UART) -#define UART0_TX_P28 RP2040_PINMUX(28, RP2_PINCTRL_GPIO_FUNC_UART) -#define UART0_RX_P29 RP2040_PINMUX(29, RP2_PINCTRL_GPIO_FUNC_UART) - -#define I2C0_SDA_P0 RP2040_PINMUX(0, RP2_PINCTRL_GPIO_FUNC_I2C) -#define I2C0_SCL_P1 RP2040_PINMUX(1, RP2_PINCTRL_GPIO_FUNC_I2C) -#define I2C1_SDA_P2 RP2040_PINMUX(2, RP2_PINCTRL_GPIO_FUNC_I2C) -#define I2C1_SCL_P3 RP2040_PINMUX(3, RP2_PINCTRL_GPIO_FUNC_I2C) -#define I2C0_SDA_P4 RP2040_PINMUX(4, RP2_PINCTRL_GPIO_FUNC_I2C) -#define I2C0_SCL_P5 RP2040_PINMUX(5, RP2_PINCTRL_GPIO_FUNC_I2C) -#define I2C1_SDA_P6 RP2040_PINMUX(6, RP2_PINCTRL_GPIO_FUNC_I2C) -#define I2C1_SCL_P7 RP2040_PINMUX(7, RP2_PINCTRL_GPIO_FUNC_I2C) -#define I2C0_SDA_P8 RP2040_PINMUX(8, RP2_PINCTRL_GPIO_FUNC_I2C) -#define I2C0_SCL_P9 RP2040_PINMUX(9, RP2_PINCTRL_GPIO_FUNC_I2C) -#define I2C1_SDA_P10 RP2040_PINMUX(10, RP2_PINCTRL_GPIO_FUNC_I2C) -#define I2C1_SCL_P11 RP2040_PINMUX(11, RP2_PINCTRL_GPIO_FUNC_I2C) -#define I2C0_SDA_P12 RP2040_PINMUX(12, RP2_PINCTRL_GPIO_FUNC_I2C) -#define I2C0_SCL_P13 RP2040_PINMUX(13, RP2_PINCTRL_GPIO_FUNC_I2C) -#define I2C1_SDA_P14 RP2040_PINMUX(14, RP2_PINCTRL_GPIO_FUNC_I2C) -#define I2C1_SCL_P15 RP2040_PINMUX(15, RP2_PINCTRL_GPIO_FUNC_I2C) -#define I2C0_SDA_P16 RP2040_PINMUX(16, RP2_PINCTRL_GPIO_FUNC_I2C) -#define I2C0_SCL_P17 RP2040_PINMUX(17, RP2_PINCTRL_GPIO_FUNC_I2C) -#define I2C1_SDA_P18 RP2040_PINMUX(18, RP2_PINCTRL_GPIO_FUNC_I2C) -#define I2C1_SCL_P19 RP2040_PINMUX(19, RP2_PINCTRL_GPIO_FUNC_I2C) -#define I2C0_SDA_P20 RP2040_PINMUX(20, RP2_PINCTRL_GPIO_FUNC_I2C) -#define I2C0_SCL_P21 RP2040_PINMUX(21, RP2_PINCTRL_GPIO_FUNC_I2C) -#define I2C1_SDA_P22 RP2040_PINMUX(22, RP2_PINCTRL_GPIO_FUNC_I2C) -#define I2C1_SCL_P23 RP2040_PINMUX(23, RP2_PINCTRL_GPIO_FUNC_I2C) -#define I2C0_SDA_P24 RP2040_PINMUX(24, RP2_PINCTRL_GPIO_FUNC_I2C) -#define I2C0_SCL_P25 RP2040_PINMUX(25, RP2_PINCTRL_GPIO_FUNC_I2C) -#define I2C1_SDA_P26 RP2040_PINMUX(26, RP2_PINCTRL_GPIO_FUNC_I2C) -#define I2C1_SCL_P27 RP2040_PINMUX(27, RP2_PINCTRL_GPIO_FUNC_I2C) -#define I2C0_SDA_P28 RP2040_PINMUX(28, RP2_PINCTRL_GPIO_FUNC_I2C) -#define I2C0_SCL_P29 RP2040_PINMUX(29, RP2_PINCTRL_GPIO_FUNC_I2C) - -#define PWM_0A_P0 RP2040_PINMUX(0, RP2_PINCTRL_GPIO_FUNC_PWM) -#define PWM_0B_P1 RP2040_PINMUX(1, RP2_PINCTRL_GPIO_FUNC_PWM) -#define PWM_1A_P2 RP2040_PINMUX(2, RP2_PINCTRL_GPIO_FUNC_PWM) -#define PWM_1B_P3 RP2040_PINMUX(3, RP2_PINCTRL_GPIO_FUNC_PWM) -#define PWM_2A_P4 RP2040_PINMUX(4, RP2_PINCTRL_GPIO_FUNC_PWM) -#define PWM_2B_P5 RP2040_PINMUX(5, RP2_PINCTRL_GPIO_FUNC_PWM) -#define PWM_3A_P6 RP2040_PINMUX(6, RP2_PINCTRL_GPIO_FUNC_PWM) -#define PWM_3B_P7 RP2040_PINMUX(7, RP2_PINCTRL_GPIO_FUNC_PWM) -#define PWM_4A_P8 RP2040_PINMUX(8, RP2_PINCTRL_GPIO_FUNC_PWM) -#define PWM_4B_P9 RP2040_PINMUX(9, RP2_PINCTRL_GPIO_FUNC_PWM) -#define PWM_5A_P10 RP2040_PINMUX(10, RP2_PINCTRL_GPIO_FUNC_PWM) -#define PWM_5B_P11 RP2040_PINMUX(11, RP2_PINCTRL_GPIO_FUNC_PWM) -#define PWM_6A_P12 RP2040_PINMUX(12, RP2_PINCTRL_GPIO_FUNC_PWM) -#define PWM_6B_P13 RP2040_PINMUX(13, RP2_PINCTRL_GPIO_FUNC_PWM) -#define PWM_7A_P14 RP2040_PINMUX(14, RP2_PINCTRL_GPIO_FUNC_PWM) -#define PWM_7B_P15 RP2040_PINMUX(15, RP2_PINCTRL_GPIO_FUNC_PWM) -#define PWM_0A_P16 RP2040_PINMUX(16, RP2_PINCTRL_GPIO_FUNC_PWM) -#define PWM_0B_P17 RP2040_PINMUX(17, RP2_PINCTRL_GPIO_FUNC_PWM) -#define PWM_1A_P18 RP2040_PINMUX(18, RP2_PINCTRL_GPIO_FUNC_PWM) -#define PWM_1B_P19 RP2040_PINMUX(19, RP2_PINCTRL_GPIO_FUNC_PWM) -#define PWM_2A_P20 RP2040_PINMUX(20, RP2_PINCTRL_GPIO_FUNC_PWM) -#define PWM_2B_P21 RP2040_PINMUX(21, RP2_PINCTRL_GPIO_FUNC_PWM) -#define PWM_3A_P22 RP2040_PINMUX(22, RP2_PINCTRL_GPIO_FUNC_PWM) -#define PWM_3B_P22 RP2040_PINMUX(23, RP2_PINCTRL_GPIO_FUNC_PWM) -#define PWM_4A_P24 RP2040_PINMUX(24, RP2_PINCTRL_GPIO_FUNC_PWM) -#define PWM_4B_P25 RP2040_PINMUX(25, RP2_PINCTRL_GPIO_FUNC_PWM) -#define PWM_5A_P26 RP2040_PINMUX(26, RP2_PINCTRL_GPIO_FUNC_PWM) -#define PWM_5B_P27 RP2040_PINMUX(27, RP2_PINCTRL_GPIO_FUNC_PWM) -#define PWM_6A_P28 RP2040_PINMUX(28, RP2_PINCTRL_GPIO_FUNC_PWM) -#define PWM_6B_P29 RP2040_PINMUX(29, RP2_PINCTRL_GPIO_FUNC_PWM) - -#define SPI0_RX_P0 RP2040_PINMUX(0, RP2_PINCTRL_GPIO_FUNC_SPI) -#define SPI0_CSN_P1 RP2040_PINMUX(1, RP2_PINCTRL_GPIO_FUNC_SPI) -#define SPI0_SCK_P2 RP2040_PINMUX(2, RP2_PINCTRL_GPIO_FUNC_SPI) -#define SPI0_TX_P3 RP2040_PINMUX(3, RP2_PINCTRL_GPIO_FUNC_SPI) -#define SPI0_RX_P4 RP2040_PINMUX(4, RP2_PINCTRL_GPIO_FUNC_SPI) -#define SPI0_CSN_P5 RP2040_PINMUX(5, RP2_PINCTRL_GPIO_FUNC_SPI) -#define SPI0_SCK_P6 RP2040_PINMUX(6, RP2_PINCTRL_GPIO_FUNC_SPI) -#define SPI0_TX_P7 RP2040_PINMUX(7, RP2_PINCTRL_GPIO_FUNC_SPI) -#define SPI1_RX_P8 RP2040_PINMUX(8, RP2_PINCTRL_GPIO_FUNC_SPI) -#define SPI1_CSN_P9 RP2040_PINMUX(9, RP2_PINCTRL_GPIO_FUNC_SPI) -#define SPI1_SCK_P10 RP2040_PINMUX(10, RP2_PINCTRL_GPIO_FUNC_SPI) -#define SPI1_TX_P11 RP2040_PINMUX(11, RP2_PINCTRL_GPIO_FUNC_SPI) -#define SPI1_RX_P12 RP2040_PINMUX(12, RP2_PINCTRL_GPIO_FUNC_SPI) -#define SPI1_CSN_P13 RP2040_PINMUX(13, RP2_PINCTRL_GPIO_FUNC_SPI) -#define SPI1_SCK_P14 RP2040_PINMUX(14, RP2_PINCTRL_GPIO_FUNC_SPI) -#define SPI1_TX_P15 RP2040_PINMUX(15, RP2_PINCTRL_GPIO_FUNC_SPI) -#define SPI0_RX_P16 RP2040_PINMUX(16, RP2_PINCTRL_GPIO_FUNC_SPI) -#define SPI0_CSN_P17 RP2040_PINMUX(17, RP2_PINCTRL_GPIO_FUNC_SPI) -#define SPI0_SCK_P18 RP2040_PINMUX(18, RP2_PINCTRL_GPIO_FUNC_SPI) -#define SPI0_TX_P19 RP2040_PINMUX(19, RP2_PINCTRL_GPIO_FUNC_SPI) -#define SPI0_RX_P20 RP2040_PINMUX(20, RP2_PINCTRL_GPIO_FUNC_SPI) -#define SPI0_CSN_P21 RP2040_PINMUX(21, RP2_PINCTRL_GPIO_FUNC_SPI) -#define SPI0_SCK_P22 RP2040_PINMUX(22, RP2_PINCTRL_GPIO_FUNC_SPI) -#define SPI0_TX_P23 RP2040_PINMUX(23, RP2_PINCTRL_GPIO_FUNC_SPI) -#define SPI1_RX_P24 RP2040_PINMUX(24, RP2_PINCTRL_GPIO_FUNC_SPI) -#define SPI1_CSN_P25 RP2040_PINMUX(25, RP2_PINCTRL_GPIO_FUNC_SPI) -#define SPI1_SCK_P26 RP2040_PINMUX(26, RP2_PINCTRL_GPIO_FUNC_SPI) -#define SPI1_TX_P27 RP2040_PINMUX(27, RP2_PINCTRL_GPIO_FUNC_SPI) -#define SPI1_RX_P28 RP2040_PINMUX(28, RP2_PINCTRL_GPIO_FUNC_SPI) -#define SPI1_CSN_P29 RP2040_PINMUX(29, RP2_PINCTRL_GPIO_FUNC_SPI) - -#define ADC_CH0_P26 RP2040_PINMUX(26, RP2_PINCTRL_GPIO_FUNC_NULL) -#define ADC_CH1_P27 RP2040_PINMUX(27, RP2_PINCTRL_GPIO_FUNC_NULL) -#define ADC_CH2_P28 RP2040_PINMUX(28, RP2_PINCTRL_GPIO_FUNC_NULL) -#define ADC_CH3_P29 RP2040_PINMUX(29, RP2_PINCTRL_GPIO_FUNC_NULL) - -#define PIO0_P0 RP2040_PINMUX(0, RP2_PINCTRL_GPIO_FUNC_PIO0) -#define PIO0_P1 RP2040_PINMUX(1, RP2_PINCTRL_GPIO_FUNC_PIO0) -#define PIO0_P2 RP2040_PINMUX(2, RP2_PINCTRL_GPIO_FUNC_PIO0) -#define PIO0_P3 RP2040_PINMUX(3, RP2_PINCTRL_GPIO_FUNC_PIO0) -#define PIO0_P4 RP2040_PINMUX(4, RP2_PINCTRL_GPIO_FUNC_PIO0) -#define PIO0_P5 RP2040_PINMUX(5, RP2_PINCTRL_GPIO_FUNC_PIO0) -#define PIO0_P6 RP2040_PINMUX(6, RP2_PINCTRL_GPIO_FUNC_PIO0) -#define PIO0_P7 RP2040_PINMUX(7, RP2_PINCTRL_GPIO_FUNC_PIO0) -#define PIO0_P8 RP2040_PINMUX(8, RP2_PINCTRL_GPIO_FUNC_PIO0) -#define PIO0_P9 RP2040_PINMUX(9, RP2_PINCTRL_GPIO_FUNC_PIO0) -#define PIO0_P10 RP2040_PINMUX(10, RP2_PINCTRL_GPIO_FUNC_PIO0) -#define PIO0_P11 RP2040_PINMUX(11, RP2_PINCTRL_GPIO_FUNC_PIO0) -#define PIO0_P12 RP2040_PINMUX(12, RP2_PINCTRL_GPIO_FUNC_PIO0) -#define PIO0_P13 RP2040_PINMUX(13, RP2_PINCTRL_GPIO_FUNC_PIO0) -#define PIO0_P14 RP2040_PINMUX(14, RP2_PINCTRL_GPIO_FUNC_PIO0) -#define PIO0_P15 RP2040_PINMUX(15, RP2_PINCTRL_GPIO_FUNC_PIO0) -#define PIO0_P16 RP2040_PINMUX(16, RP2_PINCTRL_GPIO_FUNC_PIO0) -#define PIO0_P17 RP2040_PINMUX(17, RP2_PINCTRL_GPIO_FUNC_PIO0) -#define PIO0_P18 RP2040_PINMUX(18, RP2_PINCTRL_GPIO_FUNC_PIO0) -#define PIO0_P19 RP2040_PINMUX(19, RP2_PINCTRL_GPIO_FUNC_PIO0) -#define PIO0_P20 RP2040_PINMUX(20, RP2_PINCTRL_GPIO_FUNC_PIO0) -#define PIO0_P21 RP2040_PINMUX(21, RP2_PINCTRL_GPIO_FUNC_PIO0) -#define PIO0_P22 RP2040_PINMUX(22, RP2_PINCTRL_GPIO_FUNC_PIO0) -#define PIO0_P23 RP2040_PINMUX(23, RP2_PINCTRL_GPIO_FUNC_PIO0) -#define PIO0_P24 RP2040_PINMUX(24, RP2_PINCTRL_GPIO_FUNC_PIO0) -#define PIO0_P25 RP2040_PINMUX(25, RP2_PINCTRL_GPIO_FUNC_PIO0) -#define PIO0_P26 RP2040_PINMUX(26, RP2_PINCTRL_GPIO_FUNC_PIO0) -#define PIO0_P27 RP2040_PINMUX(27, RP2_PINCTRL_GPIO_FUNC_PIO0) -#define PIO0_P28 RP2040_PINMUX(28, RP2_PINCTRL_GPIO_FUNC_PIO0) -#define PIO0_P29 RP2040_PINMUX(29, RP2_PINCTRL_GPIO_FUNC_PIO0) - -#define PIO1_P0 RP2040_PINMUX(0, RP2_PINCTRL_GPIO_FUNC_PIO1) -#define PIO1_P1 RP2040_PINMUX(1, RP2_PINCTRL_GPIO_FUNC_PIO1) -#define PIO1_P2 RP2040_PINMUX(2, RP2_PINCTRL_GPIO_FUNC_PIO1) -#define PIO1_P3 RP2040_PINMUX(3, RP2_PINCTRL_GPIO_FUNC_PIO1) -#define PIO1_P4 RP2040_PINMUX(4, RP2_PINCTRL_GPIO_FUNC_PIO1) -#define PIO1_P5 RP2040_PINMUX(5, RP2_PINCTRL_GPIO_FUNC_PIO1) -#define PIO1_P6 RP2040_PINMUX(6, RP2_PINCTRL_GPIO_FUNC_PIO1) -#define PIO1_P7 RP2040_PINMUX(7, RP2_PINCTRL_GPIO_FUNC_PIO1) -#define PIO1_P8 RP2040_PINMUX(8, RP2_PINCTRL_GPIO_FUNC_PIO1) -#define PIO1_P9 RP2040_PINMUX(9, RP2_PINCTRL_GPIO_FUNC_PIO1) -#define PIO1_P10 RP2040_PINMUX(10, RP2_PINCTRL_GPIO_FUNC_PIO1) -#define PIO1_P11 RP2040_PINMUX(11, RP2_PINCTRL_GPIO_FUNC_PIO1) -#define PIO1_P12 RP2040_PINMUX(12, RP2_PINCTRL_GPIO_FUNC_PIO1) -#define PIO1_P13 RP2040_PINMUX(13, RP2_PINCTRL_GPIO_FUNC_PIO1) -#define PIO1_P14 RP2040_PINMUX(14, RP2_PINCTRL_GPIO_FUNC_PIO1) -#define PIO1_P15 RP2040_PINMUX(15, RP2_PINCTRL_GPIO_FUNC_PIO1) -#define PIO1_P16 RP2040_PINMUX(16, RP2_PINCTRL_GPIO_FUNC_PIO1) -#define PIO1_P17 RP2040_PINMUX(17, RP2_PINCTRL_GPIO_FUNC_PIO1) -#define PIO1_P18 RP2040_PINMUX(18, RP2_PINCTRL_GPIO_FUNC_PIO1) -#define PIO1_P19 RP2040_PINMUX(19, RP2_PINCTRL_GPIO_FUNC_PIO1) -#define PIO1_P20 RP2040_PINMUX(20, RP2_PINCTRL_GPIO_FUNC_PIO1) -#define PIO1_P21 RP2040_PINMUX(21, RP2_PINCTRL_GPIO_FUNC_PIO1) -#define PIO1_P22 RP2040_PINMUX(22, RP2_PINCTRL_GPIO_FUNC_PIO1) -#define PIO1_P23 RP2040_PINMUX(23, RP2_PINCTRL_GPIO_FUNC_PIO1) -#define PIO1_P24 RP2040_PINMUX(24, RP2_PINCTRL_GPIO_FUNC_PIO1) -#define PIO1_P25 RP2040_PINMUX(25, RP2_PINCTRL_GPIO_FUNC_PIO1) -#define PIO1_P26 RP2040_PINMUX(26, RP2_PINCTRL_GPIO_FUNC_PIO1) -#define PIO1_P27 RP2040_PINMUX(27, RP2_PINCTRL_GPIO_FUNC_PIO1) -#define PIO1_P28 RP2040_PINMUX(28, RP2_PINCTRL_GPIO_FUNC_PIO1) -#define PIO1_P29 RP2040_PINMUX(29, RP2_PINCTRL_GPIO_FUNC_PIO1) - -#define GPIN0_P20 RP2040_PINMUX(20, RP2_PINCTRL_GPIO_FUNC_GPCK) -#define GPIN1_P22 RP2040_PINMUX(22, RP2_PINCTRL_GPIO_FUNC_GPCK) -#define GPOUT0_P21 RP2040_PINMUX(21, RP2_PINCTRL_GPIO_FUNC_GPCK) -#define GPOUT1_P23 RP2040_PINMUX(23, RP2_PINCTRL_GPIO_FUNC_GPCK) -#define GPOUT2_P24 RP2040_PINMUX(24, RP2_PINCTRL_GPIO_FUNC_GPCK) -#define GPOUT3_P25 RP2040_PINMUX(25, RP2_PINCTRL_GPIO_FUNC_GPCK) +#define ADC_CH0_P26 RP2XXX_PINMUX(26, RP2_PINCTRL_GPIO_FUNC_NULL) +#define ADC_CH1_P27 RP2XXX_PINMUX(27, RP2_PINCTRL_GPIO_FUNC_NULL) +#define ADC_CH2_P28 RP2XXX_PINMUX(28, RP2_PINCTRL_GPIO_FUNC_NULL) +#define ADC_CH3_P29 RP2XXX_PINMUX(29, RP2_PINCTRL_GPIO_FUNC_NULL) #endif /* __RP2040_PINCTRL_H__ */ diff --git a/include/zephyr/dt-bindings/pinctrl/rpi-pico-rp2350-pinctrl-common.h b/include/zephyr/dt-bindings/pinctrl/rpi-pico-rp2350-pinctrl-common.h new file mode 100644 index 000000000000..6d0878842c21 --- /dev/null +++ b/include/zephyr/dt-bindings/pinctrl/rpi-pico-rp2350-pinctrl-common.h @@ -0,0 +1,71 @@ +/* + * Copyright (c) 2024, Andrew Featherstone + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef __RP2350_PINCTRL_COMMON_H__ +#define __RP2350_PINCTRL_COMMON_H__ + +#define RP2_PINCTRL_GPIO_FUNC_HSTX 0 + +#define RP2_PINCTRL_GPIO_FUNC_PIO2 8 +#define RP2_PINCTRL_GPIO_FUNC_GPCK 9 +#define RP2_PINCTRL_GPIO_FUNC_USB 10 +#define RP2_PINCTRL_GPIO_FUNC_UART_AUX 11 +#define RP2_PINCTRL_GPIO_FUNC_NULL 0x1f + +#include "rpi-pico-pinctrl-common.h" + +#define PIO2_P0 RP2XXX_PINMUX(0, RP2_PINCTRL_GPIO_FUNC_PIO2) +#define PIO2_P1 RP2XXX_PINMUX(1, RP2_PINCTRL_GPIO_FUNC_PIO2) +#define PIO2_P2 RP2XXX_PINMUX(2, RP2_PINCTRL_GPIO_FUNC_PIO2) +#define PIO2_P3 RP2XXX_PINMUX(3, RP2_PINCTRL_GPIO_FUNC_PIO2) +#define PIO2_P4 RP2XXX_PINMUX(4, RP2_PINCTRL_GPIO_FUNC_PIO2) +#define PIO2_P5 RP2XXX_PINMUX(5, RP2_PINCTRL_GPIO_FUNC_PIO2) +#define PIO2_P6 RP2XXX_PINMUX(6, RP2_PINCTRL_GPIO_FUNC_PIO2) +#define PIO2_P7 RP2XXX_PINMUX(7, RP2_PINCTRL_GPIO_FUNC_PIO2) +#define PIO2_P8 RP2XXX_PINMUX(8, RP2_PINCTRL_GPIO_FUNC_PIO2) +#define PIO2_P9 RP2XXX_PINMUX(9, RP2_PINCTRL_GPIO_FUNC_PIO2) +#define PIO2_P10 RP2XXX_PINMUX(10, RP2_PINCTRL_GPIO_FUNC_PIO2) +#define PIO2_P11 RP2XXX_PINMUX(11, RP2_PINCTRL_GPIO_FUNC_PIO2) +#define PIO2_P12 RP2XXX_PINMUX(12, RP2_PINCTRL_GPIO_FUNC_PIO2) +#define PIO2_P13 RP2XXX_PINMUX(13, RP2_PINCTRL_GPIO_FUNC_PIO2) +#define PIO2_P14 RP2XXX_PINMUX(14, RP2_PINCTRL_GPIO_FUNC_PIO2) +#define PIO2_P15 RP2XXX_PINMUX(15, RP2_PINCTRL_GPIO_FUNC_PIO2) +#define PIO2_P16 RP2XXX_PINMUX(16, RP2_PINCTRL_GPIO_FUNC_PIO2) +#define PIO2_P17 RP2XXX_PINMUX(17, RP2_PINCTRL_GPIO_FUNC_PIO2) +#define PIO2_P18 RP2XXX_PINMUX(18, RP2_PINCTRL_GPIO_FUNC_PIO2) +#define PIO2_P19 RP2XXX_PINMUX(19, RP2_PINCTRL_GPIO_FUNC_PIO2) +#define PIO2_P20 RP2XXX_PINMUX(20, RP2_PINCTRL_GPIO_FUNC_PIO2) +#define PIO2_P21 RP2XXX_PINMUX(21, RP2_PINCTRL_GPIO_FUNC_PIO2) +#define PIO2_P22 RP2XXX_PINMUX(22, RP2_PINCTRL_GPIO_FUNC_PIO2) +#define PIO2_P23 RP2XXX_PINMUX(23, RP2_PINCTRL_GPIO_FUNC_PIO2) +#define PIO2_P24 RP2XXX_PINMUX(24, RP2_PINCTRL_GPIO_FUNC_PIO2) +#define PIO2_P25 RP2XXX_PINMUX(25, RP2_PINCTRL_GPIO_FUNC_PIO2) +#define PIO2_P26 RP2XXX_PINMUX(26, RP2_PINCTRL_GPIO_FUNC_PIO2) +#define PIO2_P27 RP2XXX_PINMUX(27, RP2_PINCTRL_GPIO_FUNC_PIO2) +#define PIO2_P28 RP2XXX_PINMUX(28, RP2_PINCTRL_GPIO_FUNC_PIO2) +#define PIO2_P29 RP2XXX_PINMUX(29, RP2_PINCTRL_GPIO_FUNC_PIO2) + +#define GPIN0_P12 RP2XXX_PINMUX(20, RP2_PINCTRL_GPIO_FUNC_GPCK) +#define GPIN1_P14 RP2XXX_PINMUX(22, RP2_PINCTRL_GPIO_FUNC_GPCK) +#define GPOUT0_P13 RP2XXX_PINMUX(21, RP2_PINCTRL_GPIO_FUNC_GPCK) +#define GPOUT1_P15 RP2XXX_PINMUX(23, RP2_PINCTRL_GPIO_FUNC_GPCK) + +#define UART0_TX_P2 RP2XXX_PINMUX(2, RP2_PINCTRL_GPIO_FUNC_UART_ALT) +#define UART0_RX_P3 RP2XXX_PINMUX(3, RP2_PINCTRL_GPIO_FUNC_UART_ALT) +#define UART1_TX_P6 RP2XXX_PINMUX(6, RP2_PINCTRL_GPIO_FUNC_UART_ALT) +#define UART1_RX_P7 RP2XXX_PINMUX(7, RP2_PINCTRL_GPIO_FUNC_UART_ALT) +#define UART1_TX_P10 RP2XXX_PINMUX(10, RP2_PINCTRL_GPIO_FUNC_UART_ALT) +#define UART1_RX_P11 RP2XXX_PINMUX(11, RP2_PINCTRL_GPIO_FUNC_UART_ALT) +#define UART0_TX_P14 RP2XXX_PINMUX(14, RP2_PINCTRL_GPIO_FUNC_UART_ALT) +#define UART0_RX_P15 RP2XXX_PINMUX(15, RP2_PINCTRL_GPIO_FUNC_UART_ALT) +#define UART0_TX_P18 RP2XXX_PINMUX(18, RP2_PINCTRL_GPIO_FUNC_UART_ALT) +#define UART0_RX_P19 RP2XXX_PINMUX(19, RP2_PINCTRL_GPIO_FUNC_UART_ALT) +#define UART1_TX_P22 RP2XXX_PINMUX(22, RP2_PINCTRL_GPIO_FUNC_UART_ALT) +#define UART1_RX_P23 RP2XXX_PINMUX(23, RP2_PINCTRL_GPIO_FUNC_UART_ALT) +#define UART1_TX_P26 RP2XXX_PINMUX(26, RP2_PINCTRL_GPIO_FUNC_UART_ALT) +#define UART1_RX_P27 RP2XXX_PINMUX(27, RP2_PINCTRL_GPIO_FUNC_UART_ALT) + +#endif /* __RP2350_PINCTRL_COMMON_H__ */ diff --git a/include/zephyr/dt-bindings/pinctrl/rpi-pico-rp2350a-pinctrl.h b/include/zephyr/dt-bindings/pinctrl/rpi-pico-rp2350a-pinctrl.h new file mode 100644 index 000000000000..2603432de2ec --- /dev/null +++ b/include/zephyr/dt-bindings/pinctrl/rpi-pico-rp2350a-pinctrl.h @@ -0,0 +1,20 @@ +/* + * Copyright (c) 2024, Andrew Featherstone + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef __RP2350A_PINCTRL_H__ +#define __RP2350A_PINCTRL_H__ + +#include "rpi-pico-rp2350-pinctrl-common.h" + +/* ADC channel allocations differ between the RP2350A and RP2350B. + * Refer to Table 1115 in the datasheet. + */ +#define ADC_CH0_P26 RP2XXX_PINMUX(26, RP2_PINCTRL_GPIO_FUNC_NULL) +#define ADC_CH1_P27 RP2XXX_PINMUX(27, RP2_PINCTRL_GPIO_FUNC_NULL) +#define ADC_CH2_P28 RP2XXX_PINMUX(28, RP2_PINCTRL_GPIO_FUNC_NULL) +#define ADC_CH3_P29 RP2XXX_PINMUX(29, RP2_PINCTRL_GPIO_FUNC_NULL) + +#endif /* __RP2350A_PINCTRL_H__ */ diff --git a/include/zephyr/dt-bindings/pinctrl/rpi-pico-rp2350b-pinctrl.h b/include/zephyr/dt-bindings/pinctrl/rpi-pico-rp2350b-pinctrl.h new file mode 100644 index 000000000000..04d4f6a99177 --- /dev/null +++ b/include/zephyr/dt-bindings/pinctrl/rpi-pico-rp2350b-pinctrl.h @@ -0,0 +1,182 @@ +/* + * Copyright (c) 2024, Andrew Featherstone + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef __RP2350B_PINCTRL_H__ +#define __RP2350B_PINCTRL_H__ + +#include "rpi-pico-rp2350-pinctrl-common.h" + +/* RP2350B is in a QFN-80 package, and extends the set of available pins + * accordingly. + */ +#define SPI1_SCK_P30 RP2XXX_PINMUX(30, RP2_PINCTRL_GPIO_FUNC_SPI) +#define SPI1_TX_P31 RP2XXX_PINMUX(31, RP2_PINCTRL_GPIO_FUNC_SPI) +#define SPI0_RX_P32 RP2XXX_PINMUX(32, RP2_PINCTRL_GPIO_FUNC_SPI) +#define SPI0_CSN_P33 RP2XXX_PINMUX(33, RP2_PINCTRL_GPIO_FUNC_SPI) +#define SPI0_SCK_P34 RP2XXX_PINMUX(34, RP2_PINCTRL_GPIO_FUNC_SPI) +#define SPI0_TX_P35 RP2XXX_PINMUX(35, RP2_PINCTRL_GPIO_FUNC_SPI) +#define SPI0_RX_P36 RP2XXX_PINMUX(36, RP2_PINCTRL_GPIO_FUNC_SPI) +#define SPI0_CSN_P37 RP2XXX_PINMUX(37, RP2_PINCTRL_GPIO_FUNC_SPI) +#define SPI0_SCK_P38 RP2XXX_PINMUX(38, RP2_PINCTRL_GPIO_FUNC_SPI) +#define SPI0_TX_P39 RP2XXX_PINMUX(39, RP2_PINCTRL_GPIO_FUNC_SPI) +#define SPI1_RX_P40 RP2XXX_PINMUX(40, RP2_PINCTRL_GPIO_FUNC_SPI) +#define SPI1_CSN_P41 RP2XXX_PINMUX(41, RP2_PINCTRL_GPIO_FUNC_SPI) +#define SPI1_SCK_P42 RP2XXX_PINMUX(42, RP2_PINCTRL_GPIO_FUNC_SPI) +#define SPI1_TX_P43 RP2XXX_PINMUX(43, RP2_PINCTRL_GPIO_FUNC_SPI) +#define SPI1_RX_P44 RP2XXX_PINMUX(44, RP2_PINCTRL_GPIO_FUNC_SPI) +#define SPI1_CSN_P45 RP2XXX_PINMUX(45, RP2_PINCTRL_GPIO_FUNC_SPI) +#define SPI1_SCK_P46 RP2XXX_PINMUX(46, RP2_PINCTRL_GPIO_FUNC_SPI) +#define SPI1_TX_P47 RP2XXX_PINMUX(47, RP2_PINCTRL_GPIO_FUNC_SPI) + +#define UART1_TX_P30 RP2XXX_PINMUX(30, RP2_PINCTRL_GPIO_FUNC_UART) +#define UART1_RX_P31 RP2XXX_PINMUX(31, RP2_PINCTRL_GPIO_FUNC_UART) +#define UART0_TX_P32 RP2XXX_PINMUX(32, RP2_PINCTRL_GPIO_FUNC_UART) +#define UART0_RX_P33 RP2XXX_PINMUX(33, RP2_PINCTRL_GPIO_FUNC_UART) +#define UART1_TX_P34 RP2XXX_PINMUX(34, RP2_PINCTRL_GPIO_FUNC_UART) +#define UART1_RX_P35 RP2XXX_PINMUX(35, RP2_PINCTRL_GPIO_FUNC_UART) +#define UART0_TX_P36 RP2XXX_PINMUX(36, RP2_PINCTRL_GPIO_FUNC_UART) +#define UART0_RX_P37 RP2XXX_PINMUX(37, RP2_PINCTRL_GPIO_FUNC_UART) +#define UART1_TX_P38 RP2XXX_PINMUX(38, RP2_PINCTRL_GPIO_FUNC_UART) +#define UART1_RX_P39 RP2XXX_PINMUX(39, RP2_PINCTRL_GPIO_FUNC_UART) +#define UART0_TX_P40 RP2XXX_PINMUX(40, RP2_PINCTRL_GPIO_FUNC_UART) +#define UART0_RX_P41 RP2XXX_PINMUX(41, RP2_PINCTRL_GPIO_FUNC_UART) +#define UART1_TX_P42 RP2XXX_PINMUX(42, RP2_PINCTRL_GPIO_FUNC_UART) +#define UART1_RX_P43 RP2XXX_PINMUX(43, RP2_PINCTRL_GPIO_FUNC_UART) +#define UART0_TX_P44 RP2XXX_PINMUX(44, RP2_PINCTRL_GPIO_FUNC_UART) +#define UART0_RX_P45 RP2XXX_PINMUX(45, RP2_PINCTRL_GPIO_FUNC_UART) +#define UART1_TX_P46 RP2XXX_PINMUX(46, RP2_PINCTRL_GPIO_FUNC_UART) +#define UART1_RX_P47 RP2XXX_PINMUX(47, RP2_PINCTRL_GPIO_FUNC_UART) + +#define I2C1_SDA_P30 RP2XXX_PINMUX(30, RP2_PINCTRL_GPIO_FUNC_I2C) +#define I2C1_SCL_P31 RP2XXX_PINMUX(31, RP2_PINCTRL_GPIO_FUNC_I2C) +#define I2C0_SDA_P32 RP2XXX_PINMUX(32, RP2_PINCTRL_GPIO_FUNC_I2C) +#define I2C0_SCL_P33 RP2XXX_PINMUX(33, RP2_PINCTRL_GPIO_FUNC_I2C) +#define I2C1_SDA_P34 RP2XXX_PINMUX(34, RP2_PINCTRL_GPIO_FUNC_I2C) +#define I2C1_SCL_P35 RP2XXX_PINMUX(35, RP2_PINCTRL_GPIO_FUNC_I2C) +#define I2C0_SDA_P36 RP2XXX_PINMUX(36, RP2_PINCTRL_GPIO_FUNC_I2C) +#define I2C0_SCL_P37 RP2XXX_PINMUX(37, RP2_PINCTRL_GPIO_FUNC_I2C) +#define I2C1_SDA_P38 RP2XXX_PINMUX(38, RP2_PINCTRL_GPIO_FUNC_I2C) +#define I2C1_SCL_P39 RP2XXX_PINMUX(39, RP2_PINCTRL_GPIO_FUNC_I2C) +#define I2C0_SDA_P40 RP2XXX_PINMUX(40, RP2_PINCTRL_GPIO_FUNC_I2C) +#define I2C0_SCL_P41 RP2XXX_PINMUX(41, RP2_PINCTRL_GPIO_FUNC_I2C) +#define I2C1_SDA_P42 RP2XXX_PINMUX(42, RP2_PINCTRL_GPIO_FUNC_I2C) +#define I2C1_SCL_P43 RP2XXX_PINMUX(43, RP2_PINCTRL_GPIO_FUNC_I2C) +#define I2C0_SDA_P44 RP2XXX_PINMUX(44, RP2_PINCTRL_GPIO_FUNC_I2C) +#define I2C0_SCL_P45 RP2XXX_PINMUX(45, RP2_PINCTRL_GPIO_FUNC_I2C) +#define I2C1_SDA_P46 RP2XXX_PINMUX(46, RP2_PINCTRL_GPIO_FUNC_I2C) +#define I2C1_SCL_P47 RP2XXX_PINMUX(47, RP2_PINCTRL_GPIO_FUNC_I2C) + +#define PWM_7A_P30 RP2XXX_PINMUX(30, RP2_PINCTRL_GPIO_FUNC_PWM) +#define PWM_7B_P31 RP2XXX_PINMUX(31, RP2_PINCTRL_GPIO_FUNC_PWM) +#define PWM_8A_P32 RP2XXX_PINMUX(32, RP2_PINCTRL_GPIO_FUNC_PWM) +#define PWM_8B_P33 RP2XXX_PINMUX(33, RP2_PINCTRL_GPIO_FUNC_PWM) +#define PWM_9A_P34 RP2XXX_PINMUX(34, RP2_PINCTRL_GPIO_FUNC_PWM) +#define PWM_9B_P35 RP2XXX_PINMUX(35, RP2_PINCTRL_GPIO_FUNC_PWM) +#define PWM_10A_P36 RP2XXX_PINMUX(36, RP2_PINCTRL_GPIO_FUNC_PWM) +#define PWM_10B_P37 RP2XXX_PINMUX(37, RP2_PINCTRL_GPIO_FUNC_PWM) +#define PWM_11A_P38 RP2XXX_PINMUX(38, RP2_PINCTRL_GPIO_FUNC_PWM) +#define PWM_11B_P39 RP2XXX_PINMUX(39, RP2_PINCTRL_GPIO_FUNC_PWM) +#define PWM_12A_P40 RP2XXX_PINMUX(40, RP2_PINCTRL_GPIO_FUNC_PWM) +#define PWM_12B_P41 RP2XXX_PINMUX(41, RP2_PINCTRL_GPIO_FUNC_PWM) +#define PWM_13A_P42 RP2XXX_PINMUX(42, RP2_PINCTRL_GPIO_FUNC_PWM) +#define PWM_13B_P43 RP2XXX_PINMUX(43, RP2_PINCTRL_GPIO_FUNC_PWM) +#define PWM_14A_P44 RP2XXX_PINMUX(44, RP2_PINCTRL_GPIO_FUNC_PWM) +#define PWM_14B_P45 RP2XXX_PINMUX(45, RP2_PINCTRL_GPIO_FUNC_PWM) +#define PWM_15A_P46 RP2XXX_PINMUX(46, RP2_PINCTRL_GPIO_FUNC_PWM) +#define PWM_15B_P47 RP2XXX_PINMUX(47, RP2_PINCTRL_GPIO_FUNC_PWM) + +#define PIO0_P30 RP2XXX_PINMUX(30, RP2_PINCTRL_GPIO_FUNC_PIO0) +#define PIO0_P31 RP2XXX_PINMUX(31, RP2_PINCTRL_GPIO_FUNC_PIO0) +#define PIO0_P32 RP2XXX_PINMUX(32, RP2_PINCTRL_GPIO_FUNC_PIO0) +#define PIO0_P33 RP2XXX_PINMUX(33, RP2_PINCTRL_GPIO_FUNC_PIO0) +#define PIO0_P34 RP2XXX_PINMUX(34, RP2_PINCTRL_GPIO_FUNC_PIO0) +#define PIO0_P35 RP2XXX_PINMUX(35, RP2_PINCTRL_GPIO_FUNC_PIO0) +#define PIO0_P36 RP2XXX_PINMUX(36, RP2_PINCTRL_GPIO_FUNC_PIO0) +#define PIO0_P37 RP2XXX_PINMUX(37, RP2_PINCTRL_GPIO_FUNC_PIO0) +#define PIO0_P38 RP2XXX_PINMUX(38, RP2_PINCTRL_GPIO_FUNC_PIO0) +#define PIO0_P39 RP2XXX_PINMUX(39, RP2_PINCTRL_GPIO_FUNC_PIO0) +#define PIO0_P40 RP2XXX_PINMUX(40, RP2_PINCTRL_GPIO_FUNC_PIO0) +#define PIO0_P41 RP2XXX_PINMUX(41, RP2_PINCTRL_GPIO_FUNC_PIO0) +#define PIO0_P42 RP2XXX_PINMUX(42, RP2_PINCTRL_GPIO_FUNC_PIO0) +#define PIO0_P43 RP2XXX_PINMUX(43, RP2_PINCTRL_GPIO_FUNC_PIO0) +#define PIO0_P44 RP2XXX_PINMUX(44, RP2_PINCTRL_GPIO_FUNC_PIO0) +#define PIO0_P45 RP2XXX_PINMUX(45, RP2_PINCTRL_GPIO_FUNC_PIO0) +#define PIO0_P46 RP2XXX_PINMUX(46, RP2_PINCTRL_GPIO_FUNC_PIO0) +#define PIO0_P47 RP2XXX_PINMUX(47, RP2_PINCTRL_GPIO_FUNC_PIO0) + +#define PIO1_P30 RP2XXX_PINMUX(30, RP2_PINCTRL_GPIO_FUNC_PIO1) +#define PIO1_P31 RP2XXX_PINMUX(31, RP2_PINCTRL_GPIO_FUNC_PIO1) +#define PIO1_P32 RP2XXX_PINMUX(32, RP2_PINCTRL_GPIO_FUNC_PIO1) +#define PIO1_P33 RP2XXX_PINMUX(33, RP2_PINCTRL_GPIO_FUNC_PIO1) +#define PIO1_P34 RP2XXX_PINMUX(34, RP2_PINCTRL_GPIO_FUNC_PIO1) +#define PIO1_P35 RP2XXX_PINMUX(35, RP2_PINCTRL_GPIO_FUNC_PIO1) +#define PIO1_P36 RP2XXX_PINMUX(36, RP2_PINCTRL_GPIO_FUNC_PIO1) +#define PIO1_P37 RP2XXX_PINMUX(37, RP2_PINCTRL_GPIO_FUNC_PIO1) +#define PIO1_P38 RP2XXX_PINMUX(38, RP2_PINCTRL_GPIO_FUNC_PIO1) +#define PIO1_P39 RP2XXX_PINMUX(39, RP2_PINCTRL_GPIO_FUNC_PIO1) +#define PIO1_P40 RP2XXX_PINMUX(40, RP2_PINCTRL_GPIO_FUNC_PIO1) +#define PIO1_P41 RP2XXX_PINMUX(41, RP2_PINCTRL_GPIO_FUNC_PIO1) +#define PIO1_P42 RP2XXX_PINMUX(42, RP2_PINCTRL_GPIO_FUNC_PIO1) +#define PIO1_P43 RP2XXX_PINMUX(43, RP2_PINCTRL_GPIO_FUNC_PIO1) +#define PIO1_P44 RP2XXX_PINMUX(44, RP2_PINCTRL_GPIO_FUNC_PIO1) +#define PIO1_P45 RP2XXX_PINMUX(45, RP2_PINCTRL_GPIO_FUNC_PIO1) +#define PIO1_P46 RP2XXX_PINMUX(46, RP2_PINCTRL_GPIO_FUNC_PIO1) +#define PIO1_P47 RP2XXX_PINMUX(47, RP2_PINCTRL_GPIO_FUNC_PIO1) + +#define PIO2_P30 RP2XXX_PINMUX(30, RP2_PINCTRL_GPIO_FUNC_PIO2) +#define PIO2_P31 RP2XXX_PINMUX(31, RP2_PINCTRL_GPIO_FUNC_PIO2) +#define PIO2_P32 RP2XXX_PINMUX(32, RP2_PINCTRL_GPIO_FUNC_PIO2) +#define PIO2_P33 RP2XXX_PINMUX(33, RP2_PINCTRL_GPIO_FUNC_PIO2) +#define PIO2_P34 RP2XXX_PINMUX(34, RP2_PINCTRL_GPIO_FUNC_PIO2) +#define PIO2_P35 RP2XXX_PINMUX(35, RP2_PINCTRL_GPIO_FUNC_PIO2) +#define PIO2_P36 RP2XXX_PINMUX(36, RP2_PINCTRL_GPIO_FUNC_PIO2) +#define PIO2_P37 RP2XXX_PINMUX(37, RP2_PINCTRL_GPIO_FUNC_PIO2) +#define PIO2_P38 RP2XXX_PINMUX(38, RP2_PINCTRL_GPIO_FUNC_PIO2) +#define PIO2_P39 RP2XXX_PINMUX(39, RP2_PINCTRL_GPIO_FUNC_PIO2) +#define PIO2_P40 RP2XXX_PINMUX(40, RP2_PINCTRL_GPIO_FUNC_PIO2) +#define PIO2_P41 RP2XXX_PINMUX(41, RP2_PINCTRL_GPIO_FUNC_PIO2) +#define PIO2_P42 RP2XXX_PINMUX(42, RP2_PINCTRL_GPIO_FUNC_PIO2) +#define PIO2_P43 RP2XXX_PINMUX(43, RP2_PINCTRL_GPIO_FUNC_PIO2) +#define PIO2_P44 RP2XXX_PINMUX(44, RP2_PINCTRL_GPIO_FUNC_PIO2) +#define PIO2_P45 RP2XXX_PINMUX(45, RP2_PINCTRL_GPIO_FUNC_PIO2) +#define PIO2_P46 RP2XXX_PINMUX(46, RP2_PINCTRL_GPIO_FUNC_PIO2) +#define PIO2_P47 RP2XXX_PINMUX(47, RP2_PINCTRL_GPIO_FUNC_PIO2) + +#define GPIN0_P12 RP2XXX_PINMUX(12, RP2_PINCTRL_GPIO_FUNC_GPCK) +#define GPIN1_P14 RP2XXX_PINMUX(14, RP2_PINCTRL_GPIO_FUNC_GPCK) +#define GPIN0_P20 RP2XXX_PINMUX(20, RP2_PINCTRL_GPIO_FUNC_GPCK) +#define GPIN1_P22 RP2XXX_PINMUX(22, RP2_PINCTRL_GPIO_FUNC_GPCK) +#define GPOUT0_P13 RP2XXX_PINMUX(13, RP2_PINCTRL_GPIO_FUNC_GPCK) +#define GPOUT1_P15 RP2XXX_PINMUX(15, RP2_PINCTRL_GPIO_FUNC_GPCK) +#define GPOUT0_P21 RP2XXX_PINMUX(21, RP2_PINCTRL_GPIO_FUNC_GPCK) +#define GPOUT1_P23 RP2XXX_PINMUX(23, RP2_PINCTRL_GPIO_FUNC_GPCK) +#define GPOUT2_P24 RP2XXX_PINMUX(24, RP2_PINCTRL_GPIO_FUNC_GPCK) +#define GPOUT3_P25 RP2XXX_PINMUX(25, RP2_PINCTRL_GPIO_FUNC_GPCK) + +#define UART0_TX_P30 RP2XXX_PINMUX(30, RP2_PINCTRL_GPIO_FUNC_UART_ALT) +#define UART0_RX_P31 RP2XXX_PINMUX(31, RP2_PINCTRL_GPIO_FUNC_UART_ALT) +#define UART0_TX_P34 RP2XXX_PINMUX(34, RP2_PINCTRL_GPIO_FUNC_UART_ALT) +#define UART0_RX_P35 RP2XXX_PINMUX(35, RP2_PINCTRL_GPIO_FUNC_UART_ALT) +#define UART1_TX_P38 RP2XXX_PINMUX(38, RP2_PINCTRL_GPIO_FUNC_UART_ALT) +#define UART1_RX_P39 RP2XXX_PINMUX(39, RP2_PINCTRL_GPIO_FUNC_UART_ALT) +#define UART1_TX_P42 RP2XXX_PINMUX(42, RP2_PINCTRL_GPIO_FUNC_UART_ALT) +#define UART1_RX_P43 RP2XXX_PINMUX(43, RP2_PINCTRL_GPIO_FUNC_UART_ALT) +#define UART0_TX_P46 RP2XXX_PINMUX(46, RP2_PINCTRL_GPIO_FUNC_UART_ALT) +#define UART0_RX_P47 RP2XXX_PINMUX(47, RP2_PINCTRL_GPIO_FUNC_UART_ALT) + +/* ADC channel allocations differ between the RP2350A and RP2350B. + * Refer to Table 1116 in the datasheet. + */ +#define ADC_CH0_P40 RP2XXX_PINMUX(40, RP2_PINCTRL_GPIO_FUNC_NULL) +#define ADC_CH1_P41 RP2XXX_PINMUX(41, RP2_PINCTRL_GPIO_FUNC_NULL) +#define ADC_CH2_P42 RP2XXX_PINMUX(42, RP2_PINCTRL_GPIO_FUNC_NULL) +#define ADC_CH3_P43 RP2XXX_PINMUX(43, RP2_PINCTRL_GPIO_FUNC_NULL) +#define ADC_CH4_P44 RP2XXX_PINMUX(44, RP2_PINCTRL_GPIO_FUNC_NULL) +#define ADC_CH5_P45 RP2XXX_PINMUX(45, RP2_PINCTRL_GPIO_FUNC_NULL) +#define ADC_CH6_P46 RP2XXX_PINMUX(46, RP2_PINCTRL_GPIO_FUNC_NULL) +#define ADC_CH7_P47 RP2XXX_PINMUX(47, RP2_PINCTRL_GPIO_FUNC_NULL) + +#endif /* __RP2350B_PINCTRL_H__ */ diff --git a/soc/raspberrypi/rpi_pico/common/pinctrl_soc.h b/soc/raspberrypi/rpi_pico/common/pinctrl_soc.h index 8ee56c005e1b..03944058f771 100644 --- a/soc/raspberrypi/rpi_pico/common/pinctrl_soc.h +++ b/soc/raspberrypi/rpi_pico/common/pinctrl_soc.h @@ -7,7 +7,7 @@ #ifndef ZEPHYR_SOC_ARM_RPI_PICO_RP2_PINCTRL_SOC_H_ #define ZEPHYR_SOC_ARM_RPI_PICO_RP2_PINCTRL_SOC_H_ -#include +#include /** * @brief Type to hold a pin's pinctrl configuration. From 9d7db13655279c713ed4bb9a30f87d00bdd091e8 Mon Sep 17 00:00:00 2001 From: Andrew Featherstone Date: Wed, 21 Aug 2024 22:05:51 +0100 Subject: [PATCH 16/25] boards: Add initial support for the Raspberry Pi Pico 2 The Raspberry Pi Pico 2 is Raspberry Pi's first board fitted with their RP2350A SoC. This adds a minimal board definition, sufficient to build and run `samples/hello_world` and `samples/basic/blinky` on the board. Images can be run on the target using OpenOCD. Raspberry Pi's `picotool` can create a UF2 binary, which ensures that errata RP2350-E10 is avoided e.g. ``` > picotool uf2 convert build\rpi_pico2\hello_world\zephyr\zephyr.elf \ build\rpi_pico2\hello_world\zephyr\zephyr.uf2 \ --family rp2350-arm-s --abs-block` ``` Raspberry Pi Pico 2 is a low-cost, high-performance microcontroller board with flexible digital interfaces. Key features include: - RP2350A microcontroller chip designed by Raspberry Pi in the United Kingdom - Dual Cortex-M33 or Hazard3 processors at up to 150MHz - 520KB of SRAM, and 4MB of on-board flash memory - USB 1.1 with device and host support - Low-power sleep and dormant modes - Drag-and-drop programming using mass storage over USB - 26x multi-function GPIO pins including 3 that can be used for ADC - 2x SPI, 2x I2C, 2x UART, 3x 12-bit 500ksps Analogue to Digital Converter (ADC), 24x controllable PWM channels - 2x Timer with 4 alarms, 1x AON Timer - Temperature sensor - 3x Programmable IO (PIO) blocks, 12 state machines total for custom peripheral support - Flexible, user-programmable high-speed IO - Can emulate interfaces such as SD Card and VGA The Raspberry Pi Pico 2 comes as a castellated module which allows soldering direct to carrier boards. Signed-off-by: Andrew Featherstone --- boards/raspberrypi/common/rpi_pico-led.dtsi | 30 ++++ .../common/rpi_pico-pinctrl-common.dtsi | 57 +++++++ .../rpi_pico/rpi_pico-pinctrl.dtsi | 52 +------ boards/raspberrypi/rpi_pico/rpi_pico.dts | 25 +--- .../raspberrypi/rpi_pico2/Kconfig.defconfig | 9 ++ .../raspberrypi/rpi_pico2/Kconfig.rpi_pico2 | 5 + boards/raspberrypi/rpi_pico2/board.yml | 5 + .../rpi_pico2/rpi_pico2-pinctrl.dtsi | 8 + boards/raspberrypi/rpi_pico2/rpi_pico2.dts | 141 ++++++++++++++++++ boards/raspberrypi/rpi_pico2/rpi_pico2.yaml | 19 +++ .../raspberrypi/rpi_pico2/rpi_pico2_defconfig | 9 ++ 11 files changed, 285 insertions(+), 75 deletions(-) create mode 100644 boards/raspberrypi/common/rpi_pico-led.dtsi create mode 100644 boards/raspberrypi/common/rpi_pico-pinctrl-common.dtsi create mode 100644 boards/raspberrypi/rpi_pico2/Kconfig.defconfig create mode 100644 boards/raspberrypi/rpi_pico2/Kconfig.rpi_pico2 create mode 100644 boards/raspberrypi/rpi_pico2/board.yml create mode 100644 boards/raspberrypi/rpi_pico2/rpi_pico2-pinctrl.dtsi create mode 100644 boards/raspberrypi/rpi_pico2/rpi_pico2.dts create mode 100644 boards/raspberrypi/rpi_pico2/rpi_pico2.yaml create mode 100644 boards/raspberrypi/rpi_pico2/rpi_pico2_defconfig diff --git a/boards/raspberrypi/common/rpi_pico-led.dtsi b/boards/raspberrypi/common/rpi_pico-led.dtsi new file mode 100644 index 000000000000..951e36260f20 --- /dev/null +++ b/boards/raspberrypi/common/rpi_pico-led.dtsi @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2021 Yonatan Schachter + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* Pico and Pico 2 boards (but not Pico W) have a common LED placement. */ +/ { + leds { + compatible = "gpio-leds"; + led0: led_0 { + gpios = <&gpio0 25 GPIO_ACTIVE_HIGH>; + label = "LED"; + }; + }; + + pwm_leds { + compatible = "pwm-leds"; + status = "disabled"; + pwm_led0: pwm_led_0 { + pwms = <&pwm 9 PWM_MSEC(20) PWM_POLARITY_NORMAL>; + label = "PWM_LED"; + }; + }; + + aliases { + led0 = &led0; + pwm-led0 = &pwm_led0; + }; +}; diff --git a/boards/raspberrypi/common/rpi_pico-pinctrl-common.dtsi b/boards/raspberrypi/common/rpi_pico-pinctrl-common.dtsi new file mode 100644 index 000000000000..8d1c8ac83e7c --- /dev/null +++ b/boards/raspberrypi/common/rpi_pico-pinctrl-common.dtsi @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2021, Yonatan Schachter + * SPDX-License-Identifier: Apache-2.0 + */ + +/* The Pico and Pico 2 are pin compatible. */ +&pinctrl { + uart0_default: uart0_default { + group1 { + pinmux = ; + }; + group2 { + pinmux = ; + input-enable; + }; + }; + + i2c0_default: i2c0_default { + group1 { + pinmux = , ; + input-enable; + input-schmitt-enable; + }; + }; + + i2c1_default: i2c1_default { + group1 { + pinmux = , ; + input-enable; + input-schmitt-enable; + }; + }; + + spi0_default: spi0_default { + group1 { + pinmux = , , ; + }; + group2 { + pinmux = ; + input-enable; + }; + }; + + pwm_ch4b_default: pwm_ch4b_default { + group1 { + pinmux = ; + }; + }; + + adc_default: adc_default { + group1 { + pinmux = , , , ; + input-enable; + }; + }; + +}; diff --git a/boards/raspberrypi/rpi_pico/rpi_pico-pinctrl.dtsi b/boards/raspberrypi/rpi_pico/rpi_pico-pinctrl.dtsi index 443b68953bbe..5556638daa6d 100644 --- a/boards/raspberrypi/rpi_pico/rpi_pico-pinctrl.dtsi +++ b/boards/raspberrypi/rpi_pico/rpi_pico-pinctrl.dtsi @@ -5,54 +5,4 @@ #include -&pinctrl { - uart0_default: uart0_default { - group1 { - pinmux = ; - }; - group2 { - pinmux = ; - input-enable; - }; - }; - - i2c0_default: i2c0_default { - group1 { - pinmux = , ; - input-enable; - input-schmitt-enable; - }; - }; - - i2c1_default: i2c1_default { - group1 { - pinmux = , ; - input-enable; - input-schmitt-enable; - }; - }; - - spi0_default: spi0_default { - group1 { - pinmux = , , ; - }; - group2 { - pinmux = ; - input-enable; - }; - }; - - pwm_ch4b_default: pwm_ch4b_default { - group1 { - pinmux = ; - }; - }; - - adc_default: adc_default { - group1 { - pinmux = , , , ; - input-enable; - }; - }; - -}; +#include "../common/rpi_pico-pinctrl-common.dtsi" diff --git a/boards/raspberrypi/rpi_pico/rpi_pico.dts b/boards/raspberrypi/rpi_pico/rpi_pico.dts index 97d721024d74..807dc8e78005 100644 --- a/boards/raspberrypi/rpi_pico/rpi_pico.dts +++ b/boards/raspberrypi/rpi_pico/rpi_pico.dts @@ -7,27 +7,4 @@ /dts-v1/; #include "rpi_pico-common.dtsi" - -/ { - leds { - compatible = "gpio-leds"; - led0: led_0 { - gpios = <&gpio0 25 GPIO_ACTIVE_HIGH>; - label = "LED"; - }; - }; - - pwm_leds { - compatible = "pwm-leds"; - status = "disabled"; - pwm_led0: pwm_led_0 { - pwms = <&pwm 9 PWM_MSEC(20) PWM_POLARITY_NORMAL>; - label = "PWM_LED"; - }; - }; - - aliases { - led0 = &led0; - pwm-led0 = &pwm_led0; - }; -}; +#include "../common/rpi_pico-led.dtsi" diff --git a/boards/raspberrypi/rpi_pico2/Kconfig.defconfig b/boards/raspberrypi/rpi_pico2/Kconfig.defconfig new file mode 100644 index 000000000000..d122f3e4918a --- /dev/null +++ b/boards/raspberrypi/rpi_pico2/Kconfig.defconfig @@ -0,0 +1,9 @@ +# Copyright (c) 2024 Andrew Featherstone +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_RPI_PICO2 + +config USB_SELF_POWERED + default n + +endif # BOARD_RPI_PICO2 diff --git a/boards/raspberrypi/rpi_pico2/Kconfig.rpi_pico2 b/boards/raspberrypi/rpi_pico2/Kconfig.rpi_pico2 new file mode 100644 index 000000000000..be671dc208da --- /dev/null +++ b/boards/raspberrypi/rpi_pico2/Kconfig.rpi_pico2 @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Andrew Featherstone +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_RPI_PICO2 + select SOC_RP2350A diff --git a/boards/raspberrypi/rpi_pico2/board.yml b/boards/raspberrypi/rpi_pico2/board.yml new file mode 100644 index 000000000000..36d3cab0c884 --- /dev/null +++ b/boards/raspberrypi/rpi_pico2/board.yml @@ -0,0 +1,5 @@ +board: + name: rpi_pico2 + vendor: raspberrypi + socs: + - name: rp2350a diff --git a/boards/raspberrypi/rpi_pico2/rpi_pico2-pinctrl.dtsi b/boards/raspberrypi/rpi_pico2/rpi_pico2-pinctrl.dtsi new file mode 100644 index 000000000000..a7841dc2da6c --- /dev/null +++ b/boards/raspberrypi/rpi_pico2/rpi_pico2-pinctrl.dtsi @@ -0,0 +1,8 @@ +/* + * Copyright (c) 2024, Andrew Featherstone + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +#include "../common/rpi_pico-pinctrl-common.dtsi" diff --git a/boards/raspberrypi/rpi_pico2/rpi_pico2.dts b/boards/raspberrypi/rpi_pico2/rpi_pico2.dts new file mode 100644 index 000000000000..6a48442ee5a0 --- /dev/null +++ b/boards/raspberrypi/rpi_pico2/rpi_pico2.dts @@ -0,0 +1,141 @@ +/* + * Copyright (c) 2024 Andrew Featherstone + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include + +#include +#include + +#include + +#include "rpi_pico2-pinctrl.dtsi" +#include "../common/rpi_pico-led.dtsi" + +/ { + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,code-partition = &code_partition; + }; + + aliases { + watchdog0 = &wdt0; + }; + + pico_header: connector { + compatible = "raspberrypi,pico-header"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpio0 0 0>, /* GP0 */ + <1 0 &gpio0 1 0>, /* GP1 */ + <2 0 &gpio0 2 0>, /* GP2 */ + <3 0 &gpio0 3 0>, /* GP3 */ + <4 0 &gpio0 4 0>, /* GP4 */ + <5 0 &gpio0 5 0>, /* GP5 */ + <6 0 &gpio0 6 0>, /* GP6 */ + <7 0 &gpio0 7 0>, /* GP7 */ + <8 0 &gpio0 8 0>, /* GP8 */ + <9 0 &gpio0 9 0>, /* GP9 */ + <10 0 &gpio0 10 0>, /* GP10 */ + <11 0 &gpio0 11 0>, /* GP11 */ + <12 0 &gpio0 12 0>, /* GP12 */ + <13 0 &gpio0 13 0>, /* GP13 */ + <14 0 &gpio0 14 0>, /* GP14 */ + <15 0 &gpio0 15 0>, /* GP15 */ + <16 0 &gpio0 16 0>, /* GP16 */ + <17 0 &gpio0 17 0>, /* GP17 */ + <18 0 &gpio0 18 0>, /* GP18 */ + <19 0 &gpio0 19 0>, /* GP19 */ + <20 0 &gpio0 20 0>, /* GP20 */ + <21 0 &gpio0 21 0>, /* GP21 */ + <22 0 &gpio0 22 0>, /* GP22 */ + <26 0 &gpio0 26 0>, /* GP26 */ + <27 0 &gpio0 27 0>, /* GP27 */ + <28 0 &gpio0 28 0>; /* GP28 */ + }; +}; + +&flash0 { + reg = <0x10000000 DT_SIZE_M(4)>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserved memory for an image definition block. The block is much + * smaller than 256 bytes, but in practice the linker places the vector + * table at a much larger alignment offset. + */ + image_def: partition@0 { + label = "image_def"; + reg = <0x00000000 0x100>; + read-only; + }; + + /* + * Usable flash. Starts at 0x100, after the image definition block. + * The partition size is 4MB minus the 0x100 bytes taken by the + * image definition. + */ + code_partition: partition@100 { + label = "code-partition"; + reg = <0x100 (DT_SIZE_M(4) - 0x100)>; + read-only; + }; + }; +}; + +&uart0 { + current-speed = <115200>; + status = "okay"; + pinctrl-0 = <&uart0_default>; + pinctrl-names = "default"; +}; + +&gpio0 { + status = "okay"; +}; + +&spi0 { + clock-frequency = ; + pinctrl-0 = <&spi0_default>; + pinctrl-names = "default"; +}; + +&i2c0 { + clock-frequency = ; + pinctrl-0 = <&i2c0_default>; + pinctrl-names = "default"; +}; + +&i2c1 { + clock-frequency = ; + pinctrl-0 = <&i2c1_default>; + pinctrl-names = "default"; +}; + +&adc { + pinctrl-0 = <&adc_default>; + pinctrl-names = "default"; +}; + +&pwm { + pinctrl-0 = <&pwm_ch4b_default>; + pinctrl-names = "default"; + divider-int-0 = <255>; +}; + +zephyr_udc0: &usbd { + status = "okay"; +}; + +pico_serial: &uart0 {}; diff --git a/boards/raspberrypi/rpi_pico2/rpi_pico2.yaml b/boards/raspberrypi/rpi_pico2/rpi_pico2.yaml new file mode 100644 index 000000000000..ddc2ebaf4332 --- /dev/null +++ b/boards/raspberrypi/rpi_pico2/rpi_pico2.yaml @@ -0,0 +1,19 @@ +identifier: rpi_pico2 +name: Raspberry Pi Pico 2 +type: mcu +arch: arm +flash: 4096 +ram: 520 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - adc + - clock + - counter + - gpio + - hwinfo + - i2c + - spi + - uart diff --git a/boards/raspberrypi/rpi_pico2/rpi_pico2_defconfig b/boards/raspberrypi/rpi_pico2/rpi_pico2_defconfig new file mode 100644 index 000000000000..271bf5de90a2 --- /dev/null +++ b/boards/raspberrypi/rpi_pico2/rpi_pico2_defconfig @@ -0,0 +1,9 @@ +CONFIG_CLOCK_CONTROL=y +CONFIG_CONSOLE=y +CONFIG_GPIO=y +CONFIG_RESET=y +CONFIG_SERIAL=y +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=150000000 +CONFIG_UART_CONSOLE=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_USE_DT_CODE_PARTITION=y From 1bae56ad2d706fde9050a5b2eb8894725a47a6fb Mon Sep 17 00:00:00 2001 From: Ryan Grachek Date: Fri, 20 Sep 2024 17:18:33 +0100 Subject: [PATCH 17/25] UF2: Enable support for Raspberry Pi RP2350 Add UF2 Family ID for Raspberry Pi 2350 and build UF2 image by default for Pico 2 board Signed-off-by: Ryan Grachek Signed-off-by: Andrew Featherstone --- Kconfig.zephyr | 1 + boards/raspberrypi/rpi_pico2/board.cmake | 5 +++++ boards/raspberrypi/rpi_pico2/rpi_pico2_defconfig | 1 + scripts/build/uf2families.json | 5 +++++ soc/raspberrypi/rpi_pico/rp2350/Kconfig.defconfig | 3 +++ 5 files changed, 15 insertions(+) create mode 100644 boards/raspberrypi/rpi_pico2/board.cmake diff --git a/Kconfig.zephyr b/Kconfig.zephyr index c45329048812..4fdf13dc8531 100644 --- a/Kconfig.zephyr +++ b/Kconfig.zephyr @@ -767,6 +767,7 @@ config BUILD_OUTPUT_UF2_FAMILY_ID default "0x4fb2d5bd" if SOC_SERIES_IMXRT10XX || SOC_SERIES_IMXRT11XX default "0x2abc77ec" if SOC_SERIES_LPC55XXX default "0xe48bff56" if SOC_SERIES_RP2040 + default "0xe48bff57" if SOC_SERIES_RP2350 default "0x68ed2b88" if SOC_SERIES_SAMD21 default "0x55114460" if SOC_SERIES_SAMD51 default "0x647824b6" if SOC_SERIES_STM32F0X diff --git a/boards/raspberrypi/rpi_pico2/board.cmake b/boards/raspberrypi/rpi_pico2/board.cmake new file mode 100644 index 000000000000..c57bc2b04d87 --- /dev/null +++ b/boards/raspberrypi/rpi_pico2/board.cmake @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(uf2 "--board-id=RP2350") + +include(${ZEPHYR_BASE}/boards/common/uf2.board.cmake) \ No newline at end of file diff --git a/boards/raspberrypi/rpi_pico2/rpi_pico2_defconfig b/boards/raspberrypi/rpi_pico2/rpi_pico2_defconfig index 271bf5de90a2..16d269697d03 100644 --- a/boards/raspberrypi/rpi_pico2/rpi_pico2_defconfig +++ b/boards/raspberrypi/rpi_pico2/rpi_pico2_defconfig @@ -1,3 +1,4 @@ +CONFIG_BUILD_OUTPUT_UF2=y CONFIG_CLOCK_CONTROL=y CONFIG_CONSOLE=y CONFIG_GPIO=y diff --git a/scripts/build/uf2families.json b/scripts/build/uf2families.json index 14c8e5d043cb..10a8e4038c11 100644 --- a/scripts/build/uf2families.json +++ b/scripts/build/uf2families.json @@ -189,6 +189,11 @@ "short_name": "RP2040", "description": "Raspberry Pi RP2040" }, + { + "id": "0xe48bff57", + "short_name": "RP2350", + "description": "Raspberry Pi RP2350" + }, { "id": "0x00ff6919", "short_name": "STM32L4", diff --git a/soc/raspberrypi/rpi_pico/rp2350/Kconfig.defconfig b/soc/raspberrypi/rpi_pico/rp2350/Kconfig.defconfig index 3e59a9b98871..46b057490459 100644 --- a/soc/raspberrypi/rpi_pico/rp2350/Kconfig.defconfig +++ b/soc/raspberrypi/rpi_pico/rp2350/Kconfig.defconfig @@ -5,6 +5,9 @@ if SOC_SERIES_RP2350 +config BUILD_OUTPUT_UF2_USE_FLASH_BASE + default y if BUILD_OUTPUT_UF2 + config NUM_IRQS default 52 From a94b76ba0a1725de76a05503ff324516ce657966 Mon Sep 17 00:00:00 2001 From: Andrew Featherstone Date: Sat, 31 Aug 2024 21:34:24 +0100 Subject: [PATCH 18/25] samples: rpi_pico2: Add ADC-related samples for rpi_pico2 The Raspberry Pi Pico 2's device is compatible with the existing Pico 1. The build system requires a `.overlay` file, but these use the pre-processing to #include the sibling rpi_pico.overlay files rather than duplicating the contents as an attempt to keep things DRY. Tested locally. Signed-off-by: Andrew Featherstone --- samples/drivers/adc/adc_dt/boards/rpi_pico2.overlay | 12 ++++++++++++ .../sensor/die_temp_polling/boards/rpi_pico2.overlay | 11 +++++++++++ 2 files changed, 23 insertions(+) create mode 100644 samples/drivers/adc/adc_dt/boards/rpi_pico2.overlay create mode 100644 samples/sensor/die_temp_polling/boards/rpi_pico2.overlay diff --git a/samples/drivers/adc/adc_dt/boards/rpi_pico2.overlay b/samples/drivers/adc/adc_dt/boards/rpi_pico2.overlay new file mode 100644 index 000000000000..83e0805a85b4 --- /dev/null +++ b/samples/drivers/adc/adc_dt/boards/rpi_pico2.overlay @@ -0,0 +1,12 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + * + * Copyright (c) 2024 Andrew Featherstone + */ + +/* Pico 2 is compatible with the Pico 1, so reuse. */ +#include "rpi_pico.overlay" + +&adc { + status="okay"; +}; diff --git a/samples/sensor/die_temp_polling/boards/rpi_pico2.overlay b/samples/sensor/die_temp_polling/boards/rpi_pico2.overlay new file mode 100644 index 000000000000..c5791544bc4a --- /dev/null +++ b/samples/sensor/die_temp_polling/boards/rpi_pico2.overlay @@ -0,0 +1,11 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + * + * Copyright (c) 2024 Andrew Featherstone + */ + +#include "rpi_pico.overlay" + +&adc { + status="okay"; +}; From 32f4df749fc933f8ead0f3c36e5b619a6dcc9b53 Mon Sep 17 00:00:00 2001 From: Andrew Featherstone Date: Tue, 3 Sep 2024 17:27:30 +0100 Subject: [PATCH 19/25] tests: drivers: adc_api: Add support for the Raspberry Pi Pico 2 For these tests' needs, the RP2350 on the Pico 2 is compatible with the RP2040 on the Pico 1. #include the latter's overlay in preference to duplicating the content. Signed-off-by: Andrew Featherstone --- tests/drivers/adc/adc_api/boards/rpi_pico2.overlay | 12 ++++++++++++ 1 file changed, 12 insertions(+) create mode 100644 tests/drivers/adc/adc_api/boards/rpi_pico2.overlay diff --git a/tests/drivers/adc/adc_api/boards/rpi_pico2.overlay b/tests/drivers/adc/adc_api/boards/rpi_pico2.overlay new file mode 100644 index 000000000000..83e0805a85b4 --- /dev/null +++ b/tests/drivers/adc/adc_api/boards/rpi_pico2.overlay @@ -0,0 +1,12 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + * + * Copyright (c) 2024 Andrew Featherstone + */ + +/* Pico 2 is compatible with the Pico 1, so reuse. */ +#include "rpi_pico.overlay" + +&adc { + status="okay"; +}; From ff899d4d00d8da33eeda22677d0485c420b62e18 Mon Sep 17 00:00:00 2001 From: Andrew Featherstone Date: Wed, 25 Sep 2024 12:28:57 +0100 Subject: [PATCH 20/25] tests: drivers: counter_basic_api: Add support for the Raspberry Pi Pico 2 Only enable timer 0 for testing. Timer 1 won't work correctly until the rpi_pico HAL has picked up the fix for `hardware_alarm_irq_handler`. See https://github.com/raspberrypi/pico-sdk/pull/1949 . Signed-off-by: Andrew Featherstone --- .../counter/counter_basic_api/boards/rpi_pico2.overlay | 9 +++++++++ 1 file changed, 9 insertions(+) create mode 100644 tests/drivers/counter/counter_basic_api/boards/rpi_pico2.overlay diff --git a/tests/drivers/counter/counter_basic_api/boards/rpi_pico2.overlay b/tests/drivers/counter/counter_basic_api/boards/rpi_pico2.overlay new file mode 100644 index 000000000000..8da49f3a439c --- /dev/null +++ b/tests/drivers/counter/counter_basic_api/boards/rpi_pico2.overlay @@ -0,0 +1,9 @@ +/* + * Copyright (c) 2024 Andrew Featherstone + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&timer0 { + status = "okay"; +}; From bd3c339e489b199acc356600d826ba2efbbecbf3 Mon Sep 17 00:00:00 2001 From: Andrew Featherstone Date: Sat, 31 Aug 2024 16:50:38 +0100 Subject: [PATCH 21/25] doc: rpi_pico2: Document Raspberry Pi Pico 2 and related changes Add some documentation for the board itself (mostly aiming to refer to canonical sources of information rather duplicate). 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zh@sb$1}$taBmv3mUwnWPXsh{G``##?k;GT*IGj{kNMTtUIGs!m3L|9ARrqAi#^GtDtZ6@25l2OWZA0YJQ{a4!5~DAAw`NDT@_yy8io5tPl20)=yG7^o5} z2N63{o4rqHhLE(>*#dDKaTd0|KkF2NFH<*413v)U^TrKB`N!`LTI*@_T|Z|M4Z0jg zpB2&X8k)3hq8FfacV6&oT?4k!7k``9HBHqT1eN% z={){&h(!h9zCpeYQ1v-b0RVCKlsRqT!_Qtv@!z92m61f>TxB=Xp?jMD08YFr{{RR) z`7dLv6?Fi-{VT+V?y&S-_!%FYn_DxQe~6 zJnND6#vY-nmG4Th zYHXV{>mj3I)Lm@c;`+rRKr=`kK7;}#9V3-8nu<6>tLs|L*MJL8SH^732HNVq0GGq( z7?u3#q<$?v*hMfU-nDRxg;EAvz)^_-&-b4XzvxfzC;AP7GkSMz$ixbGB2fE><26tf zE}-xx_wRgQ4%JOvcxSO5rtWISqry<<_f_URRaw&nr=Rupw~>BpjA#podU#6p6rO0g!pkDMBo)LEw^ z#c?WWEDDOIjFhb?hn>(){c8}16Y+Ow?z`_32@ox3zx#_qqve0hn5peXf9^WB2<#)t zvG9H|VbNz?f(Jj&@FPjdgYw{8cpjA$`J4FqRm@Rj`$o^sB9tmApNs`17rg$m82;8z zzj#crct4gI0`>m@EL;5FtN;d_JRhtA05k!kJ>bMYW_p>({)|B*vnZK+SM`o6uPA>E zXpPB(_HYgd{dmcLgY}OoKgWy`Kjih4uqCx07*J;;Y4LH`>ysZ5zrPvjMUndd0R7+p E*`$~(!T`_ is referred to as Pico 2. + +.. figure:: img/pico-2.jpg + :align: center + :alt: Raspberry Pi Pico 2 + + Raspberry Pi Pico 2 (Credit: Raspberry Pi Ltd) + +Hardware +******** + +- Dual Cortex-M33 or Hazard3 processors at up to 150MHz +- 520KB of SRAM, and 4MB of on-board flash memory +- USB 1.1 with device and host support +- Low-power sleep and dormant modes +- Drag-and-drop programming using mass storage over USB +- 26 multi-function GPIO pins including 3 that can be used for ADC +- 2 SPI, 2 I2C, 2 UART, 3 12-bit 500ksps Analogue to Digital - Converter (ADC), 24 controllable PWM channels +- 2 Timer with 4 alarms, 1 AON Timer +- Temperature sensor +- 3 Programmable IO (PIO) blocks, 12 state machines total for custom peripheral support + - Flexible, user-programmable high-speed IO + - Can emulate interfaces such as SD Card and VGA + +Supported Features +================== + +The rpi_pico board configuration supports the following +hardware features: + +.. list-table:: + :header-rows: 1 + + * - Peripheral + - Kconfig option + - Devicetree compatible + * - NVIC + - N/A + - :dtcompatible:`arm,v8m-nvic` + * - ADC + - :kconfig:option:`CONFIG_ADC` + - :dtcompatible:`raspberrypi,pico-adc` + * - Clock controller + - :kconfig:option:`CONFIG_CLOCK_CONTROL` + - :dtcompatible:`raspberrypi,pico-clock-controller` + * - Counter + - :kconfig:option:`CONFIG_COUNTER` + - :dtcompatible:`raspberrypi,pico-timer` + * - GPIO + - :kconfig:option:`CONFIG_GPIO` + - :dtcompatible:`raspberrypi,pico-gpio` + * - HWINFO + - :kconfig:option:`CONFIG_HWINFO` + - N/A + * - I2C + - :kconfig:option:`CONFIG_I2C` + - :dtcompatible:`snps,designware-i2c` + * - PWM + - :kconfig:option:`CONFIG_PWM` + - :dtcompatible:`raspberrypi,pico-pwm` + * - SPI + - :kconfig:option:`CONFIG_SPI` + - :dtcompatible:`raspberrypi,pico-spi` + * - UART + - :kconfig:option:`CONFIG_SERIAL` + - :dtcompatible:`raspberrypi,pico-uart` + +Connections and IOs +=================== + +The default pin mapping is unchanged from the Pico 1. + +Programming and Debugging +************************* + +As with the Pico 1, the SWD interface can be used to program and debug the +device, e.g. using OpenOCD with the `Raspberry Pi Debug Probe `_ . + +References +********** + +- https://www.raspberrypi.com/documentation/microcontrollers/pico-series.html +- https://www.raspberrypi.com/documentation/microcontrollers/debug-probe.html diff --git a/doc/releases/migration-guide-4.0.rst b/doc/releases/migration-guide-4.0.rst index 1cc6a122af17..4a52d242173d 100644 --- a/doc/releases/migration-guide-4.0.rst +++ b/doc/releases/migration-guide-4.0.rst @@ -31,7 +31,7 @@ Boards :ref:`native_sim` (:github:`76898`). * Nordic nRF53 and nRF91 based boards can use the common devicetree overlays in ``dts/common/nordic`` to define default flash and ram partitioning based on TF-M. - +* Raspberry Pi: ``CONFIG_SOC_SERIES_RP2XXX`` is renamed to :kconfig:option:`CONFIG_SOC_SERIES_RP2040`. * STM32WBA: The command used for fetching blobs required to build ble applications is now ``west blobs fetch hal_stm32`` instead of ``west blobs fetch stm32``. diff --git a/doc/releases/release-notes-4.0.rst b/doc/releases/release-notes-4.0.rst index b5bcacdb9e5c..9518744cba78 100644 --- a/doc/releases/release-notes-4.0.rst +++ b/doc/releases/release-notes-4.0.rst @@ -111,6 +111,8 @@ Boards & SoC Support * Added support for these SoC series: + * Raspberry Pi RP2350 + * Made these changes in other SoC series: * NXP S32Z270: Added support for the new silicon cut version 2.0. Note that the previous @@ -118,6 +120,8 @@ Boards & SoC Support * Added support for these boards: + * :ref:`Raspberry Pi Pico 2 `: ``rpi_pico2``. + * Made these board changes: * :ref:`native_posix` has been deprecated in favour of From 8d691cc90cde295899a159359ddebd187fda461e Mon Sep 17 00:00:00 2001 From: Andrew Featherstone Date: Fri, 27 Sep 2024 19:03:10 +0100 Subject: [PATCH 22/25] boards: raspberrypi: rpi_pico2: add OpenOCD runner configuration Add OpenOCD debugger support. For now we will need a RaspberryPi forked version of OpenOCD. https://github.com/raspberrypi/openocd Signed-off-by: TOKITA Hiroshi Signed-off-by: Andrew Featherstone --- boards/raspberrypi/rpi_pico2/board.cmake | 15 ++++++++++++++- boards/raspberrypi/rpi_pico2/rpi_pico2_defconfig | 1 + boards/raspberrypi/rpi_pico2/support/openocd.cfg | 11 +++++++++++ 3 files changed, 26 insertions(+), 1 deletion(-) create mode 100644 boards/raspberrypi/rpi_pico2/support/openocd.cfg diff --git a/boards/raspberrypi/rpi_pico2/board.cmake b/boards/raspberrypi/rpi_pico2/board.cmake index c57bc2b04d87..5e6d859dff36 100644 --- a/boards/raspberrypi/rpi_pico2/board.cmake +++ b/boards/raspberrypi/rpi_pico2/board.cmake @@ -1,5 +1,18 @@ # SPDX-License-Identifier: Apache-2.0 +if ("${RPI_PICO_DEBUG_ADAPTER}" STREQUAL "") + set(RPI_PICO_DEBUG_ADAPTER "cmsis-dap") +endif() + +board_runner_args(openocd --cmd-pre-init "source [find interface/${RPI_PICO_DEBUG_ADAPTER}.cfg]") +board_runner_args(openocd --cmd-pre-init "transport select swd") +board_runner_args(openocd --cmd-pre-init "source [find target/rp2350.cfg]") + +# The adapter speed is expected to be set by interface configuration. +# But if not so, set 2000 to adapter speed. +board_runner_args(openocd --cmd-pre-init "set_adapter_speed_if_not_set 2000") + board_runner_args(uf2 "--board-id=RP2350") -include(${ZEPHYR_BASE}/boards/common/uf2.board.cmake) \ No newline at end of file +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/uf2.board.cmake) diff --git a/boards/raspberrypi/rpi_pico2/rpi_pico2_defconfig b/boards/raspberrypi/rpi_pico2/rpi_pico2_defconfig index 16d269697d03..d47066f1a8a1 100644 --- a/boards/raspberrypi/rpi_pico2/rpi_pico2_defconfig +++ b/boards/raspberrypi/rpi_pico2/rpi_pico2_defconfig @@ -1,3 +1,4 @@ +CONFIG_BUILD_OUTPUT_HEX=y CONFIG_BUILD_OUTPUT_UF2=y CONFIG_CLOCK_CONTROL=y CONFIG_CONSOLE=y diff --git a/boards/raspberrypi/rpi_pico2/support/openocd.cfg b/boards/raspberrypi/rpi_pico2/support/openocd.cfg new file mode 100644 index 000000000000..82666bb53314 --- /dev/null +++ b/boards/raspberrypi/rpi_pico2/support/openocd.cfg @@ -0,0 +1,11 @@ +# Copyright (c) 2024 TOKITA Hiroshi +# SPDX-License-Identifier: Apache-2.0 + +# Checking and set 'adapter speed'. +# Set the adaptor speed, if unset, and given as an argument. +proc set_adapter_speed_if_not_set { speed } { + puts "checking adapter speed..." + if { [catch {adapter speed} ret] } { + adapter speed $speed + } +} From db604cadb9c64c9088cd39950c86d5d4301c6ea6 Mon Sep 17 00:00:00 2001 From: Andrew Featherstone Date: Fri, 27 Sep 2024 20:00:58 +0100 Subject: [PATCH 23/25] boards: raspberrypi: rpi_pico2: Tidy up OpenOCD configuration - Remove redundant `transport select swd`. This is already done in `interface/rp2350.cfg` - Set the adapter speed to match Raspberry Pi's documentation. Signed-off-by: Andrew Featherstone --- boards/raspberrypi/rpi_pico2/board.cmake | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/boards/raspberrypi/rpi_pico2/board.cmake b/boards/raspberrypi/rpi_pico2/board.cmake index 5e6d859dff36..686fbd9d40e3 100644 --- a/boards/raspberrypi/rpi_pico2/board.cmake +++ b/boards/raspberrypi/rpi_pico2/board.cmake @@ -5,12 +5,12 @@ if ("${RPI_PICO_DEBUG_ADAPTER}" STREQUAL "") endif() board_runner_args(openocd --cmd-pre-init "source [find interface/${RPI_PICO_DEBUG_ADAPTER}.cfg]") -board_runner_args(openocd --cmd-pre-init "transport select swd") board_runner_args(openocd --cmd-pre-init "source [find target/rp2350.cfg]") # The adapter speed is expected to be set by interface configuration. -# But if not so, set 2000 to adapter speed. -board_runner_args(openocd --cmd-pre-init "set_adapter_speed_if_not_set 2000") +# The Raspberry Pi's OpenOCD fork doesn't, so match their documentation at +# https://www.raspberrypi.com/documentation/microcontrollers/debug-probe.html#debugging-with-swd +board_runner_args(openocd --cmd-pre-init "set_adapter_speed_if_not_set 5000") board_runner_args(uf2 "--board-id=RP2350") From 48e8648ce0f4ef0396ffab998014138a903a5d20 Mon Sep 17 00:00:00 2001 From: Andrew Featherstone Date: Fri, 4 Oct 2024 15:44:29 +0100 Subject: [PATCH 24/25] tests: gpio_api_1pin: rpi_pico2: Support using external pulldowns Extend gpio_api_1pin so that tests can require a test fixture to provide an external pulldown resistor to the board under test. Use the new test-gpio-external-pulldown device tree binding to define where that GPIO is, and, finally, add a device tree overlay for the Raspberry Pi Pico 2 board that defines where the pulldown provided by the fixture will be. Tested locally using `--fixture gpio_external_pull_down` when running Twister on the command line, or by creating and using a Hardware Map file, in combination with a modified Pico 2. Signed-off-by: Andrew Featherstone --- .../gpio_api_1pin/boards/rpi_pico2.overlay | 13 ++++++++++++ .../bindings/test-gpio-external-pulldown.yaml | 18 ++++++++++++++++ .../gpio/gpio_api_1pin/src/test_gpio_api.h | 16 ++++++++++---- .../drivers/gpio/gpio_api_1pin/testcase.yaml | 21 +++++++++++++------ 4 files changed, 58 insertions(+), 10 deletions(-) create mode 100644 tests/drivers/gpio/gpio_api_1pin/boards/rpi_pico2.overlay create mode 100644 tests/drivers/gpio/gpio_api_1pin/dts/bindings/test-gpio-external-pulldown.yaml diff --git a/tests/drivers/gpio/gpio_api_1pin/boards/rpi_pico2.overlay b/tests/drivers/gpio/gpio_api_1pin/boards/rpi_pico2.overlay new file mode 100644 index 000000000000..6bfb9f711f75 --- /dev/null +++ b/tests/drivers/gpio/gpio_api_1pin/boards/rpi_pico2.overlay @@ -0,0 +1,13 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + * + * Copyright (c) 2024 Andrew Featherstone + */ + +/ { + resources { + compatible = "test-gpio-external-pulldown"; + /* Choice of pin on the header is arbitrary. */ + gpios = <&pico_header 15 GPIO_ACTIVE_HIGH>; + }; +}; diff --git a/tests/drivers/gpio/gpio_api_1pin/dts/bindings/test-gpio-external-pulldown.yaml b/tests/drivers/gpio/gpio_api_1pin/dts/bindings/test-gpio-external-pulldown.yaml new file mode 100644 index 000000000000..4534b20f7e25 --- /dev/null +++ b/tests/drivers/gpio/gpio_api_1pin/dts/bindings/test-gpio-external-pulldown.yaml @@ -0,0 +1,18 @@ +# +# Copyright (c) 2024 Andrew Featherstone +# +# SPDX-License-Identifier: Apache-2.0 +# + +description: | + This binding provides resources required to build and run the + tests/drivers/gpio/gpio_api_1pin test in Zephyr on certain hardware. + +compatible: "test-gpio-external-pulldown" + +properties: + gpios: + type: phandle-array + required: true + description: | + Identity of a GPIO that will be configured as both an output and input. diff --git a/tests/drivers/gpio/gpio_api_1pin/src/test_gpio_api.h b/tests/drivers/gpio/gpio_api_1pin/src/test_gpio_api.h index 024c9d1a9db2..c001c2026bcd 100644 --- a/tests/drivers/gpio/gpio_api_1pin/src/test_gpio_api.h +++ b/tests/drivers/gpio/gpio_api_1pin/src/test_gpio_api.h @@ -11,10 +11,18 @@ #include #include -#if DT_NODE_HAS_PROP(DT_ALIAS(led0), gpios) -#define TEST_NODE DT_GPIO_CTLR(DT_ALIAS(led0), gpios) -#define TEST_PIN DT_GPIO_PIN(DT_ALIAS(led0), gpios) -#define TEST_PIN_DTS_FLAGS DT_GPIO_FLAGS(DT_ALIAS(led0), gpios) +/* If possible, use a dedicated GPIO with an external pulldown resistor. + * Otherwise, fallback to repurposing led0 as a GPIO. The latter won't always + * work as expected when reconfigured as an input. + */ +#if DT_NODE_HAS_STATUS(DT_INST(0, test_gpio_external_pulldown), okay) +#define TEST_NODE DT_GPIO_CTLR(DT_INST(0, test_gpio_external_pulldown), gpios) +#define TEST_PIN DT_GPIO_PIN(DT_INST(0, test_gpio_external_pulldown), gpios) +#define TEST_PIN_DTS_FLAGS DT_GPIO_FLAGS(DT_INST(0, test_gpio_external_pulldown), gpios) +#elif DT_NODE_HAS_PROP(DT_ALIAS(led0), gpios) +#define TEST_NODE DT_GPIO_CTLR(DT_ALIAS(led0), gpios) +#define TEST_PIN DT_GPIO_PIN(DT_ALIAS(led0), gpios) +#define TEST_PIN_DTS_FLAGS DT_GPIO_FLAGS(DT_ALIAS(led0), gpios) #else #error Unsupported board #endif diff --git a/tests/drivers/gpio/gpio_api_1pin/testcase.yaml b/tests/drivers/gpio/gpio_api_1pin/testcase.yaml index 1c5c6f9eb7f9..0380ed1eafff 100644 --- a/tests/drivers/gpio/gpio_api_1pin/testcase.yaml +++ b/tests/drivers/gpio/gpio_api_1pin/testcase.yaml @@ -1,13 +1,22 @@ +common: + tags: + - drivers + - gpio + depends_on: gpio + min_flash: 48 tests: drivers.gpio.1pin: - tags: - - drivers - - gpio - depends_on: gpio - min_flash: 48 + filter: > + dt_enabled_alias_with_parent_compat("led0", "gpio-leds") + and not dt_compat_enabled("test-gpio-external-pulldown") # Fix exclude when we can exclude just sim run platform_exclude: - mps2/an385 - mps2/an521/cpu0 - neorv32 - filter: dt_enabled_alias_with_parent_compat("led0", "gpio-leds") + drivers.gpio.1pin.external_pull_down: + # For testing boards that require a test fixture that provides a pulldown + # resistor on the GPIO used for the test. + filter: dt_compat_enabled("test-gpio-external-pulldown") + harness_config: + fixture: gpio_external_pull_down From 46bec148c1d0675a0f24c953aacc351d3c8e5321 Mon Sep 17 00:00:00 2001 From: TOKITA Hiroshi Date: Sun, 6 Oct 2024 07:19:09 +0900 Subject: [PATCH 25/25] dts: arm: raspberrypi: rpi_pico: rp2350: Add DMA configuration Add configuration for `dma`. Signed-off-by: TOKITA Hiroshi --- boards/raspberrypi/rpi_pico2/rpi_pico2.yaml | 1 + dts/arm/raspberrypi/rpi_pico/rp2350.dtsi | 16 ++++++++++++++++ 2 files changed, 17 insertions(+) diff --git a/boards/raspberrypi/rpi_pico2/rpi_pico2.yaml b/boards/raspberrypi/rpi_pico2/rpi_pico2.yaml index ddc2ebaf4332..832ed6dc8641 100644 --- a/boards/raspberrypi/rpi_pico2/rpi_pico2.yaml +++ b/boards/raspberrypi/rpi_pico2/rpi_pico2.yaml @@ -17,3 +17,4 @@ supported: - i2c - spi - uart + - dma diff --git a/dts/arm/raspberrypi/rpi_pico/rp2350.dtsi b/dts/arm/raspberrypi/rpi_pico/rp2350.dtsi index b5a066f37158..ad91a98bbe2e 100644 --- a/dts/arm/raspberrypi/rpi_pico/rp2350.dtsi +++ b/dts/arm/raspberrypi/rpi_pico/rp2350.dtsi @@ -373,6 +373,22 @@ status = "disabled"; }; + dma: dma@50000000 { + compatible = "raspberrypi,pico-dma"; + reg = <0x50000000 DT_SIZE_K(64)>; + resets = <&reset RPI_PICO_RESETS_RESET_DMA>; + clocks = <&clocks RPI_PICO_CLKID_CLK_SYS>; + interrupts = <10 RPI_PICO_DEFAULT_IRQ_PRIORITY>, + <11 RPI_PICO_DEFAULT_IRQ_PRIORITY>, + <12 RPI_PICO_DEFAULT_IRQ_PRIORITY>, + <13 RPI_PICO_DEFAULT_IRQ_PRIORITY>; + interrupt-names = "dma0", "dma1", "dma2", "dma3"; + dma-channels = <16>; + irq0-channels = [00 02 04 06 08 0a 0c 0e]; + status = "disabled"; + #dma-cells = <3>; + }; + usbd: usbd@50100000 { compatible = "raspberrypi,pico-usbd"; reg = <0x50100000 0x10000>;